{"id":"https://openalex.org/W3118338221","doi":"https://doi.org/10.1109/tcsi.2020.3046524","title":"LAYGO: A Template-and-Grid-Based Layout Generation Engine for Advanced CMOS Technologies","display_name":"LAYGO: A Template-and-Grid-Based Layout Generation Engine for Advanced CMOS Technologies","publication_year":2021,"publication_date":"2021-01-05","ids":{"openalex":"https://openalex.org/W3118338221","doi":"https://doi.org/10.1109/tcsi.2020.3046524","mag":"3118338221"},"language":"en","primary_location":{"id":"doi:10.1109/tcsi.2020.3046524","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tcsi.2020.3046524","pdf_url":null,"source":{"id":"https://openalex.org/S116977442","display_name":"IEEE Transactions on Circuits and Systems I Regular Papers","issn_l":"1549-8328","issn":["1549-8328","1558-0806"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Circuits and Systems I: Regular Papers","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5056788062","display_name":"Jaeduk Han","orcid":"https://orcid.org/0000-0002-2292-7670"},"institutions":[{"id":"https://openalex.org/I4575257","display_name":"Hanyang University","ror":"https://ror.org/046865y68","country_code":"KR","type":"education","lineage":["https://openalex.org/I4575257"]}],"countries":["KR"],"is_corresponding":false,"raw_author_name":"Jaeduk Han","raw_affiliation_strings":["Department of Electronic Engineering, Hanyang University, Seoul, South Korea"],"raw_orcid":"https://orcid.org/0000-0002-2292-7670","affiliations":[{"raw_affiliation_string":"Department of Electronic Engineering, Hanyang University, Seoul, South Korea","institution_ids":["https://openalex.org/I4575257"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5084764827","display_name":"Woorham Bae","orcid":"https://orcid.org/0000-0002-9274-0182"},"institutions":[{"id":"https://openalex.org/I4210138881","display_name":"Ayar Labs (United States)","ror":"https://ror.org/03rgkeg55","country_code":"US","type":"company","lineage":["https://openalex.org/I4210138881"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Woorham Bae","raw_affiliation_strings":["Ayar Labs, Santa Clara, CA, USA"],"raw_orcid":"https://orcid.org/0000-0002-9274-0182","affiliations":[{"raw_affiliation_string":"Ayar Labs, Santa Clara, CA, USA","institution_ids":["https://openalex.org/I4210138881"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5101826331","display_name":"Eric Chang","orcid":"https://orcid.org/0000-0001-7672-4038"},"institutions":[{"id":"https://openalex.org/I95457486","display_name":"University of California, Berkeley","ror":"https://ror.org/01an7q238","country_code":"US","type":"education","lineage":["https://openalex.org/I95457486"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Eric Chang","raw_affiliation_strings":["Department of Electrical Engineering and Computer Sciences, University of California at Berkeley, Berkeley, CA, USA"],"raw_orcid":"https://orcid.org/0000-0001-7672-4038","affiliations":[{"raw_affiliation_string":"Department of Electrical Engineering and Computer Sciences, University of California at Berkeley, Berkeley, CA, USA","institution_ids":["https://openalex.org/I95457486"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5101804913","display_name":"Zhongkai Wang","orcid":"https://orcid.org/0009-0006-5622-5366"},"institutions":[{"id":"https://openalex.org/I95457486","display_name":"University of California, Berkeley","ror":"https://ror.org/01an7q238","country_code":"US","type":"education","lineage":["https://openalex.org/I95457486"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Zhongkai Wang","raw_affiliation_strings":["Department of Electrical Engineering and Computer Sciences, University of California at Berkeley, Berkeley, CA, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Electrical Engineering and Computer Sciences, University of California at Berkeley, Berkeley, CA, USA","institution_ids":["https://openalex.org/I95457486"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5041784384","display_name":"Borivoje Nikoli\u0107","orcid":"https://orcid.org/0000-0003-2324-1715"},"institutions":[{"id":"https://openalex.org/I95457486","display_name":"University of California, Berkeley","ror":"https://ror.org/01an7q238","country_code":"US","type":"education","lineage":["https://openalex.org/I95457486"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Borivoje Nikolic","raw_affiliation_strings":["Department of Electrical Engineering and Computer Sciences, University of California at Berkeley, Berkeley, CA, USA"],"raw_orcid":"https://orcid.org/0000-0003-2324-1715","affiliations":[{"raw_affiliation_string":"Department of Electrical Engineering and Computer Sciences, University of California at Berkeley, Berkeley, CA, USA","institution_ids":["https://openalex.org/I95457486"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5110516457","display_name":"Elad Alon","orcid":null},"institutions":[{"id":"https://openalex.org/I95457486","display_name":"University of California, Berkeley","ror":"https://ror.org/01an7q238","country_code":"US","type":"education","lineage":["https://openalex.org/I95457486"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Elad Alon","raw_affiliation_strings":["Department of Electrical Engineering and Computer Sciences, University of California at Berkeley, Berkeley, CA, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Electrical Engineering and Computer Sciences, University of California at Berkeley, Berkeley, CA, USA","institution_ids":["https://openalex.org/I95457486"]}]}],"institutions":[],"countries_distinct_count":2,"institutions_distinct_count":6,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":2.6442,"has_fulltext":false,"cited_by_count":30,"citation_normalized_percentile":{"value":0.90012828,"is_in_top_1_percent":false,"is_in_top_10_percent":true},"cited_by_percentile_year":{"min":95,"max":99},"biblio":{"volume":"68","issue":"3","first_page":"1012","last_page":"1022"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11527","display_name":"3D IC and TSV technologies","score":0.9995999932289124,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9994000196456909,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/cmos","display_name":"CMOS","score":0.6518636345863342},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6323451399803162},{"id":"https://openalex.org/keywords/software-portability","display_name":"Software portability","score":0.5234231948852539},{"id":"https://openalex.org/keywords/grid","display_name":"Grid","score":0.4644489288330078},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.446031391620636},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.339338481426239},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.3353261947631836},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.2162325382232666}],"concepts":[{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.6518636345863342},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6323451399803162},{"id":"https://openalex.org/C63000827","wikidata":"https://www.wikidata.org/wiki/Q3080428","display_name":"Software portability","level":2,"score":0.5234231948852539},{"id":"https://openalex.org/C187691185","wikidata":"https://www.wikidata.org/wiki/Q2020720","display_name":"Grid","level":2,"score":0.4644489288330078},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.446031391620636},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.339338481426239},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.3353261947631836},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.2162325382232666},{"id":"https://openalex.org/C2524010","wikidata":"https://www.wikidata.org/wiki/Q8087","display_name":"Geometry","level":1,"score":0.0},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.0},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/tcsi.2020.3046524","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tcsi.2020.3046524","pdf_url":null,"source":{"id":"https://openalex.org/S116977442","display_name":"IEEE Transactions on Circuits and Systems I Regular Papers","issn_l":"1549-8328","issn":["1549-8328","1558-0806"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Circuits and Systems I: Regular Papers","raw_type":"journal-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":34,"referenced_works":["https://openalex.org/W1506322852","https://openalex.org/W1666015432","https://openalex.org/W1967575124","https://openalex.org/W1983740965","https://openalex.org/W1996605065","https://openalex.org/W2030300946","https://openalex.org/W2064465719","https://openalex.org/W2074590526","https://openalex.org/W2089267425","https://openalex.org/W2104823269","https://openalex.org/W2113142084","https://openalex.org/W2116989584","https://openalex.org/W2121545913","https://openalex.org/W2126996785","https://openalex.org/W2146519106","https://openalex.org/W2162975204","https://openalex.org/W2171146006","https://openalex.org/W2242139250","https://openalex.org/W2496172083","https://openalex.org/W2534626369","https://openalex.org/W2592547566","https://openalex.org/W2745002353","https://openalex.org/W2799036521","https://openalex.org/W2801370963","https://openalex.org/W2912937848","https://openalex.org/W2926344714","https://openalex.org/W2945221971","https://openalex.org/W2966289590","https://openalex.org/W4236728296","https://openalex.org/W4247888923","https://openalex.org/W4253367659","https://openalex.org/W6675609000","https://openalex.org/W6734095656","https://openalex.org/W6742841919"],"related_works":["https://openalex.org/W107105315","https://openalex.org/W4367156293","https://openalex.org/W1584537303","https://openalex.org/W4388155270","https://openalex.org/W1872724644","https://openalex.org/W2750549761","https://openalex.org/W28826848","https://openalex.org/W2122272819","https://openalex.org/W2130894091","https://openalex.org/W2994151208"],"abstract_inverted_index":{"LAYout":[0],"with":[1,91,111],"Gridded":[2],"Objects":[3],"(LAYGO),":[4],"a":[5,28,35,140,149],"Python-based":[6],"layout-generation":[7],"engine":[8],"for":[9,87,96,100],"enhancing":[10],"the":[11,55,75,85,101,117,171,174,181],"design":[12,56,88,172],"productivity":[13],"of":[14],"custom":[15],"circuit":[16],"layouts":[17,125],"in":[18,34,130,139],"advanced":[19,107],"CMOS":[20,38,133,143],"processes,":[21],"is":[22,137],"presented":[23],"and":[24,58,78,94,104,109,119,146,161],"verified":[25],"by":[26,45],"implementing":[27],"time-interleaved":[29],"SAR":[30],"(TI-SAR)":[31],"ADC":[32,124],"instance":[33,136],"16":[36,141],"nm":[37,132,142],"FinFET":[39,144],"technology.":[40],"LAYGO":[41,129],"supports":[42],"rapid":[43],"generation":[44],"placing":[46],"customized":[47],"templates":[48,62],"on":[49,67,84],"process-specific":[50,59],"placement":[51,103],"grids,":[52],"thereby":[53],"encapsulating":[54],"rules":[57],"structures.":[60],"The":[61,98],"can":[63],"be":[64],"located":[65],"based":[66],"their":[68],"relative":[69],"positional":[70],"information,":[71],"which":[72],"further":[73],"enhances":[74],"description":[76,118],"capability":[77],"portability.":[79],"Interconnecting":[80],"wires":[81],"are":[82,126],"routed":[83],"grids":[86],"rule":[89],"abstractions,":[90],"additional":[92],"customizations":[93],"support":[95],"multi-patterning.":[97],"functions":[99],"on-grid":[102],"routing":[105],"use":[106],"indexing":[108],"slicing":[110],"multi-dimensional":[112],"object":[113],"containers":[114],"to":[115,166],"improve":[116],"parameterization":[120],"capabilities.":[121],"Multiple":[122],"TI-SAR":[123],"generated":[127,182],"using":[128],"28-16":[131],"technologies.":[134],"One":[135],"fabricated":[138],"process":[145],"measured,":[147],"achieving":[148],"38.2":[150],"dB":[151],"signal-to-noise-and-distortion":[152],"ratio":[153],"(SNDR)":[154],"at":[155],"7":[156],"GS/s":[157],"after":[158],"digital":[159],"calibration":[160],"consuming":[162],"45.2":[163],"mW.":[164],"Owing":[165],"its":[167],"high":[168],"customization":[169],"capability,":[170],"achieved":[173],"highest":[175],"sampling":[176],"rate":[177],"(7":[178],"GS/s)":[179],"among":[180],"ADCs.":[183]},"counts_by_year":[{"year":2026,"cited_by_count":1},{"year":2025,"cited_by_count":3},{"year":2024,"cited_by_count":4},{"year":2023,"cited_by_count":11},{"year":2022,"cited_by_count":8},{"year":2021,"cited_by_count":3}],"updated_date":"2026-06-19T17:40:00.097472","created_date":"2025-10-10T00:00:00"}