{"id":"https://openalex.org/W3094715568","doi":"https://doi.org/10.1109/tcsi.2020.3032431","title":"All Digital Phase-Locked Loop Networks for Clock Generation and Distribution: Network Stability, Convergence and Performance","display_name":"All Digital Phase-Locked Loop Networks for Clock Generation and Distribution: Network Stability, Convergence and Performance","publication_year":2020,"publication_date":"2020-10-28","ids":{"openalex":"https://openalex.org/W3094715568","doi":"https://doi.org/10.1109/tcsi.2020.3032431","mag":"3094715568"},"language":"en","primary_location":{"id":"doi:10.1109/tcsi.2020.3032431","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tcsi.2020.3032431","pdf_url":null,"source":{"id":"https://openalex.org/S116977442","display_name":"IEEE Transactions on Circuits and Systems I Regular Papers","issn_l":"1549-8328","issn":["1549-8328","1558-0806"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Circuits and Systems I: Regular Papers","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5031376924","display_name":"Eugene Koskin","orcid":"https://orcid.org/0000-0002-4253-0312"},"institutions":[{"id":"https://openalex.org/I100930933","display_name":"University College Dublin","ror":"https://ror.org/05m7pjf47","country_code":"IE","type":"education","lineage":["https://openalex.org/I100930933"]}],"countries":["IE"],"is_corresponding":false,"raw_author_name":"Eugene Koskin","raw_affiliation_strings":["School of Electrical and Electronic Engineering, University College Dublin, Dublin 4, Ireland"],"raw_orcid":"https://orcid.org/0000-0002-4253-0312","affiliations":[{"raw_affiliation_string":"School of Electrical and Electronic Engineering, University College Dublin, Dublin 4, Ireland","institution_ids":["https://openalex.org/I100930933"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5074395223","display_name":"Pierre Bisiaux","orcid":"https://orcid.org/0000-0001-7111-4337"},"institutions":[{"id":"https://openalex.org/I100930933","display_name":"University College Dublin","ror":"https://ror.org/05m7pjf47","country_code":"IE","type":"education","lineage":["https://openalex.org/I100930933"]}],"countries":["IE"],"is_corresponding":false,"raw_author_name":"Pierre Bisiaux","raw_affiliation_strings":["School of Electrical and Electronic Engineering, University College Dublin, Dublin 4, Ireland"],"raw_orcid":"https://orcid.org/0000-0001-7111-4337","affiliations":[{"raw_affiliation_string":"School of Electrical and Electronic Engineering, University College Dublin, Dublin 4, Ireland","institution_ids":["https://openalex.org/I100930933"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5032777255","display_name":"Dimitri Galayko","orcid":"https://orcid.org/0000-0002-7056-7489"},"institutions":[{"id":"https://openalex.org/I39804081","display_name":"Sorbonne Universit\u00e9","ror":"https://ror.org/02en5vm52","country_code":"FR","type":"education","lineage":["https://openalex.org/I39804081"]},{"id":"https://openalex.org/I4210159731","display_name":"LIP6","ror":"https://ror.org/05krcen59","country_code":"FR","type":"facility","lineage":["https://openalex.org/I1294671590","https://openalex.org/I1294671590","https://openalex.org/I39804081","https://openalex.org/I4210159245","https://openalex.org/I4210159731"]}],"countries":["FR"],"is_corresponding":false,"raw_author_name":"Dimitri Galayko","raw_affiliation_strings":["LIP6, Sorbonne University, Paris, France"],"raw_orcid":"https://orcid.org/0000-0002-7056-7489","affiliations":[{"raw_affiliation_string":"LIP6, Sorbonne University, Paris, France","institution_ids":["https://openalex.org/I4210159731","https://openalex.org/I39804081"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5001003834","display_name":"Elena Blokhina","orcid":"https://orcid.org/0000-0002-4164-4350"},"institutions":[{"id":"https://openalex.org/I100930933","display_name":"University College Dublin","ror":"https://ror.org/05m7pjf47","country_code":"IE","type":"education","lineage":["https://openalex.org/I100930933"]}],"countries":["IE"],"is_corresponding":false,"raw_author_name":"Elena Blokhina","raw_affiliation_strings":["School of Electrical and Electronic Engineering, University College Dublin, Dublin 4, Ireland"],"raw_orcid":"https://orcid.org/0000-0002-4164-4350","affiliations":[{"raw_affiliation_string":"School of Electrical and Electronic Engineering, University College Dublin, Dublin 4, Ireland","institution_ids":["https://openalex.org/I100930933"]}]}],"institutions":[],"countries_distinct_count":2,"institutions_distinct_count":4,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":0.4862,"has_fulltext":false,"cited_by_count":6,"citation_normalized_percentile":{"value":0.69032237,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":90,"max":96},"biblio":{"volume":"68","issue":"1","first_page":"406","last_page":"415"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11187","display_name":"Nonlinear Dynamics and Pattern Formation","score":0.9987000226974487,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11187","display_name":"Nonlinear Dynamics and Pattern Formation","score":0.9987000226974487,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11417","display_name":"Advancements in PLL and VCO Technologies","score":0.9958000183105469,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T12216","display_name":"Network Time Synchronization Technologies","score":0.9948999881744385,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/asynchronous-communication","display_name":"Asynchronous communication","score":0.6348926424980164},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6261739730834961},{"id":"https://openalex.org/keywords/synchronization","display_name":"Synchronization (alternating current)","score":0.6254912614822388},{"id":"https://openalex.org/keywords/clock-synchronization","display_name":"Clock synchronization","score":0.5516499280929565},{"id":"https://openalex.org/keywords/phase-locked-loop","display_name":"Phase-locked loop","score":0.5055911540985107},{"id":"https://openalex.org/keywords/stability","display_name":"Stability (learning theory)","score":0.49280574917793274},{"id":"https://openalex.org/keywords/synchronization-networks","display_name":"Synchronization networks","score":0.47318315505981445},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.4475381076335907},{"id":"https://openalex.org/keywords/clock-domain-crossing","display_name":"Clock domain crossing","score":0.44628119468688965},{"id":"https://openalex.org/keywords/domain","display_name":"Domain (mathematical analysis)","score":0.4286262094974518},{"id":"https://openalex.org/keywords/topology","display_name":"Topology (electrical circuits)","score":0.3639301061630249},{"id":"https://openalex.org/keywords/clock-signal","display_name":"Clock signal","score":0.34972208738327026},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.17222580313682556},{"id":"https://openalex.org/keywords/synchronous-circuit","display_name":"Synchronous circuit","score":0.15120959281921387},{"id":"https://openalex.org/keywords/telecommunications","display_name":"Telecommunications","score":0.1307297646999359},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.09999024868011475},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.09060618281364441}],"concepts":[{"id":"https://openalex.org/C151319957","wikidata":"https://www.wikidata.org/wiki/Q752739","display_name":"Asynchronous communication","level":2,"score":0.6348926424980164},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6261739730834961},{"id":"https://openalex.org/C2778562939","wikidata":"https://www.wikidata.org/wiki/Q1298791","display_name":"Synchronization (alternating current)","level":3,"score":0.6254912614822388},{"id":"https://openalex.org/C129891060","wikidata":"https://www.wikidata.org/wiki/Q1513059","display_name":"Clock synchronization","level":4,"score":0.5516499280929565},{"id":"https://openalex.org/C12707504","wikidata":"https://www.wikidata.org/wiki/Q52637","display_name":"Phase-locked loop","level":3,"score":0.5055911540985107},{"id":"https://openalex.org/C112972136","wikidata":"https://www.wikidata.org/wiki/Q7595718","display_name":"Stability (learning theory)","level":2,"score":0.49280574917793274},{"id":"https://openalex.org/C111097370","wikidata":"https://www.wikidata.org/wiki/Q10969923","display_name":"Synchronization networks","level":4,"score":0.47318315505981445},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.4475381076335907},{"id":"https://openalex.org/C127204226","wikidata":"https://www.wikidata.org/wiki/Q5134799","display_name":"Clock domain crossing","level":5,"score":0.44628119468688965},{"id":"https://openalex.org/C36503486","wikidata":"https://www.wikidata.org/wiki/Q11235244","display_name":"Domain (mathematical analysis)","level":2,"score":0.4286262094974518},{"id":"https://openalex.org/C184720557","wikidata":"https://www.wikidata.org/wiki/Q7825049","display_name":"Topology (electrical circuits)","level":2,"score":0.3639301061630249},{"id":"https://openalex.org/C137059387","wikidata":"https://www.wikidata.org/wiki/Q426882","display_name":"Clock signal","level":3,"score":0.34972208738327026},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.17222580313682556},{"id":"https://openalex.org/C42196554","wikidata":"https://www.wikidata.org/wiki/Q1186179","display_name":"Synchronous circuit","level":4,"score":0.15120959281921387},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.1307297646999359},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.09999024868011475},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.09060618281364441},{"id":"https://openalex.org/C134306372","wikidata":"https://www.wikidata.org/wiki/Q7754","display_name":"Mathematical analysis","level":1,"score":0.0},{"id":"https://openalex.org/C127162648","wikidata":"https://www.wikidata.org/wiki/Q16858953","display_name":"Channel (broadcasting)","level":2,"score":0.0},{"id":"https://openalex.org/C119857082","wikidata":"https://www.wikidata.org/wiki/Q2539","display_name":"Machine learning","level":1,"score":0.0},{"id":"https://openalex.org/C134652429","wikidata":"https://www.wikidata.org/wiki/Q1052698","display_name":"Jitter","level":2,"score":0.0}],"mesh":[],"locations_count":2,"locations":[{"id":"doi:10.1109/tcsi.2020.3032431","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tcsi.2020.3032431","pdf_url":null,"source":{"id":"https://openalex.org/S116977442","display_name":"IEEE Transactions on Circuits and Systems I Regular Papers","issn_l":"1549-8328","issn":["1549-8328","1558-0806"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Circuits and Systems I: Regular Papers","raw_type":"journal-article"},{"id":"pmh:oai:HAL:hal-04030230v1","is_oa":false,"landing_page_url":"https://hal.science/hal-04030230","pdf_url":null,"source":{"id":"https://openalex.org/S4306402512","display_name":"HAL (Le Centre pour la Communication Scientifique Directe)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I1294671590","host_organization_name":"Centre National de la Recherche Scientifique","host_organization_lineage":["https://openalex.org/I1294671590"],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"IEEE Transactions on Circuits and Systems I: Regular Papers, 2021, 68 (1), pp.406-415. &#x27E8;10.1109/TCSI.2020.3032431&#x27E9;","raw_type":"Journal articles"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[{"id":"https://openalex.org/G296308891","display_name":null,"funder_award_id":"CF-2018-0872-P","funder_id":"https://openalex.org/F4320320834","funder_display_name":"Enterprise Ireland"}],"funders":[{"id":"https://openalex.org/F4320320834","display_name":"Enterprise Ireland","ror":"https://ror.org/023z51242"}],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":72,"referenced_works":["https://openalex.org/W1530349891","https://openalex.org/W1532564654","https://openalex.org/W1544882865","https://openalex.org/W1583806922","https://openalex.org/W2001188743","https://openalex.org/W2009233867","https://openalex.org/W2010779896","https://openalex.org/W2017720909","https://openalex.org/W2033770904","https://openalex.org/W2051049739","https://openalex.org/W2057845030","https://openalex.org/W2069142841","https://openalex.org/W2083782512","https://openalex.org/W2089328455","https://openalex.org/W2097242029","https://openalex.org/W2100205120","https://openalex.org/W2104502229","https://openalex.org/W2111991111","https://openalex.org/W2117300324","https://openalex.org/W2118232269","https://openalex.org/W2127115683","https://openalex.org/W2129134935","https://openalex.org/W2129429105","https://openalex.org/W2137807823","https://openalex.org/W2142250731","https://openalex.org/W2146925387","https://openalex.org/W2154332266","https://openalex.org/W2154395793","https://openalex.org/W2159584850","https://openalex.org/W2163117858","https://openalex.org/W2168400970","https://openalex.org/W2168549392","https://openalex.org/W2291159204","https://openalex.org/W2292034224","https://openalex.org/W2298036307","https://openalex.org/W2337949091","https://openalex.org/W2490165320","https://openalex.org/W2536327210","https://openalex.org/W2547192377","https://openalex.org/W2584998015","https://openalex.org/W2601082425","https://openalex.org/W2615504945","https://openalex.org/W2753327552","https://openalex.org/W2754368137","https://openalex.org/W2758150969","https://openalex.org/W2791192103","https://openalex.org/W2793340579","https://openalex.org/W2794241492","https://openalex.org/W2802574371","https://openalex.org/W2887823254","https://openalex.org/W2895796083","https://openalex.org/W2911266525","https://openalex.org/W2913547449","https://openalex.org/W2914703523","https://openalex.org/W2941102108","https://openalex.org/W2946252709","https://openalex.org/W2962855623","https://openalex.org/W2963673880","https://openalex.org/W2963830578","https://openalex.org/W2965666675","https://openalex.org/W2982402701","https://openalex.org/W2994806350","https://openalex.org/W2996914186","https://openalex.org/W3042176402","https://openalex.org/W3083804490","https://openalex.org/W3102275355","https://openalex.org/W3104543387","https://openalex.org/W3147966010","https://openalex.org/W4233569121","https://openalex.org/W6728941046","https://openalex.org/W6754311400","https://openalex.org/W6785941900"],"related_works":["https://openalex.org/W3013924136","https://openalex.org/W1917576147","https://openalex.org/W1924044602","https://openalex.org/W2083095101","https://openalex.org/W2006392656","https://openalex.org/W2386718233","https://openalex.org/W4380625041","https://openalex.org/W2292909929","https://openalex.org/W2147289961","https://openalex.org/W2376911584"],"abstract_inverted_index":{"In":[0],"this":[1],"paper,":[2],"we":[3],"study":[4],"networks":[5,98],"of":[6,14,39,44,96],"coupled":[7],"oscillators":[8,21],"applied":[9],"to":[10,67,84],"the":[11,37,55,68,78,81,85,131,140],"distributed":[12,124],"synthesis":[13],"clock":[15,122],"signals":[16],"for":[17,60,70,115,139],"large":[18,61],"systems-on-chip.":[19],"The":[20,109],"are":[22,31],"implemented":[23],"as":[24],"interconnected":[25,50],"all-digital":[26],"phase-locked":[27],"loops":[28],"(ADPLLs),":[29],"which":[30],"asynchronous":[32],"control":[33,132],"systems.":[34],"We":[35,52,74],"address":[36],"issue":[38],"modelling,":[40],"synchronization":[41],"and":[42,49,64,91,101,118,127],"stability":[43,56,79],"both":[45,88],"a":[46,71],"single":[47,72],"ADPLL":[48],"ADPLLs.":[51],"prove":[53],"that":[54,76],"domain":[57,69,80],"is":[58,99,103,136],"universal":[59],"Cartesian":[62,97],"networks,":[63],"it":[65,102],"related":[66],"ADPLL.":[73],"show":[75],"within":[77],"network":[82],"synchronises":[83],"reference":[86],"signal":[87],"in":[89],"frequency":[90],"phase.":[92],"A":[93],"hardware":[94],"verification":[95],"presented,":[100],"consistent":[104],"with":[105],"our":[106],"theoretical":[107],"findings.":[108],"proposed":[110],"design":[111],"may":[112],"be":[113],"useful":[114],"multiples":[116],"engineering":[117],"physics":[119],"applications,":[120,129],"including":[121],"generation,":[123],"computations,":[125],"beamforming,":[126],"other":[128],"where":[130],"over":[133],"time":[134],"synchronicity":[135],"crucially":[137],"important":[138],"system":[141],"performance.":[142]},"counts_by_year":[{"year":2025,"cited_by_count":1},{"year":2024,"cited_by_count":2},{"year":2023,"cited_by_count":2},{"year":2022,"cited_by_count":1}],"updated_date":"2026-06-11T09:08:48.828518","created_date":"2025-10-10T00:00:00"}
