{"id":"https://openalex.org/W3036901913","doi":"https://doi.org/10.1109/tcsi.2020.3000468","title":"A Crossbar-Based In-Memory Computing Architecture","display_name":"A Crossbar-Based In-Memory Computing Architecture","publication_year":2020,"publication_date":"2020-06-18","ids":{"openalex":"https://openalex.org/W3036901913","doi":"https://doi.org/10.1109/tcsi.2020.3000468","mag":"3036901913"},"language":"en","primary_location":{"id":"doi:10.1109/tcsi.2020.3000468","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tcsi.2020.3000468","pdf_url":null,"source":{"id":"https://openalex.org/S116977442","display_name":"IEEE Transactions on Circuits and Systems I Regular Papers","issn_l":"1549-8328","issn":["1549-8328","1558-0806"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Circuits and Systems I: Regular Papers","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5108050055","display_name":"Xinxin Wang","orcid":"https://orcid.org/0000-0003-0136-5936"},"institutions":[{"id":"https://openalex.org/I27837315","display_name":"University of Michigan","ror":"https://ror.org/00jmfr291","country_code":"US","type":"education","lineage":["https://openalex.org/I27837315"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Xinxin Wang","raw_affiliation_strings":["University of Michigan, Ann Arbor, MI, USA"],"raw_orcid":"https://orcid.org/0000-0003-0136-5936","affiliations":[{"raw_affiliation_string":"University of Michigan, Ann Arbor, MI, USA","institution_ids":["https://openalex.org/I27837315"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5046637848","display_name":"Mohammed A. Zidan","orcid":"https://orcid.org/0000-0003-3843-814X"},"institutions":[{"id":"https://openalex.org/I27837315","display_name":"University of Michigan","ror":"https://ror.org/00jmfr291","country_code":"US","type":"education","lineage":["https://openalex.org/I27837315"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Mohammed A. Zidan","raw_affiliation_strings":["University of Michigan, Ann Arbor, MI, USA"],"raw_orcid":"https://orcid.org/0000-0003-3843-814X","affiliations":[{"raw_affiliation_string":"University of Michigan, Ann Arbor, MI, USA","institution_ids":["https://openalex.org/I27837315"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5066881061","display_name":"Wei L\u00fc","orcid":"https://orcid.org/0000-0003-4731-1976"},"institutions":[{"id":"https://openalex.org/I27837315","display_name":"University of Michigan","ror":"https://ror.org/00jmfr291","country_code":"US","type":"education","lineage":["https://openalex.org/I27837315"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Wei D. Lu","raw_affiliation_strings":["University of Michigan, Ann Arbor, MI, USA"],"raw_orcid":"https://orcid.org/0000-0003-4731-1976","affiliations":[{"raw_affiliation_string":"University of Michigan, Ann Arbor, MI, USA","institution_ids":["https://openalex.org/I27837315"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":3,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":1.8732,"has_fulltext":false,"cited_by_count":29,"citation_normalized_percentile":{"value":0.85832534,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":95,"max":99},"biblio":{"volume":"67","issue":"12","first_page":"4224","last_page":"4232"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10502","display_name":"Advanced Memory and Neural Computing","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10502","display_name":"Advanced Memory and Neural Computing","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T12808","display_name":"Ferroelectric and Negative Capacitance Devices","score":0.9994999766349792,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10472","display_name":"Semiconductor materials and devices","score":0.9947999715805054,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/crossbar-switch","display_name":"Crossbar switch","score":0.8753105401992798},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.8005703687667847},{"id":"https://openalex.org/keywords/resistive-random-access-memory","display_name":"Resistive random-access memory","score":0.7393897175788879},{"id":"https://openalex.org/keywords/von-neumann-architecture","display_name":"Von Neumann architecture","score":0.662484347820282},{"id":"https://openalex.org/keywords/in-memory-processing","display_name":"In-Memory Processing","score":0.6508557200431824},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.595566987991333},{"id":"https://openalex.org/keywords/bottleneck","display_name":"Bottleneck","score":0.5724202990531921},{"id":"https://openalex.org/keywords/memory-architecture","display_name":"Memory architecture","score":0.5315627455711365},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.4781457185745239},{"id":"https://openalex.org/keywords/block","display_name":"Block (permutation group theory)","score":0.45110124349594116},{"id":"https://openalex.org/keywords/computing-with-memory","display_name":"Computing with Memory","score":0.41705745458602905},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.4099675714969635},{"id":"https://openalex.org/keywords/semiconductor-memory","display_name":"Semiconductor memory","score":0.4090900719165802},{"id":"https://openalex.org/keywords/memory-management","display_name":"Memory management","score":0.406257301568985},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.33200472593307495},{"id":"https://openalex.org/keywords/uniform-memory-access","display_name":"Uniform memory access","score":0.301677405834198},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.13882660865783691},{"id":"https://openalex.org/keywords/search-engine","display_name":"Search engine","score":0.11756902933120728},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.10071620345115662},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.08178383111953735},{"id":"https://openalex.org/keywords/voltage","display_name":"Voltage","score":0.07561424374580383}],"concepts":[{"id":"https://openalex.org/C29984679","wikidata":"https://www.wikidata.org/wiki/Q1929149","display_name":"Crossbar switch","level":2,"score":0.8753105401992798},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.8005703687667847},{"id":"https://openalex.org/C182019814","wikidata":"https://www.wikidata.org/wiki/Q1143830","display_name":"Resistive random-access memory","level":3,"score":0.7393897175788879},{"id":"https://openalex.org/C80469333","wikidata":"https://www.wikidata.org/wiki/Q189088","display_name":"Von Neumann architecture","level":2,"score":0.662484347820282},{"id":"https://openalex.org/C123593499","wikidata":"https://www.wikidata.org/wiki/Q6008583","display_name":"In-Memory Processing","level":5,"score":0.6508557200431824},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.595566987991333},{"id":"https://openalex.org/C2780513914","wikidata":"https://www.wikidata.org/wiki/Q18210350","display_name":"Bottleneck","level":2,"score":0.5724202990531921},{"id":"https://openalex.org/C2779602883","wikidata":"https://www.wikidata.org/wiki/Q15544750","display_name":"Memory architecture","level":2,"score":0.5315627455711365},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.4781457185745239},{"id":"https://openalex.org/C2777210771","wikidata":"https://www.wikidata.org/wiki/Q4927124","display_name":"Block (permutation group theory)","level":2,"score":0.45110124349594116},{"id":"https://openalex.org/C152890283","wikidata":"https://www.wikidata.org/wiki/Q4129922","display_name":"Computing with Memory","level":5,"score":0.41705745458602905},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.4099675714969635},{"id":"https://openalex.org/C98986596","wikidata":"https://www.wikidata.org/wiki/Q1143031","display_name":"Semiconductor memory","level":2,"score":0.4090900719165802},{"id":"https://openalex.org/C176649486","wikidata":"https://www.wikidata.org/wiki/Q2308807","display_name":"Memory management","level":3,"score":0.406257301568985},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.33200472593307495},{"id":"https://openalex.org/C51290061","wikidata":"https://www.wikidata.org/wiki/Q1936765","display_name":"Uniform memory access","level":4,"score":0.301677405834198},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.13882660865783691},{"id":"https://openalex.org/C97854310","wikidata":"https://www.wikidata.org/wiki/Q19541","display_name":"Search engine","level":2,"score":0.11756902933120728},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.10071620345115662},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.08178383111953735},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.07561424374580383},{"id":"https://openalex.org/C164120249","wikidata":"https://www.wikidata.org/wiki/Q995982","display_name":"Web search query","level":3,"score":0.0},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.0},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.0},{"id":"https://openalex.org/C23123220","wikidata":"https://www.wikidata.org/wiki/Q816826","display_name":"Information retrieval","level":1,"score":0.0},{"id":"https://openalex.org/C2524010","wikidata":"https://www.wikidata.org/wiki/Q8087","display_name":"Geometry","level":1,"score":0.0},{"id":"https://openalex.org/C194222762","wikidata":"https://www.wikidata.org/wiki/Q114486","display_name":"Query by Example","level":4,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/tcsi.2020.3000468","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tcsi.2020.3000468","pdf_url":null,"source":{"id":"https://openalex.org/S116977442","display_name":"IEEE Transactions on Circuits and Systems I Regular Papers","issn_l":"1549-8328","issn":["1549-8328","1558-0806"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Circuits and Systems I: Regular Papers","raw_type":"journal-article"}],"best_oa_location":null,"sustainable_development_goals":[{"display_name":"Affordable and clean energy","id":"https://metadata.un.org/sdg/7","score":0.8799999952316284}],"awards":[{"id":"https://openalex.org/G2360633885","display_name":null,"funder_award_id":"CCF-1900675","funder_id":"https://openalex.org/F4320306076","funder_display_name":"National Science Foundation"},{"id":"https://openalex.org/G7794282163","display_name":null,"funder_award_id":"CCF-1617315","funder_id":"https://openalex.org/F4320306076","funder_display_name":"National Science Foundation"}],"funders":[{"id":"https://openalex.org/F4320306076","display_name":"National Science Foundation","ror":"https://ror.org/021nxhr62"}],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":39,"referenced_works":["https://openalex.org/W1184503651","https://openalex.org/W1518772125","https://openalex.org/W1526568018","https://openalex.org/W1582848023","https://openalex.org/W1925766216","https://openalex.org/W1940420793","https://openalex.org/W1983604042","https://openalex.org/W2004823737","https://openalex.org/W2018774711","https://openalex.org/W2021853834","https://openalex.org/W2035474862","https://openalex.org/W2052218585","https://openalex.org/W2080391538","https://openalex.org/W2081729575","https://openalex.org/W2086112773","https://openalex.org/W2090413838","https://openalex.org/W2108340689","https://openalex.org/W2148331362","https://openalex.org/W2216132385","https://openalex.org/W2248506981","https://openalex.org/W2250636351","https://openalex.org/W2292548336","https://openalex.org/W2345622364","https://openalex.org/W2407339173","https://openalex.org/W2431884816","https://openalex.org/W2522667948","https://openalex.org/W2565353159","https://openalex.org/W2604191638","https://openalex.org/W2612936968","https://openalex.org/W2731422849","https://openalex.org/W2736959895","https://openalex.org/W2752015454","https://openalex.org/W2753526263","https://openalex.org/W2778935320","https://openalex.org/W2795584069","https://openalex.org/W2905594454","https://openalex.org/W6663974305","https://openalex.org/W6672930468","https://openalex.org/W6704402733"],"related_works":["https://openalex.org/W3090482767","https://openalex.org/W3180803030","https://openalex.org/W4225739994","https://openalex.org/W4321062910","https://openalex.org/W1970751325","https://openalex.org/W2942841750","https://openalex.org/W3163143851","https://openalex.org/W2143690511","https://openalex.org/W2993507867","https://openalex.org/W3025845664"],"abstract_inverted_index":{"To":[0],"address":[1],"the":[2,76,105,133,149],"von":[3],"Neumann":[4],"bottleneck":[5],"that":[6,45,132],"leads":[7],"to":[8,89,154],"both":[9],"energy":[10],"and":[11,48,53,68,84,99,109],"speed":[12],"degradations,":[13],"in-memory":[14,34,135],"processing":[15],"architectures":[16],"have":[17],"been":[18],"proposed":[19,134],"as":[20],"a":[21,65],"promising":[22],"alternative":[23],"for":[24,140],"future":[25],"computing":[26,35,55,136],"applications.":[27],"In":[28],"this":[29,123],"paper,":[30],"we":[31],"present":[32],"an":[33],"system":[36,58],"based":[37],"on":[38,104,122],"resistive":[39],"random-access":[40],"memory":[41,66],"(RRAM)":[42],"crossbar":[43,79,150],"arrays":[44],"is":[46,120,138,152],"reconfigurable":[47],"can":[49],"potentially":[50],"perform":[51],"parallel":[52],"general":[54],"tasks.":[56],"The":[57,144],"consists":[59],"of":[60,95,107,117,148],"small":[61],"look-up":[62],"tables":[63],"(LUTs),":[64],"block,":[67],"two":[69],"search":[70,108],"auxiliary":[71],"blocks,":[72],"all":[73],"implemented":[74],"in":[75],"same":[77],"RRAM":[78],"array.":[80],"External":[81],"data":[82,85],"access":[83],"conversions":[86],"are":[87,102],"eliminated":[88],"allow":[90],"operations":[91,101],"fully":[92],"in-memory.":[93],"Details":[94],"addition,":[96],"AND":[97],"logic":[98],"multiplication":[100],"discussed":[103],"basis":[106],"writeback":[110],"steps.":[111],"A":[112],"compact":[113],"instruction":[114],"set":[115],"consisting":[116],"10":[118],"instructions":[119],"demonstrated":[121],"architecture":[124,137],"through":[125],"circuit":[126],"level":[127],"simulations.":[128],"Performance":[129],"evaluations":[130],"show":[131],"suitable":[139],"handling":[141],"data-intensive":[142],"problems.":[143],"average":[145],"power":[146],"consumption":[147],"chip":[151],"estimated":[153],"be":[155],"45\u03bcW.":[156]},"counts_by_year":[{"year":2026,"cited_by_count":1},{"year":2025,"cited_by_count":6},{"year":2024,"cited_by_count":4},{"year":2023,"cited_by_count":5},{"year":2022,"cited_by_count":6},{"year":2021,"cited_by_count":4},{"year":2020,"cited_by_count":3}],"updated_date":"2026-06-11T09:08:48.828518","created_date":"2025-10-10T00:00:00"}