{"id":"https://openalex.org/W2980922935","doi":"https://doi.org/10.1109/tcsi.2019.2945086","title":"Low-Power All-Digital Multiphase DLL Design Using a Scalable Phase-to-Digital Converter","display_name":"Low-Power All-Digital Multiphase DLL Design Using a Scalable Phase-to-Digital Converter","publication_year":2019,"publication_date":"2019-10-15","ids":{"openalex":"https://openalex.org/W2980922935","doi":"https://doi.org/10.1109/tcsi.2019.2945086","mag":"2980922935"},"language":"en","primary_location":{"id":"doi:10.1109/tcsi.2019.2945086","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tcsi.2019.2945086","pdf_url":null,"source":{"id":"https://openalex.org/S116977442","display_name":"IEEE Transactions on Circuits and Systems I Regular Papers","issn_l":"1549-8328","issn":["1549-8328","1558-0806"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Circuits and Systems I: Regular Papers","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5027557514","display_name":"Nico Angeli","orcid":"https://orcid.org/0000-0002-7731-9859"},"institutions":[{"id":"https://openalex.org/I31512782","display_name":"Technical University of Darmstadt","ror":"https://ror.org/05n911h24","country_code":"DE","type":"education","lineage":["https://openalex.org/I31512782"]}],"countries":["DE"],"is_corresponding":true,"raw_author_name":"Nico Angeli","raw_affiliation_strings":["Chair of Integrated Electronic Systems, TU Darmstadt, Darmstadt, Germany"],"affiliations":[{"raw_affiliation_string":"Chair of Integrated Electronic Systems, TU Darmstadt, Darmstadt, Germany","institution_ids":["https://openalex.org/I31512782"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5061804977","display_name":"Klaus Hofmann","orcid":"https://orcid.org/0000-0002-6675-0221"},"institutions":[{"id":"https://openalex.org/I31512782","display_name":"Technical University of Darmstadt","ror":"https://ror.org/05n911h24","country_code":"DE","type":"education","lineage":["https://openalex.org/I31512782"]}],"countries":["DE"],"is_corresponding":false,"raw_author_name":"Klaus Hofmann","raw_affiliation_strings":["Chair of Integrated Electronic Systems, TU Darmstadt, Darmstadt, Germany"],"affiliations":[{"raw_affiliation_string":"Chair of Integrated Electronic Systems, TU Darmstadt, Darmstadt, Germany","institution_ids":["https://openalex.org/I31512782"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":2,"corresponding_author_ids":["https://openalex.org/A5027557514"],"corresponding_institution_ids":["https://openalex.org/I31512782"],"apc_list":null,"apc_paid":null,"fwci":1.1923,"has_fulltext":false,"cited_by_count":18,"citation_normalized_percentile":{"value":0.79863441,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":98},"biblio":{"volume":"67","issue":"4","first_page":"1158","last_page":"1168"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11417","display_name":"Advancements in PLL and VCO Technologies","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11417","display_name":"Advancements in PLL and VCO Technologies","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10323","display_name":"Analog and Mixed-Signal Circuit Design","score":0.9986000061035156,"subfield":{"id":"https://openalex.org/subfields/2204","display_name":"Biomedical Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10299","display_name":"Photonic and Optical Devices","score":0.9973999857902527,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/jitter","display_name":"Jitter","score":0.788253903388977},{"id":"https://openalex.org/keywords/clock-generator","display_name":"Clock generator","score":0.7147544026374817},{"id":"https://openalex.org/keywords/cmos","display_name":"CMOS","score":0.571845293045044},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.5689213275909424},{"id":"https://openalex.org/keywords/inverter","display_name":"Inverter","score":0.5591650009155273},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.5499427318572998},{"id":"https://openalex.org/keywords/phase-locked-loop","display_name":"Phase-locked loop","score":0.466691792011261},{"id":"https://openalex.org/keywords/delay-locked-loop","display_name":"Delay-locked loop","score":0.4546409845352173},{"id":"https://openalex.org/keywords/scalability","display_name":"Scalability","score":0.4372161030769348},{"id":"https://openalex.org/keywords/voltage","display_name":"Voltage","score":0.28839194774627686},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.250989705324173},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.1855776309967041},{"id":"https://openalex.org/keywords/clock-signal","display_name":"Clock signal","score":0.11474195122718811}],"concepts":[{"id":"https://openalex.org/C134652429","wikidata":"https://www.wikidata.org/wiki/Q1052698","display_name":"Jitter","level":2,"score":0.788253903388977},{"id":"https://openalex.org/C2778023540","wikidata":"https://www.wikidata.org/wiki/Q2164847","display_name":"Clock generator","level":4,"score":0.7147544026374817},{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.571845293045044},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.5689213275909424},{"id":"https://openalex.org/C11190779","wikidata":"https://www.wikidata.org/wiki/Q664575","display_name":"Inverter","level":3,"score":0.5591650009155273},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.5499427318572998},{"id":"https://openalex.org/C12707504","wikidata":"https://www.wikidata.org/wiki/Q52637","display_name":"Phase-locked loop","level":3,"score":0.466691792011261},{"id":"https://openalex.org/C190462668","wikidata":"https://www.wikidata.org/wiki/Q492265","display_name":"Delay-locked loop","level":4,"score":0.4546409845352173},{"id":"https://openalex.org/C48044578","wikidata":"https://www.wikidata.org/wiki/Q727490","display_name":"Scalability","level":2,"score":0.4372161030769348},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.28839194774627686},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.250989705324173},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.1855776309967041},{"id":"https://openalex.org/C137059387","wikidata":"https://www.wikidata.org/wiki/Q426882","display_name":"Clock signal","level":3,"score":0.11474195122718811},{"id":"https://openalex.org/C77088390","wikidata":"https://www.wikidata.org/wiki/Q8513","display_name":"Database","level":1,"score":0.0}],"mesh":[],"locations_count":2,"locations":[{"id":"doi:10.1109/tcsi.2019.2945086","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tcsi.2019.2945086","pdf_url":null,"source":{"id":"https://openalex.org/S116977442","display_name":"IEEE Transactions on Circuits and Systems I Regular Papers","issn_l":"1549-8328","issn":["1549-8328","1558-0806"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Circuits and Systems I: Regular Papers","raw_type":"journal-article"},{"id":"pmh:oai:tubiblio.ulb.tu-darmstadt.de:122504","is_oa":false,"landing_page_url":"https://ieeexplore.ieee.org/document/8869924","pdf_url":null,"source":{"id":"https://openalex.org/S4377196390","display_name":"TUbilio (Technical University of Darmstadt)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I31512782","host_organization_name":"Technische Universit\u00e4t Darmstadt","host_organization_lineage":["https://openalex.org/I31512782"],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"","raw_type":"Artikel"}],"best_oa_location":null,"sustainable_development_goals":[{"score":0.8899999856948853,"display_name":"Affordable and clean energy","id":"https://metadata.un.org/sdg/7"}],"awards":[{"id":"https://openalex.org/G6116852188","display_name":null,"funder_award_id":"DFG 269885131","funder_id":"https://openalex.org/F4320320879","funder_display_name":"Deutsche Forschungsgemeinschaft"}],"funders":[{"id":"https://openalex.org/F4320320879","display_name":"Deutsche Forschungsgemeinschaft","ror":"https://ror.org/018mejw64"}],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":28,"referenced_works":["https://openalex.org/W1547294555","https://openalex.org/W1806144281","https://openalex.org/W1953939323","https://openalex.org/W1989484081","https://openalex.org/W1995429929","https://openalex.org/W2012162936","https://openalex.org/W2019196754","https://openalex.org/W2052293768","https://openalex.org/W2066871406","https://openalex.org/W2093818364","https://openalex.org/W2101853659","https://openalex.org/W2108914577","https://openalex.org/W2115257542","https://openalex.org/W2143085570","https://openalex.org/W2157486149","https://openalex.org/W2164188348","https://openalex.org/W2244217849","https://openalex.org/W2600277699","https://openalex.org/W2611116148","https://openalex.org/W2611330462","https://openalex.org/W2727227226","https://openalex.org/W2802255811","https://openalex.org/W2911341463","https://openalex.org/W3125936950","https://openalex.org/W3152162041","https://openalex.org/W4285719527","https://openalex.org/W6641045975","https://openalex.org/W6676128695"],"related_works":["https://openalex.org/W1994021281","https://openalex.org/W2139484866","https://openalex.org/W2301158783","https://openalex.org/W2133120878","https://openalex.org/W2354050524","https://openalex.org/W1969806930","https://openalex.org/W2083878249","https://openalex.org/W2401743820","https://openalex.org/W3177439118","https://openalex.org/W2369998856"],"abstract_inverted_index":{"This":[0],"work":[1],"presents":[2],"a":[3,18,32,47,98,162,168,193,241,257,273],"low-power":[4],"all-digital":[5],"approach":[6],"to":[7,40,46,74,228,251,263,269],"multiphase":[8,156],"delay":[9,49,60,71,81,95],"locked":[10],"loop":[11,210],"(DLL)":[12],"design":[13,78,107],"by":[14],"the":[15,38,59,80,84,89,110,130,135,137,140,201,208,212,224,231,252,259,270],"use":[16,271],"of":[17,109,139,182,200,234,272],"scalable":[19],"phase-to-digital":[20],"converter":[21],"(PDC)":[22],"based":[23,112,119,145,155,174,226,254],"on":[24,146],"asynchronous":[25],"sampling.":[26],"The":[27,65,105,151,171,197,217],"PDC":[28],"is":[29,127,203,220,261],"used":[30],"as":[31],"linear":[33],"phase":[34,43,213],"detector":[35],"(PD)":[36],"with":[37,51,79,192,223,240],"ability":[39],"measure":[41],"any":[42],"difference":[44],"leading":[45],"shorter":[48],"line":[50,82],"less":[52,103],"power":[53,100,232,248],"consumption.":[54],"Two":[55],"different":[56],"approaches":[57],"for":[58,134,207],"cell":[61,72,96],"implementation":[62],"are":[63,159],"investigated.":[64],"digitally":[66],"controlled":[67,91],"shunt-capacitor":[68],"inverter":[69,93],"(SC!)":[70],"leads":[73],"an":[75,246,277],"extremely":[76],"small":[77],"being":[83],"only":[85,177],"analog":[86,123,278],"component,":[87],"while":[88],"voltage":[90],"current-starved":[92],"(CS!)":[94],"has":[97],"lower":[99],"consumption":[101,233],"and":[102,153,185,205,211,230,276],"jitter.":[104],"proposed":[106,131,172],"procedure":[108],"SC!":[111,152,173,253],"DLL":[113,141,157,175,209,227],"allows":[114],"fast":[115],"simulation":[116],"using":[117],"Verilog":[118],"models":[120],"since":[121],"no":[122],"low":[124,279],"pass":[125,280],"filter":[126],"required.":[128],"Using":[129],"modeling":[132],"technique":[133],"PDC,":[136],"behavior":[138],"can":[142],"be":[143],"estimated":[144],"input":[147,190,238],"clock":[148,244],"jitter":[149,199,219],"specifications.":[150],"CS!":[154,225],"designs":[158],"fabricated":[160],"in":[161],"65nm":[163],"CMOS":[164],"process":[165],"operated":[166],"from":[167],"1.2V":[169],"supply.":[170],"occupies":[176],"0.0048mm":[178],"<sup":[179,265],"xmlns:mml=\"http://www.w3.org/1998/Math/MathML\"":[180,266],"xmlns:xlink=\"http://www.w3.org/1999/xlink\">2</sup>":[181,267],"active":[183],"area":[184,260],"consumes":[186],"2.25mW":[187],"at":[188,236],"2.5GHz":[189],"frequency":[191,239],"622.6MHz":[194],"sample":[195,243],"clock.":[196],"RMS":[198,218],"circuit":[202],"1.2ps":[204],"1.4ps":[206],"shifter":[214],"loop,":[215],"respectively.":[216],"significantly":[221],"reduced":[222],"0.86ps":[229],"2.64mW":[235],"4GHz":[237],"996.1MHz":[242],"provides":[245],"improved":[247],"efficiency":[249],"compared":[250],"DLL.":[255],"As":[256],"trade-off,":[258],"increased":[262],"0.0085mm":[264],"due":[268],"\u0394\u03a3":[274],"modulator":[275],"filter.":[281]},"counts_by_year":[{"year":2025,"cited_by_count":5},{"year":2024,"cited_by_count":2},{"year":2023,"cited_by_count":1},{"year":2022,"cited_by_count":1},{"year":2021,"cited_by_count":4},{"year":2020,"cited_by_count":5}],"updated_date":"2026-02-26T08:16:20.718346","created_date":"2025-10-10T00:00:00"}