{"id":"https://openalex.org/W2968205518","doi":"https://doi.org/10.1109/tcsi.2019.2926512","title":"A 0.12-mm<sup>2</sup> 1.2-to-2.4-mW 1.3-to-2.65-GHz Fractional-N Bang-Bang Digital PLL With 8-$\\mu$ s Settling Time for Multi-ISM-Band ULP Radios","display_name":"A 0.12-mm<sup>2</sup> 1.2-to-2.4-mW 1.3-to-2.65-GHz Fractional-N Bang-Bang Digital PLL With 8-$\\mu$ s Settling Time for Multi-ISM-Band ULP Radios","publication_year":2019,"publication_date":"2019-08-16","ids":{"openalex":"https://openalex.org/W2968205518","doi":"https://doi.org/10.1109/tcsi.2019.2926512","mag":"2968205518"},"language":"en","primary_location":{"id":"doi:10.1109/tcsi.2019.2926512","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tcsi.2019.2926512","pdf_url":null,"source":{"id":"https://openalex.org/S116977442","display_name":"IEEE Transactions on Circuits and Systems I Regular Papers","issn_l":"1549-8328","issn":["1549-8328","1558-0806"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Circuits and Systems I: Regular Papers","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5038010873","display_name":"Ka-Fai Un","orcid":"https://orcid.org/0000-0002-7574-4755"},"institutions":[{"id":"https://openalex.org/I204512498","display_name":"University of Macau","ror":"https://ror.org/01r4q9n85","country_code":"MO","type":"education","lineage":["https://openalex.org/I204512498"]},{"id":"https://openalex.org/I4210119392","display_name":"Institute of Microelectronics","ror":"https://ror.org/02s6gs133","country_code":"CN","type":"facility","lineage":["https://openalex.org/I19820366","https://openalex.org/I4210119392"]}],"countries":["CN","MO"],"is_corresponding":true,"raw_author_name":"Ka-Fai Un","raw_affiliation_strings":["State Key Laboratory of Analog and Mixed-Signal VLSI, Faculty of Science and Technology, ECE, Institute of Microelectronics, University of Macau, Macao, China"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"State Key Laboratory of Analog and Mixed-Signal VLSI, Faculty of Science and Technology, ECE, Institute of Microelectronics, University of Macau, Macao, China","institution_ids":["https://openalex.org/I204512498","https://openalex.org/I4210119392"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5072593783","display_name":"Gengzhen Qi","orcid":"https://orcid.org/0000-0001-5035-8017"},"institutions":[{"id":"https://openalex.org/I204512498","display_name":"University of Macau","ror":"https://ror.org/01r4q9n85","country_code":"MO","type":"education","lineage":["https://openalex.org/I204512498"]},{"id":"https://openalex.org/I4210119392","display_name":"Institute of Microelectronics","ror":"https://ror.org/02s6gs133","country_code":"CN","type":"facility","lineage":["https://openalex.org/I19820366","https://openalex.org/I4210119392"]}],"countries":["CN","MO"],"is_corresponding":false,"raw_author_name":"Gengzhen Qi","raw_affiliation_strings":["State Key Laboratory of Analog and Mixed-Signal VLSI, Institute of Microelectronics, University of Macau, Macao, China"],"raw_orcid":"https://orcid.org/0000-0001-5035-8017","affiliations":[{"raw_affiliation_string":"State Key Laboratory of Analog and Mixed-Signal VLSI, Institute of Microelectronics, University of Macau, Macao, China","institution_ids":["https://openalex.org/I204512498","https://openalex.org/I4210119392"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5006541988","display_name":"Jun Yin","orcid":"https://orcid.org/0000-0002-4195-4551"},"institutions":[{"id":"https://openalex.org/I204512498","display_name":"University of Macau","ror":"https://ror.org/01r4q9n85","country_code":"MO","type":"education","lineage":["https://openalex.org/I204512498"]},{"id":"https://openalex.org/I4210119392","display_name":"Institute of Microelectronics","ror":"https://ror.org/02s6gs133","country_code":"CN","type":"facility","lineage":["https://openalex.org/I19820366","https://openalex.org/I4210119392"]}],"countries":["CN","MO"],"is_corresponding":false,"raw_author_name":"Jun Yin","raw_affiliation_strings":["State Key Laboratory of Analog and Mixed-Signal VLSI, Faculty of Science and Technology, ECE, Institute of Microelectronics, University of Macau, Macao, China"],"raw_orcid":"https://orcid.org/0000-0002-4195-4551","affiliations":[{"raw_affiliation_string":"State Key Laboratory of Analog and Mixed-Signal VLSI, Faculty of Science and Technology, ECE, Institute of Microelectronics, University of Macau, Macao, China","institution_ids":["https://openalex.org/I204512498","https://openalex.org/I4210119392"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5010440595","display_name":"Shiheng Yang","orcid":"https://orcid.org/0000-0002-4883-160X"},"institutions":[{"id":"https://openalex.org/I204512498","display_name":"University of Macau","ror":"https://ror.org/01r4q9n85","country_code":"MO","type":"education","lineage":["https://openalex.org/I204512498"]},{"id":"https://openalex.org/I4210119392","display_name":"Institute of Microelectronics","ror":"https://ror.org/02s6gs133","country_code":"CN","type":"facility","lineage":["https://openalex.org/I19820366","https://openalex.org/I4210119392"]}],"countries":["CN","MO"],"is_corresponding":false,"raw_author_name":"Shiheng Yang","raw_affiliation_strings":["State Key Laboratory of Analog and Mixed-Signal VLSI, Institute of Microelectronics, University of Macau, Macao, China"],"raw_orcid":"https://orcid.org/0000-0002-4883-160X","affiliations":[{"raw_affiliation_string":"State Key Laboratory of Analog and Mixed-Signal VLSI, Institute of Microelectronics, University of Macau, Macao, China","institution_ids":["https://openalex.org/I204512498","https://openalex.org/I4210119392"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5104154736","display_name":"Shupeng Yu","orcid":null},"institutions":[{"id":"https://openalex.org/I204512498","display_name":"University of Macau","ror":"https://ror.org/01r4q9n85","country_code":"MO","type":"education","lineage":["https://openalex.org/I204512498"]},{"id":"https://openalex.org/I4210119392","display_name":"Institute of Microelectronics","ror":"https://ror.org/02s6gs133","country_code":"CN","type":"facility","lineage":["https://openalex.org/I19820366","https://openalex.org/I4210119392"]}],"countries":["CN","MO"],"is_corresponding":false,"raw_author_name":"Shupeng Yu","raw_affiliation_strings":["State Key Laboratory of Analog and Mixed-Signal VLSI, Institute of Microelectronics, University of Macau, Macao, China"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"State Key Laboratory of Analog and Mixed-Signal VLSI, Institute of Microelectronics, University of Macau, Macao, China","institution_ids":["https://openalex.org/I204512498","https://openalex.org/I4210119392"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5060389034","display_name":"Chio-In Ieong","orcid":null},"institutions":[{"id":"https://openalex.org/I204512498","display_name":"University of Macau","ror":"https://ror.org/01r4q9n85","country_code":"MO","type":"education","lineage":["https://openalex.org/I204512498"]},{"id":"https://openalex.org/I4210119392","display_name":"Institute of Microelectronics","ror":"https://ror.org/02s6gs133","country_code":"CN","type":"facility","lineage":["https://openalex.org/I19820366","https://openalex.org/I4210119392"]}],"countries":["CN","MO"],"is_corresponding":false,"raw_author_name":"Chio-In Ieong","raw_affiliation_strings":["State Key Laboratory of Analog and Mixed-Signal VLSI, Institute of Microelectronics, University of Macau, Macao, China"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"State Key Laboratory of Analog and Mixed-Signal VLSI, Institute of Microelectronics, University of Macau, Macao, China","institution_ids":["https://openalex.org/I204512498","https://openalex.org/I4210119392"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5058845450","display_name":"Pui\u2010In Mak","orcid":"https://orcid.org/0000-0002-3579-8740"},"institutions":[{"id":"https://openalex.org/I204512498","display_name":"University of Macau","ror":"https://ror.org/01r4q9n85","country_code":"MO","type":"education","lineage":["https://openalex.org/I204512498"]},{"id":"https://openalex.org/I4210119392","display_name":"Institute of Microelectronics","ror":"https://ror.org/02s6gs133","country_code":"CN","type":"facility","lineage":["https://openalex.org/I19820366","https://openalex.org/I4210119392"]}],"countries":["CN","MO"],"is_corresponding":false,"raw_author_name":"Pui-In Mak","raw_affiliation_strings":["State Key Laboratory of Analog and Mixed-Signal VLSI, Faculty of Science and Technology, ECE, Institute of Microelectronics, University of Macau, Macao, China"],"raw_orcid":"https://orcid.org/0000-0002-3579-8740","affiliations":[{"raw_affiliation_string":"State Key Laboratory of Analog and Mixed-Signal VLSI, Faculty of Science and Technology, ECE, Institute of Microelectronics, University of Macau, Macao, China","institution_ids":["https://openalex.org/I204512498","https://openalex.org/I4210119392"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5106943352","display_name":"Rui P. Martins","orcid":"https://orcid.org/0000-0003-2821-648X"},"institutions":[{"id":"https://openalex.org/I204512498","display_name":"University of Macau","ror":"https://ror.org/01r4q9n85","country_code":"MO","type":"education","lineage":["https://openalex.org/I204512498"]},{"id":"https://openalex.org/I4210119392","display_name":"Institute of Microelectronics","ror":"https://ror.org/02s6gs133","country_code":"CN","type":"facility","lineage":["https://openalex.org/I19820366","https://openalex.org/I4210119392"]}],"countries":["CN","MO"],"is_corresponding":false,"raw_author_name":"Rui P. Martins","raw_affiliation_strings":["State Key Laboratory of Analog and Mixed-Signal VLSI, Faculty of Science and Technology, ECE, Institute of Microelectronics, University of Macau, Macao, China"],"raw_orcid":"https://orcid.org/0000-0003-2821-648X","affiliations":[{"raw_affiliation_string":"State Key Laboratory of Analog and Mixed-Signal VLSI, Faculty of Science and Technology, ECE, Institute of Microelectronics, University of Macau, Macao, China","institution_ids":["https://openalex.org/I204512498","https://openalex.org/I4210119392"]}]}],"institutions":[],"countries_distinct_count":2,"institutions_distinct_count":8,"corresponding_author_ids":["https://openalex.org/A5038010873"],"corresponding_institution_ids":["https://openalex.org/I204512498","https://openalex.org/I4210119392"],"apc_list":null,"apc_paid":null,"fwci":1.0896,"has_fulltext":false,"cited_by_count":16,"citation_normalized_percentile":{"value":0.78319295,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":90,"max":97},"biblio":{"volume":"66","issue":"9","first_page":"3307","last_page":"3316"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11417","display_name":"Advancements in PLL and VCO Technologies","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11417","display_name":"Advancements in PLL and VCO Technologies","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10187","display_name":"Radio Frequency Integrated Circuit Design","score":0.9984999895095825,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11444","display_name":"Electromagnetic Compatibility and Noise Suppression","score":0.9957000017166138,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/phase-locked-loop","display_name":"Phase-locked loop","score":0.7925945520401001},{"id":"https://openalex.org/keywords/settling-time","display_name":"Settling time","score":0.7589339017868042},{"id":"https://openalex.org/keywords/dpll-algorithm","display_name":"DPLL algorithm","score":0.7179057598114014},{"id":"https://openalex.org/keywords/physics","display_name":"Physics","score":0.55906081199646},{"id":"https://openalex.org/keywords/cmos","display_name":"CMOS","score":0.5207688212394714},{"id":"https://openalex.org/keywords/settling","display_name":"Settling","score":0.4684619605541229},{"id":"https://openalex.org/keywords/calibration","display_name":"Calibration","score":0.4193337559700012},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.3360311985015869},{"id":"https://openalex.org/keywords/phase","display_name":"Phase (matter)","score":0.3154272139072418},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.16346320509910583},{"id":"https://openalex.org/keywords/step-response","display_name":"Step response","score":0.14200899004936218},{"id":"https://openalex.org/keywords/optoelectronics","display_name":"Optoelectronics","score":0.1376878321170807}],"concepts":[{"id":"https://openalex.org/C12707504","wikidata":"https://www.wikidata.org/wiki/Q52637","display_name":"Phase-locked loop","level":3,"score":0.7925945520401001},{"id":"https://openalex.org/C14781684","wikidata":"https://www.wikidata.org/wiki/Q3983320","display_name":"Settling time","level":3,"score":0.7589339017868042},{"id":"https://openalex.org/C143936061","wikidata":"https://www.wikidata.org/wiki/Q2030088","display_name":"DPLL algorithm","level":4,"score":0.7179057598114014},{"id":"https://openalex.org/C121332964","wikidata":"https://www.wikidata.org/wiki/Q413","display_name":"Physics","level":0,"score":0.55906081199646},{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.5207688212394714},{"id":"https://openalex.org/C173209714","wikidata":"https://www.wikidata.org/wiki/Q923906","display_name":"Settling","level":2,"score":0.4684619605541229},{"id":"https://openalex.org/C165838908","wikidata":"https://www.wikidata.org/wiki/Q736777","display_name":"Calibration","level":2,"score":0.4193337559700012},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.3360311985015869},{"id":"https://openalex.org/C44280652","wikidata":"https://www.wikidata.org/wiki/Q104837","display_name":"Phase (matter)","level":2,"score":0.3154272139072418},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.16346320509910583},{"id":"https://openalex.org/C160030872","wikidata":"https://www.wikidata.org/wiki/Q2142864","display_name":"Step response","level":2,"score":0.14200899004936218},{"id":"https://openalex.org/C49040817","wikidata":"https://www.wikidata.org/wiki/Q193091","display_name":"Optoelectronics","level":1,"score":0.1376878321170807},{"id":"https://openalex.org/C97355855","wikidata":"https://www.wikidata.org/wiki/Q11473","display_name":"Thermodynamics","level":1,"score":0.0},{"id":"https://openalex.org/C133731056","wikidata":"https://www.wikidata.org/wiki/Q4917288","display_name":"Control engineering","level":1,"score":0.0},{"id":"https://openalex.org/C62520636","wikidata":"https://www.wikidata.org/wiki/Q944","display_name":"Quantum mechanics","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/tcsi.2019.2926512","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tcsi.2019.2926512","pdf_url":null,"source":{"id":"https://openalex.org/S116977442","display_name":"IEEE Transactions on Circuits and Systems I Regular Papers","issn_l":"1549-8328","issn":["1549-8328","1558-0806"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Circuits and Systems I: Regular Papers","raw_type":"journal-article"}],"best_oa_location":null,"sustainable_development_goals":[{"display_name":"Affordable and clean energy","id":"https://metadata.un.org/sdg/7","score":0.7400000095367432}],"awards":[{"id":"https://openalex.org/G3678921673","display_name":null,"funder_award_id":"MYRG2018-00220-AMSV","funder_id":"https://openalex.org/F4320322841","funder_display_name":"Universidade de Macau"}],"funders":[{"id":"https://openalex.org/F4320321655","display_name":"Science and Technology Development Fund","ror":"https://ror.org/044vr6g03"},{"id":"https://openalex.org/F4320322841","display_name":"Universidade de Macau","ror":"https://ror.org/01r4q9n85"}],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":11,"referenced_works":["https://openalex.org/W1571758417","https://openalex.org/W1948778041","https://openalex.org/W1997287970","https://openalex.org/W2028941857","https://openalex.org/W2084208879","https://openalex.org/W2120500930","https://openalex.org/W2407917029","https://openalex.org/W2565866967","https://openalex.org/W2778427863","https://openalex.org/W2801792298","https://openalex.org/W2901368319"],"related_works":["https://openalex.org/W2380467267","https://openalex.org/W2325206724","https://openalex.org/W2059960378","https://openalex.org/W2103754166","https://openalex.org/W2058003010","https://openalex.org/W1994059163","https://openalex.org/W2082469970","https://openalex.org/W3113661469","https://openalex.org/W2110868325","https://openalex.org/W2376275105"],"abstract_inverted_index":{"This":[0],"paper":[1],"describes":[2],"a":[3,19,73,84],"wideband":[4],"ultra-fast-settling":[5],"fractional-N":[6],"bang-bang":[7],"digital":[8],"phase-locked":[9],"loop":[10,40,44],"(DPLL)":[11],"for":[12],"multi-ISM-band":[13],"ultra-low-power":[14],"(ULP)":[15],"radios.":[16],"We":[17],"propose":[18],"mismatch-free":[20],"digital-to-time-converter":[21],"(DTC)":[22],"gain":[23],"calibration":[24,30],"scheme":[25],"to":[26,53],"effectively":[27],"shorten":[28],"the":[29,33,43,55,67],"time,":[31],"while":[32],"split":[34],"coarse-fine":[35],"PLL":[36],"loops":[37],"with":[38],"different":[39],"bandwidths":[41],"accelerate":[42],"settling":[45,95],"speed.":[46],"The":[47,94],"employed":[48],"ring":[49],"VCO":[50],"(RVCO)":[51],"aids":[52],"extend":[54],"frequency":[56,75,109],"tuning":[57],"range":[58,77],"and":[59,82],"generate":[60],"multi-phase":[61],"outputs.":[62],"Prototyped":[63],"in":[64],"65-nm":[65],"CMOS,":[66],"DPLL":[68],"consumes":[69],"1.2\u20132.4":[70],"mW":[71],"over":[72],"wide":[74],"locking":[76],"of":[78,87],"68.3%":[79],"(1.3\u20132.65":[80],"GHz)":[81],"occupies":[83],"die":[85],"area":[86],"0.12":[88],"mm":[89],"<sup":[90],"xmlns:mml=\"http://www.w3.org/1998/Math/MathML\"":[91,99],"xmlns:xlink=\"http://www.w3.org/1999/xlink\">2</sup>":[92],".":[93],"time":[96],"measures":[97],"<inline-formula":[98],"xmlns:xlink=\"http://www.w3.org/1999/xlink\">":[100],"<tex-math":[101],"notation=\"LaTeX\">$8~\\mu":[102],"\\text{s}$":[103],"</tex-math></inline-formula>":[104],"at":[105],"an":[106],"82-MHz":[107],"initial":[108],"error.":[110]},"counts_by_year":[{"year":2025,"cited_by_count":2},{"year":2024,"cited_by_count":2},{"year":2023,"cited_by_count":3},{"year":2022,"cited_by_count":3},{"year":2021,"cited_by_count":2},{"year":2020,"cited_by_count":3},{"year":2019,"cited_by_count":1}],"updated_date":"2026-03-27T05:58:40.876381","created_date":"2025-10-10T00:00:00"}