{"id":"https://openalex.org/W2901080393","doi":"https://doi.org/10.1109/tcsi.2018.2877571","title":"Variation Aware Design of 50-Gbit/s, 5.027-fJ/bit Serializer Using Latency Combined Mux-Dual Latch for Inter-Chip Communication","display_name":"Variation Aware Design of 50-Gbit/s, 5.027-fJ/bit Serializer Using Latency Combined Mux-Dual Latch for Inter-Chip Communication","publication_year":2018,"publication_date":"2018-11-14","ids":{"openalex":"https://openalex.org/W2901080393","doi":"https://doi.org/10.1109/tcsi.2018.2877571","mag":"2901080393"},"language":"en","primary_location":{"id":"doi:10.1109/tcsi.2018.2877571","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tcsi.2018.2877571","pdf_url":null,"source":{"id":"https://openalex.org/S116977442","display_name":"IEEE Transactions on Circuits and Systems I Regular Papers","issn_l":"1549-8328","issn":["1549-8328","1558-0806"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Circuits and Systems I: Regular Papers","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5009067589","display_name":"Alak Majumder","orcid":"https://orcid.org/0000-0003-4775-8591"},"institutions":[{"id":"https://openalex.org/I57496824","display_name":"National Institute of Technology Arunachal Pradesh","ror":"https://ror.org/020cr8c43","country_code":"IN","type":"education","lineage":["https://openalex.org/I57496824"]}],"countries":["IN"],"is_corresponding":true,"raw_author_name":"Alak Majumder","raw_affiliation_strings":["Department of ECE, NIT Arunachal Pradesh, Arunachal Pradesh, India"],"affiliations":[{"raw_affiliation_string":"Department of ECE, NIT Arunachal Pradesh, Arunachal Pradesh, India","institution_ids":["https://openalex.org/I57496824"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5060494944","display_name":"Monalisa Das","orcid":"https://orcid.org/0000-0002-2125-4347"},"institutions":[{"id":"https://openalex.org/I57496824","display_name":"National Institute of Technology Arunachal Pradesh","ror":"https://ror.org/020cr8c43","country_code":"IN","type":"education","lineage":["https://openalex.org/I57496824"]}],"countries":["IN"],"is_corresponding":false,"raw_author_name":"Monalisa Das","raw_affiliation_strings":["Department of ECE, NIT Arunachal Pradesh, Arunachal Pradesh, India"],"affiliations":[{"raw_affiliation_string":"Department of ECE, NIT Arunachal Pradesh, Arunachal Pradesh, India","institution_ids":["https://openalex.org/I57496824"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5077892883","display_name":"Suraj Kumar Saw","orcid":"https://orcid.org/0000-0001-5732-7096"},"institutions":[{"id":"https://openalex.org/I57496824","display_name":"National Institute of Technology Arunachal Pradesh","ror":"https://ror.org/020cr8c43","country_code":"IN","type":"education","lineage":["https://openalex.org/I57496824"]}],"countries":["IN"],"is_corresponding":false,"raw_author_name":"Suraj Kumar Saw","raw_affiliation_strings":["Department of ECE, NIT Arunachal Pradesh, Arunachal Pradesh, India"],"affiliations":[{"raw_affiliation_string":"Department of ECE, NIT Arunachal Pradesh, Arunachal Pradesh, India","institution_ids":["https://openalex.org/I57496824"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5046326503","display_name":"Abir J. Mondal","orcid":"https://orcid.org/0000-0001-8023-4103"},"institutions":[{"id":"https://openalex.org/I57496824","display_name":"National Institute of Technology Arunachal Pradesh","ror":"https://ror.org/020cr8c43","country_code":"IN","type":"education","lineage":["https://openalex.org/I57496824"]}],"countries":["IN"],"is_corresponding":false,"raw_author_name":"Abir J. Mondal","raw_affiliation_strings":["Department of ECE, NIT Arunachal Pradesh, Arunachal Pradesh, India"],"affiliations":[{"raw_affiliation_string":"Department of ECE, NIT Arunachal Pradesh, Arunachal Pradesh, India","institution_ids":["https://openalex.org/I57496824"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5103238517","display_name":"Bidyut K. Bhattacharyya","orcid":"https://orcid.org/0000-0003-3933-3008"},"institutions":[{"id":"https://openalex.org/I196486160","display_name":"National Institute of Technology Agartala","ror":"https://ror.org/03swyrn62","country_code":"IN","type":"education","lineage":["https://openalex.org/I196486160"]}],"countries":["IN"],"is_corresponding":false,"raw_author_name":"Bidyut K. Bhattacharyya","raw_affiliation_strings":["Department of ECE, NIT Agartala, Tripura, India"],"affiliations":[{"raw_affiliation_string":"Department of ECE, NIT Agartala, Tripura, India","institution_ids":["https://openalex.org/I196486160"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":5,"corresponding_author_ids":["https://openalex.org/A5009067589"],"corresponding_institution_ids":["https://openalex.org/I57496824"],"apc_list":null,"apc_paid":null,"fwci":1.0099,"has_fulltext":false,"cited_by_count":6,"citation_normalized_percentile":{"value":0.75519433,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":97},"biblio":{"volume":"66","issue":"3","first_page":"1231","last_page":"1244"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9994000196456909,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9994000196456909,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9988999962806702,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10323","display_name":"Analog and Mixed-Signal Circuit Design","score":0.9984999895095825,"subfield":{"id":"https://openalex.org/subfields/2204","display_name":"Biomedical Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/multiplexer","display_name":"Multiplexer","score":0.7612245082855225},{"id":"https://openalex.org/keywords/gigabit","display_name":"Gigabit","score":0.7250064611434937},{"id":"https://openalex.org/keywords/chip","display_name":"Chip","score":0.562487006187439},{"id":"https://openalex.org/keywords/latency","display_name":"Latency (audio)","score":0.5534496307373047},{"id":"https://openalex.org/keywords/dual","display_name":"Dual (grammatical number)","score":0.5202744603157043},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.4556960165500641},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.3742697238922119},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.3507142961025238},{"id":"https://openalex.org/keywords/telecommunications","display_name":"Telecommunications","score":0.21701115369796753},{"id":"https://openalex.org/keywords/art","display_name":"Art","score":0.20867300033569336},{"id":"https://openalex.org/keywords/multiplexing","display_name":"Multiplexing","score":0.1680315136909485}],"concepts":[{"id":"https://openalex.org/C70970002","wikidata":"https://www.wikidata.org/wiki/Q189434","display_name":"Multiplexer","level":3,"score":0.7612245082855225},{"id":"https://openalex.org/C21922175","wikidata":"https://www.wikidata.org/wiki/Q3105497","display_name":"Gigabit","level":2,"score":0.7250064611434937},{"id":"https://openalex.org/C165005293","wikidata":"https://www.wikidata.org/wiki/Q1074500","display_name":"Chip","level":2,"score":0.562487006187439},{"id":"https://openalex.org/C82876162","wikidata":"https://www.wikidata.org/wiki/Q17096504","display_name":"Latency (audio)","level":2,"score":0.5534496307373047},{"id":"https://openalex.org/C2780980858","wikidata":"https://www.wikidata.org/wiki/Q110022","display_name":"Dual (grammatical number)","level":2,"score":0.5202744603157043},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.4556960165500641},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.3742697238922119},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.3507142961025238},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.21701115369796753},{"id":"https://openalex.org/C142362112","wikidata":"https://www.wikidata.org/wiki/Q735","display_name":"Art","level":0,"score":0.20867300033569336},{"id":"https://openalex.org/C19275194","wikidata":"https://www.wikidata.org/wiki/Q222903","display_name":"Multiplexing","level":2,"score":0.1680315136909485},{"id":"https://openalex.org/C124952713","wikidata":"https://www.wikidata.org/wiki/Q8242","display_name":"Literature","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/tcsi.2018.2877571","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tcsi.2018.2877571","pdf_url":null,"source":{"id":"https://openalex.org/S116977442","display_name":"IEEE Transactions on Circuits and Systems I Regular Papers","issn_l":"1549-8328","issn":["1549-8328","1558-0806"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Circuits and Systems I: Regular Papers","raw_type":"journal-article"}],"best_oa_location":null,"sustainable_development_goals":[{"score":0.9100000262260437,"id":"https://metadata.un.org/sdg/7","display_name":"Affordable and clean energy"}],"awards":[],"funders":[{"id":"https://openalex.org/F4320325255","display_name":"Ministry of Electronics and Information technology","ror":null}],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":26,"referenced_works":["https://openalex.org/W36964086","https://openalex.org/W589929473","https://openalex.org/W614374781","https://openalex.org/W1497405553","https://openalex.org/W1558809473","https://openalex.org/W1993254104","https://openalex.org/W1997433601","https://openalex.org/W1999090085","https://openalex.org/W2026574088","https://openalex.org/W2035413928","https://openalex.org/W2046926960","https://openalex.org/W2062133164","https://openalex.org/W2072569245","https://openalex.org/W2108014838","https://openalex.org/W2122931372","https://openalex.org/W2126340693","https://openalex.org/W2141825982","https://openalex.org/W2150983492","https://openalex.org/W2169859839","https://openalex.org/W2336871498","https://openalex.org/W2464946586","https://openalex.org/W2541730693","https://openalex.org/W2625345493","https://openalex.org/W4246911246","https://openalex.org/W6629947130","https://openalex.org/W6739632911"],"related_works":["https://openalex.org/W4323268213","https://openalex.org/W2101047079","https://openalex.org/W4242128654","https://openalex.org/W2152549830","https://openalex.org/W1993744883","https://openalex.org/W3197720232","https://openalex.org/W2388387398","https://openalex.org/W3203996584","https://openalex.org/W2082549546","https://openalex.org/W3022773140"],"abstract_inverted_index":{"The":[0,76,153,228],"conventional":[1],"MOS":[2],"current":[3,117],"mode":[4,95,118],"logic":[5],"(MCML)-based":[6],"multiplexer":[7,119],"needed":[8],"for":[9,64,160],"serializer":[10,32,140,157],"application":[11],"has":[12],"various":[13],"limitations,":[14],"such":[15,256],"as":[16,257],"low":[17],"voltage-swing,":[18],"substantial":[19],"power":[20,171,187,196],"consumption,":[21],"and":[22,74,105,136,147,172,180,219,249],"large":[23],"area":[24,135],"overhead.":[25],"In":[26],"the":[27,34,38,53,83,112,164,169],"circuit":[28,125],"arrangement":[29],"of":[30,40,72,80,82,108,142,155,190,198,205,216,222],"a":[31,114,186,195,213,220,235],"using":[33],"MCML-based":[35],"mux-tree":[36],"concept,":[37],"output":[39,91,203],"one":[41,237],"mux":[42,51],"at":[43,52,150,194,244,252],"any":[44],"stage":[45,55],"is":[46,96,126,208,231],"used":[47,63],"to":[48,87,131,176,184,233],"feed":[49],"another":[50],"next":[54],"through":[56,241],"some":[57],"latch":[58,124],"circuits,":[59],"which":[60],"are":[61,158,174],"basically":[62],"timing":[65],"synchronization":[66],"giving":[67],"away":[68],"penalty":[69],"in":[70,78,90,128,163],"terms":[71],"delay":[73,173,188],"area.":[75],"increase":[77],"number":[79],"stages":[81],"Serializer":[84],"may":[85],"lead":[86],"further":[88,132],"reduction":[89],"swing":[92,146,204],"(if":[93],"common":[94],"not":[97],"properly":[98],"set),":[99],"thereby":[100],"causing":[101],"signal":[102,148],"integrity":[103],"issues":[104],"finally":[106],"loss":[107],"data.":[109],"To":[110],"address":[111],"same,":[113],"latency":[115],"combined":[116],"incorporating":[120],"pMOS-based":[121],"dual":[122],"cross-coupled":[123],"unearthed":[127],"this":[129],"paper":[130],"outline":[133],"an":[134],"energy":[137],"efficient":[138],"high-speed":[139],"capable":[141],"maintaining":[143],"uniform":[144],"peak-to-peak":[145],"quality":[149],"differential":[151],"outputs.":[152],"simulations":[154],"new":[156],"performed":[159],"90-nm":[161],"CMOS":[162],"Cadence":[165],"Virtuoso":[166],"platform,":[167],"where":[168],"average":[170],"found":[175],"be":[177,234],"471.6":[178],"\u03bcW":[179],"93.9":[181],"ps,":[182],"respectively,":[183],"provide":[185],"product":[189],"43.8":[191],"fJ":[192],"only":[193],"supply":[197],"1":[199],"V.":[200],"An":[201],"improved":[202],"904":[206],"mV":[207],"also":[209,250],"noticed":[210],"along":[211],"with":[212],"data":[214],"rate":[215],"50":[217],"Gb/s":[218],"BER":[221],"<;10":[223],"<sup":[224],"xmlns:mml=\"http://www.w3.org/1998/Math/MathML\"":[225],"xmlns:xlink=\"http://www.w3.org/1999/xlink\">-12</sup>":[226],".":[227],"entire":[229],"design":[230],"proved":[232],"robust":[236],"after":[238],"simulating":[239],"it":[240],"Monte":[242],"Carlo":[243],"five":[245],"different":[246],"process":[247,254],"corners":[248],"validated":[251],"lower":[253],"nodes":[255],"28-nm":[258],"UMC.":[259]},"counts_by_year":[{"year":2025,"cited_by_count":1},{"year":2023,"cited_by_count":1},{"year":2020,"cited_by_count":1},{"year":2019,"cited_by_count":3}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}
