{"id":"https://openalex.org/W2889491624","doi":"https://doi.org/10.1109/tcsi.2018.2861463","title":"Overhead Requirements for Stateful Memristor Logic","display_name":"Overhead Requirements for Stateful Memristor Logic","publication_year":2018,"publication_date":"2018-08-27","ids":{"openalex":"https://openalex.org/W2889491624","doi":"https://doi.org/10.1109/tcsi.2018.2861463","mag":"2889491624"},"language":"en","primary_location":{"id":"doi:10.1109/tcsi.2018.2861463","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tcsi.2018.2861463","pdf_url":null,"source":{"id":"https://openalex.org/S116977442","display_name":"IEEE Transactions on Circuits and Systems I Regular Papers","issn_l":"1549-8328","issn":["1549-8328","1558-0806"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Circuits and Systems I: Regular Papers","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5088513405","display_name":"Xuan Hu","orcid":"https://orcid.org/0000-0002-7337-6637"},"institutions":[{"id":"https://openalex.org/I162577319","display_name":"The University of Texas at Dallas","ror":"https://ror.org/049emcs32","country_code":"US","type":"education","lineage":["https://openalex.org/I162577319"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Xuan Hu","raw_affiliation_strings":["Department of Electrical and Computer Engineering, The University of Texas at Dallas, Richardson, TX, USA"],"raw_orcid":"https://orcid.org/0000-0002-7337-6637","affiliations":[{"raw_affiliation_string":"Department of Electrical and Computer Engineering, The University of Texas at Dallas, Richardson, TX, USA","institution_ids":["https://openalex.org/I162577319"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5070969658","display_name":"Michael J. Schultis","orcid":null},"institutions":[{"id":"https://openalex.org/I162577319","display_name":"The University of Texas at Dallas","ror":"https://ror.org/049emcs32","country_code":"US","type":"education","lineage":["https://openalex.org/I162577319"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Michael J. Schultis","raw_affiliation_strings":["Department of Electrical and Computer Engineering, The University of Texas at Dallas, Richardson, TX, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Electrical and Computer Engineering, The University of Texas at Dallas, Richardson, TX, USA","institution_ids":["https://openalex.org/I162577319"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5052808693","display_name":"M. J. Kramer","orcid":"https://orcid.org/0000-0002-9097-6730"},"institutions":[{"id":"https://openalex.org/I162577319","display_name":"The University of Texas at Dallas","ror":"https://ror.org/049emcs32","country_code":"US","type":"education","lineage":["https://openalex.org/I162577319"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Matthew Kramer","raw_affiliation_strings":["Department of Electrical and Computer Engineering, The University of Texas at Dallas, Richardson, TX, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Electrical and Computer Engineering, The University of Texas at Dallas, Richardson, TX, USA","institution_ids":["https://openalex.org/I162577319"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5084845425","display_name":"Archit Bagla","orcid":null},"institutions":[{"id":"https://openalex.org/I162577319","display_name":"The University of Texas at Dallas","ror":"https://ror.org/049emcs32","country_code":"US","type":"education","lineage":["https://openalex.org/I162577319"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Archit Bagla","raw_affiliation_strings":["Department of Electrical and Computer Engineering, The University of Texas at Dallas, Richardson, TX, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Electrical and Computer Engineering, The University of Texas at Dallas, Richardson, TX, USA","institution_ids":["https://openalex.org/I162577319"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5072907055","display_name":"Akshay Shetty","orcid":"https://orcid.org/0000-0002-5893-9876"},"institutions":[{"id":"https://openalex.org/I162577319","display_name":"The University of Texas at Dallas","ror":"https://ror.org/049emcs32","country_code":"US","type":"education","lineage":["https://openalex.org/I162577319"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Akshay Shetty","raw_affiliation_strings":["Department of Electrical and Computer Engineering, The University of Texas at Dallas, Richardson, TX, USA"],"raw_orcid":"https://orcid.org/0000-0002-5893-9876","affiliations":[{"raw_affiliation_string":"Department of Electrical and Computer Engineering, The University of Texas at Dallas, Richardson, TX, USA","institution_ids":["https://openalex.org/I162577319"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5001887370","display_name":"Joseph S. Friedman","orcid":"https://orcid.org/0000-0001-9847-4455"},"institutions":[{"id":"https://openalex.org/I162577319","display_name":"The University of Texas at Dallas","ror":"https://ror.org/049emcs32","country_code":"US","type":"education","lineage":["https://openalex.org/I162577319"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Joseph S. Friedman","raw_affiliation_strings":["Department of Electrical and Computer Engineering, The University of Texas at Dallas, Richardson, TX, USA"],"raw_orcid":"https://orcid.org/0000-0001-9847-4455","affiliations":[{"raw_affiliation_string":"Department of Electrical and Computer Engineering, The University of Texas at Dallas, Richardson, TX, USA","institution_ids":["https://openalex.org/I162577319"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":[],"corresponding_institution_ids":["https://openalex.org/I162577319"],"apc_list":null,"apc_paid":null,"fwci":2.357,"has_fulltext":false,"cited_by_count":30,"citation_normalized_percentile":{"value":0.89367345,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":94,"max":99},"biblio":{"volume":"66","issue":"1","first_page":"263","last_page":"273"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10502","display_name":"Advanced Memory and Neural Computing","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10502","display_name":"Advanced Memory and Neural Computing","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T12808","display_name":"Ferroelectric and Negative Capacitance Devices","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10472","display_name":"Semiconductor materials and devices","score":0.9993000030517578,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/memristor","display_name":"Memristor","score":0.9216187596321106},{"id":"https://openalex.org/keywords/pass-transistor-logic","display_name":"Pass transistor logic","score":0.6020174622535706},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.581863284111023},{"id":"https://openalex.org/keywords/cmos","display_name":"CMOS","score":0.5707998275756836},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.5673516988754272},{"id":"https://openalex.org/keywords/logic-family","display_name":"Logic family","score":0.5124099850654602},{"id":"https://openalex.org/keywords/stateful-firewall","display_name":"Stateful firewall","score":0.5013113021850586},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.4300629496574402},{"id":"https://openalex.org/keywords/overhead","display_name":"Overhead (engineering)","score":0.42946022748947144},{"id":"https://openalex.org/keywords/electronic-circuit","display_name":"Electronic circuit","score":0.3755660057067871},{"id":"https://openalex.org/keywords/logic-synthesis","display_name":"Logic synthesis","score":0.33598268032073975},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.2919391989707947},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.2762197256088257},{"id":"https://openalex.org/keywords/digital-electronics","display_name":"Digital electronics","score":0.2698401212692261}],"concepts":[{"id":"https://openalex.org/C150072547","wikidata":"https://www.wikidata.org/wiki/Q212923","display_name":"Memristor","level":2,"score":0.9216187596321106},{"id":"https://openalex.org/C198521697","wikidata":"https://www.wikidata.org/wiki/Q7142438","display_name":"Pass transistor logic","level":4,"score":0.6020174622535706},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.581863284111023},{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.5707998275756836},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.5673516988754272},{"id":"https://openalex.org/C162454741","wikidata":"https://www.wikidata.org/wiki/Q173359","display_name":"Logic family","level":4,"score":0.5124099850654602},{"id":"https://openalex.org/C22927095","wikidata":"https://www.wikidata.org/wiki/Q1784206","display_name":"Stateful firewall","level":3,"score":0.5013113021850586},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.4300629496574402},{"id":"https://openalex.org/C2779960059","wikidata":"https://www.wikidata.org/wiki/Q7113681","display_name":"Overhead (engineering)","level":2,"score":0.42946022748947144},{"id":"https://openalex.org/C134146338","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Electronic circuit","level":2,"score":0.3755660057067871},{"id":"https://openalex.org/C157922185","wikidata":"https://www.wikidata.org/wiki/Q173198","display_name":"Logic synthesis","level":3,"score":0.33598268032073975},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.2919391989707947},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.2762197256088257},{"id":"https://openalex.org/C81843906","wikidata":"https://www.wikidata.org/wiki/Q173156","display_name":"Digital electronics","level":3,"score":0.2698401212692261},{"id":"https://openalex.org/C31258907","wikidata":"https://www.wikidata.org/wiki/Q1301371","display_name":"Computer network","level":1,"score":0.0},{"id":"https://openalex.org/C158379750","wikidata":"https://www.wikidata.org/wiki/Q214111","display_name":"Network packet","level":2,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/tcsi.2018.2861463","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tcsi.2018.2861463","pdf_url":null,"source":{"id":"https://openalex.org/S116977442","display_name":"IEEE Transactions on Circuits and Systems I Regular Papers","issn_l":"1549-8328","issn":["1549-8328","1558-0806"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Circuits and Systems I: Regular Papers","raw_type":"journal-article"}],"best_oa_location":null,"sustainable_development_goals":[{"display_name":"Affordable and clean energy","id":"https://metadata.un.org/sdg/7","score":0.7799999713897705}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":46,"referenced_works":["https://openalex.org/W1578783943","https://openalex.org/W1589090205","https://openalex.org/W1662522325","https://openalex.org/W1810325903","https://openalex.org/W1833852352","https://openalex.org/W1975647260","https://openalex.org/W1978002406","https://openalex.org/W1982666872","https://openalex.org/W1984050685","https://openalex.org/W2000330909","https://openalex.org/W2004782555","https://openalex.org/W2018774711","https://openalex.org/W2022691368","https://openalex.org/W2025674646","https://openalex.org/W2030671441","https://openalex.org/W2036687738","https://openalex.org/W2037616057","https://openalex.org/W2037906217","https://openalex.org/W2063517113","https://openalex.org/W2064756415","https://openalex.org/W2066280488","https://openalex.org/W2081729575","https://openalex.org/W2095928257","https://openalex.org/W2107969613","https://openalex.org/W2108343465","https://openalex.org/W2112181056","https://openalex.org/W2117379410","https://openalex.org/W2122148191","https://openalex.org/W2126810113","https://openalex.org/W2126856948","https://openalex.org/W2136288682","https://openalex.org/W2153501607","https://openalex.org/W2156694126","https://openalex.org/W2162651880","https://openalex.org/W2169757251","https://openalex.org/W2170095368","https://openalex.org/W2290310756","https://openalex.org/W2313016471","https://openalex.org/W2320724838","https://openalex.org/W2335248059","https://openalex.org/W2397312330","https://openalex.org/W2569842290","https://openalex.org/W2576918530","https://openalex.org/W2623494632","https://openalex.org/W2741582625","https://openalex.org/W2770634378"],"related_works":["https://openalex.org/W2066280488","https://openalex.org/W2134806353","https://openalex.org/W2469547363","https://openalex.org/W2072804543","https://openalex.org/W4242420860","https://openalex.org/W2791331661","https://openalex.org/W1538783473","https://openalex.org/W2509369410","https://openalex.org/W2775500725","https://openalex.org/W2795192717"],"abstract_inverted_index":{"Memristors":[0,19],"are":[1,20,187],"being":[2],"explored":[3],"as":[4],"a":[5,26,105,139],"potential":[6],"technology":[7],"to":[8,43,56,80,109,181],"replace":[9],"CMOS":[10,75,91,125,141,164],"for":[11,93,100,162,176],"logic-in-memory":[12],"systems":[13],"that":[14,24,29,77,121,137,144,171,186],"exploit":[15],"the":[16,33,38,41,49,73,88,114,122,128,145,149,169,172,190],"memristive":[17],"non-volatility.":[18],"two-terminal,":[21],"non-volatile":[22],"device":[23],"exhibit":[25],"variable":[27],"resistance":[28],"is":[30,78,98,155],"dependent":[31],"on":[32],"applied":[34],"voltage":[35],"history":[36],"of":[37,54,66,113,124,134,138,148],"device,":[39],"providing":[40],"capability":[42],"store":[44],"and":[45,104,143],"process":[46],"information":[47],"within":[48],"same":[50],"structure.":[51],"The":[52,118],"ability":[53],"memristors":[55,97,191],"perform":[57],"logic":[58,68,83,95,102,151,179],"has":[59],"been":[60],"previously":[61],"demonstrated,":[62],"but":[63],"previous":[64],"analyses":[65],"memristor":[67,82,150,178],"efficiency":[69,184],"have":[70],"not":[71],"included":[72],"overhead":[74,90,129,153,173],"circuitry":[76,92,130,154],"required":[79,89],"control":[81],"operations.":[84],"In":[85],"this":[86],"paper,":[87],"implementing":[94],"with":[96,152],"evaluated":[99],"standard":[101],"gates":[103],"one-bit":[106],"full":[107],"adder":[108],"enable":[110,168],"an":[111],"analysis":[112],"overall":[115],"system":[116],"efficiency.":[117],"results":[119,167],"show":[120],"number":[123],"devices":[126],"in":[127],"can":[131],"be":[132],"upwards":[133],"50":[135],"times":[136,159],"conventional":[140,163],"implementation,":[142],"power-delay":[146],"product":[147],"roughly":[156],"one":[157],"billion":[158],"greater":[160],"than":[161],"circuits.":[165],"These":[166],"conclusion":[170],"circuit":[174],"requirements":[175],"stateful":[177],"threaten":[180],"negate":[182],"any":[183],"improvements":[185],"achieved":[188],"by":[189],"themselves.":[192]},"counts_by_year":[{"year":2025,"cited_by_count":2},{"year":2024,"cited_by_count":3},{"year":2023,"cited_by_count":4},{"year":2022,"cited_by_count":3},{"year":2021,"cited_by_count":3},{"year":2020,"cited_by_count":9},{"year":2019,"cited_by_count":4},{"year":2018,"cited_by_count":2}],"updated_date":"2026-06-26T08:34:08.712188","created_date":"2025-10-10T00:00:00"}