{"id":"https://openalex.org/W2792232768","doi":"https://doi.org/10.1109/tcsi.2018.2813326","title":"Pentavariate &lt;inline-formula&gt; &lt;tex-math notation=\"LaTeX\"&gt;$V_{\\mathrm{min}}$ &lt;/tex-math&gt; &lt;/inline-formula&gt; Analysis of a Subthreshold 10T SRAM Bit Cell With Variation Tolerant Write and Divided Bit-Line Read","display_name":"Pentavariate &lt;inline-formula&gt; &lt;tex-math notation=\"LaTeX\"&gt;$V_{\\mathrm{min}}$ &lt;/tex-math&gt; &lt;/inline-formula&gt; Analysis of a Subthreshold 10T SRAM Bit Cell With Variation Tolerant Write and Divided Bit-Line Read","publication_year":2018,"publication_date":"2018-03-22","ids":{"openalex":"https://openalex.org/W2792232768","doi":"https://doi.org/10.1109/tcsi.2018.2813326","mag":"2792232768"},"language":"en","primary_location":{"id":"doi:10.1109/tcsi.2018.2813326","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tcsi.2018.2813326","pdf_url":null,"source":{"id":"https://openalex.org/S116977442","display_name":"IEEE Transactions on Circuits and Systems I Regular Papers","issn_l":"1549-8328","issn":["1549-8328","1558-0806"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Circuits and Systems I: Regular Papers","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5101771348","display_name":"Shourya Gupta","orcid":"https://orcid.org/0000-0002-1804-5202"},"institutions":[{"id":"https://openalex.org/I887998513","display_name":"Bharati Vidyapeeth Deemed University","ror":"https://ror.org/0052mmx10","country_code":"IN","type":"education","lineage":["https://openalex.org/I887998513"]}],"countries":["IN"],"is_corresponding":false,"raw_author_name":"Shourya Gupta","raw_affiliation_strings":["Bharati Vidyapeeth\u2019s College of Engineering, New Delhi, India","Bharati Vidyapeeth's College of Engineering, New Delhi, India"],"raw_orcid":"https://orcid.org/0000-0002-1804-5202","affiliations":[{"raw_affiliation_string":"Bharati Vidyapeeth\u2019s College of Engineering, New Delhi, India","institution_ids":["https://openalex.org/I887998513"]},{"raw_affiliation_string":"Bharati Vidyapeeth's College of Engineering, New Delhi, India","institution_ids":["https://openalex.org/I887998513"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5082620922","display_name":"Kirti Gupta","orcid":"https://orcid.org/0000-0003-0565-0654"},"institutions":[{"id":"https://openalex.org/I887998513","display_name":"Bharati Vidyapeeth Deemed University","ror":"https://ror.org/0052mmx10","country_code":"IN","type":"education","lineage":["https://openalex.org/I887998513"]}],"countries":["IN"],"is_corresponding":false,"raw_author_name":"Kirti Gupta","raw_affiliation_strings":["Bharati Vidyapeeth\u2019s College of Engineering, New Delhi, India","Bharati Vidyapeeth's College of Engineering, New Delhi, India"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Bharati Vidyapeeth\u2019s College of Engineering, New Delhi, India","institution_ids":["https://openalex.org/I887998513"]},{"raw_affiliation_string":"Bharati Vidyapeeth's College of Engineering, New Delhi, India","institution_ids":["https://openalex.org/I887998513"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5022476734","display_name":"Neeta Pandey","orcid":"https://orcid.org/0000-0003-2911-7061"},"institutions":[{"id":"https://openalex.org/I863896202","display_name":"Delhi Technological University","ror":"https://ror.org/01ztcvt22","country_code":"IN","type":"education","lineage":["https://openalex.org/I863896202"]}],"countries":["IN"],"is_corresponding":false,"raw_author_name":"Neeta Pandey","raw_affiliation_strings":["ECE Department, Delhi Technological University, Delhi, India"],"raw_orcid":"https://orcid.org/0000-0003-2911-7061","affiliations":[{"raw_affiliation_string":"ECE Department, Delhi Technological University, Delhi, India","institution_ids":["https://openalex.org/I863896202"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":3,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":2.226,"has_fulltext":false,"cited_by_count":40,"citation_normalized_percentile":{"value":0.88347298,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":90,"max":99},"biblio":{"volume":"65","issue":"10","first_page":"3326","last_page":"3337"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10558","display_name":"Advancements in Semiconductor Devices and Circuit Design","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10472","display_name":"Semiconductor materials and devices","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/static-random-access-memory","display_name":"Static random-access memory","score":0.8595062494277954},{"id":"https://openalex.org/keywords/subthreshold-conduction","display_name":"Subthreshold conduction","score":0.8116055727005005},{"id":"https://openalex.org/keywords/topology","display_name":"Topology (electrical circuits)","score":0.5399295091629028},{"id":"https://openalex.org/keywords/transistor","display_name":"Transistor","score":0.5153786540031433},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.48080912232398987},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.3779647946357727},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.36430901288986206},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.3423108458518982},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.34162241220474243},{"id":"https://openalex.org/keywords/physics","display_name":"Physics","score":0.3343578577041626},{"id":"https://openalex.org/keywords/voltage","display_name":"Voltage","score":0.29841893911361694},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.1914721429347992}],"concepts":[{"id":"https://openalex.org/C68043766","wikidata":"https://www.wikidata.org/wiki/Q267416","display_name":"Static random-access memory","level":2,"score":0.8595062494277954},{"id":"https://openalex.org/C156465305","wikidata":"https://www.wikidata.org/wiki/Q1658601","display_name":"Subthreshold conduction","level":4,"score":0.8116055727005005},{"id":"https://openalex.org/C184720557","wikidata":"https://www.wikidata.org/wiki/Q7825049","display_name":"Topology (electrical circuits)","level":2,"score":0.5399295091629028},{"id":"https://openalex.org/C172385210","wikidata":"https://www.wikidata.org/wiki/Q5339","display_name":"Transistor","level":3,"score":0.5153786540031433},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.48080912232398987},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.3779647946357727},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.36430901288986206},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.3423108458518982},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.34162241220474243},{"id":"https://openalex.org/C121332964","wikidata":"https://www.wikidata.org/wiki/Q413","display_name":"Physics","level":0,"score":0.3343578577041626},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.29841893911361694},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.1914721429347992}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/tcsi.2018.2813326","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tcsi.2018.2813326","pdf_url":null,"source":{"id":"https://openalex.org/S116977442","display_name":"IEEE Transactions on Circuits and Systems I Regular Papers","issn_l":"1549-8328","issn":["1549-8328","1558-0806"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Circuits and Systems I: Regular Papers","raw_type":"journal-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":36,"referenced_works":["https://openalex.org/W1496316476","https://openalex.org/W1968464410","https://openalex.org/W1988117382","https://openalex.org/W1995329733","https://openalex.org/W2002612140","https://openalex.org/W2004965314","https://openalex.org/W2006292752","https://openalex.org/W2035589388","https://openalex.org/W2036991999","https://openalex.org/W2064136443","https://openalex.org/W2067168777","https://openalex.org/W2073818373","https://openalex.org/W2081490067","https://openalex.org/W2093108390","https://openalex.org/W2095953597","https://openalex.org/W2102655721","https://openalex.org/W2106264726","https://openalex.org/W2106339466","https://openalex.org/W2111701388","https://openalex.org/W2112602631","https://openalex.org/W2114418221","https://openalex.org/W2118016286","https://openalex.org/W2119520935","https://openalex.org/W2131833150","https://openalex.org/W2133614817","https://openalex.org/W2136393784","https://openalex.org/W2144289559","https://openalex.org/W2148604743","https://openalex.org/W2154477062","https://openalex.org/W2155275912","https://openalex.org/W2162583644","https://openalex.org/W2198948050","https://openalex.org/W2212894501","https://openalex.org/W2248790281","https://openalex.org/W6676822853","https://openalex.org/W6680178178"],"related_works":["https://openalex.org/W2127734757","https://openalex.org/W2008627543","https://openalex.org/W1979342820","https://openalex.org/W2295018350","https://openalex.org/W2793704047","https://openalex.org/W2166731074","https://openalex.org/W2147030133","https://openalex.org/W2751272872","https://openalex.org/W4312057941","https://openalex.org/W1979588396"],"abstract_inverted_index":{"Subthreshold":[0],"and":[1,11,110,157,171,180],"near-threshold":[2],"operations":[3],"are":[4],"viable":[5,186],"approaches":[6],"towards":[7],"reducing":[8,95],"both":[9,155],"static":[10,156],"dynamic":[12,158],"power":[13,175,193],"in":[14,23,41,71,94,121],"Static":[15],"Random":[16],"Access":[17],"Memory":[18],"(SRAM).":[19],"However,":[20],"supply":[21],"scaling":[22],"SRAM":[24,60],"cells":[25,129],"is":[26,35],"severely":[27],"limited":[28],"by":[29,38],"process":[30],"variations.":[31],"Additionally,":[32],"cell":[33,61,91,166],"performance":[34],"greatly":[36],"affected":[37],"local":[39],"mismatch":[40],"subthreshold":[42,73],"region,":[43],"thereby":[44,101],"prohibiting":[45],"low":[46,192],"voltage":[47],"operation.":[48],"In":[49,106],"order":[50],"to":[51,108,169],"mitigate":[52],"these":[53],"issues,":[54],"we":[55],"present":[56],"a":[57,66,149,185],"ten-transistor":[58],"(10T)":[59],"with":[62],"capability":[63],"of":[64,78,88,127],"performing":[65],"variation":[67],"tolerant":[68],"write":[69,111],"operation":[70],"deep":[72],"region":[74],"without":[75],"the":[76,89,96,113,134,163,177],"implementation":[77],"additional":[79],"peripheral":[80],"circuitry":[81],"or":[82,191],"assist":[83],"technique.":[84],"The":[85,125],"unique":[86],"topology":[87],"proposed":[90,164],"also":[92,117],"aids":[93],"bit":[97],"line":[98],"offset":[99],"voltage,":[100],"improving":[102],"read":[103,109],"access":[104],"performance.":[105],"addition":[107],"performance,":[112],"hold":[114,174],"stability":[115],"has":[116,130],"been":[118,131],"improved,":[119],"resulting":[120],"significant":[122],"Vmin":[123,126],"gains.":[124],"all":[128],"evaluated":[132],"at":[133],"6\u03c3":[135],"failure":[136],"point":[137],"(P":[138],"<sub":[139],"xmlns:mml=\"http://www.w3.org/1998/Math/MathML\"":[140,145],"xmlns:xlink=\"http://www.w3.org/1999/xlink\">Fail</sub>":[141],"=":[142],"10":[143],"<sup":[144],"xmlns:xlink=\"http://www.w3.org/1999/xlink\">-9</sup>":[146],")":[147],"using":[148],"comprehensive":[150],"pentavariate":[151],"probability":[152],"anaylsis,":[153],"considering":[154],"measures.":[159],"At":[160],"respective":[161],"Vmin,":[162],"10T":[165],"consumes":[167],"up":[168],"39\u00d7":[170],"6.6\u00d7":[172],"lower":[173],"than":[176],"conventional":[178],"6T":[179],"8T":[181],"cells,":[182],"making":[183],"it":[184],"candidate":[187],"for":[188],"portable":[189],"electronics":[190],"sensors.":[194]},"counts_by_year":[{"year":2026,"cited_by_count":2},{"year":2025,"cited_by_count":4},{"year":2024,"cited_by_count":5},{"year":2023,"cited_by_count":5},{"year":2022,"cited_by_count":7},{"year":2021,"cited_by_count":7},{"year":2020,"cited_by_count":6},{"year":2019,"cited_by_count":3},{"year":2018,"cited_by_count":1}],"updated_date":"2026-06-11T09:08:48.828518","created_date":"2025-10-10T00:00:00"}
