{"id":"https://openalex.org/W2781947136","doi":"https://doi.org/10.1109/tcsi.2017.2784319","title":"A Flexible, Low-Power Analog PLL for SoC and Processors in 14nm CMOS","display_name":"A Flexible, Low-Power Analog PLL for SoC and Processors in 14nm CMOS","publication_year":2018,"publication_date":"2018-01-05","ids":{"openalex":"https://openalex.org/W2781947136","doi":"https://doi.org/10.1109/tcsi.2017.2784319","mag":"2781947136"},"language":"en","primary_location":{"id":"doi:10.1109/tcsi.2017.2784319","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tcsi.2017.2784319","pdf_url":null,"source":{"id":"https://openalex.org/S116977442","display_name":"IEEE Transactions on Circuits and Systems I Regular Papers","issn_l":"1549-8328","issn":["1549-8328","1558-0806"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Circuits and Systems I: Regular Papers","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5102873292","display_name":"Kuan-Yueh James Shen","orcid":"https://orcid.org/0000-0003-2796-2683"},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":true,"raw_author_name":"Kuan-Yueh Shen","raw_affiliation_strings":["Intel Corporation, Hillsboro, OR, USA","Intel Corporation, Hillsboro, OR USA#TAB#"],"raw_orcid":"https://orcid.org/0000-0003-2796-2683","affiliations":[{"raw_affiliation_string":"Intel Corporation, Hillsboro, OR, USA","institution_ids":["https://openalex.org/I1343180700"]},{"raw_affiliation_string":"Intel Corporation, Hillsboro, OR USA#TAB#","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5019254487","display_name":"Syed Feruz Syed Farooq","orcid":null},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Syed Feruz Syed Farooq","raw_affiliation_strings":["Intel Corporation, Hillsboro, OR, USA","Intel Corporation, Hillsboro, OR USA#TAB#"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Intel Corporation, Hillsboro, OR, USA","institution_ids":["https://openalex.org/I1343180700"]},{"raw_affiliation_string":"Intel Corporation, Hillsboro, OR USA#TAB#","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5018623391","display_name":"Y. Fan","orcid":"https://orcid.org/0000-0001-5914-2765"},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Yongping Fan","raw_affiliation_strings":["Intel Corporation, Hillsboro, OR, USA","Intel Corporation, Hillsboro, OR USA#TAB#"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Intel Corporation, Hillsboro, OR, USA","institution_ids":["https://openalex.org/I1343180700"]},{"raw_affiliation_string":"Intel Corporation, Hillsboro, OR USA#TAB#","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5042110041","display_name":"Khoa Nguyen","orcid":"https://orcid.org/0000-0002-7638-6654"},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Khoa Minh Nguyen","raw_affiliation_strings":["Intel Corporation, Hillsboro, OR, USA","Intel Corporation, Hillsboro, OR USA#TAB#"],"raw_orcid":"https://orcid.org/0000-0002-7638-6654","affiliations":[{"raw_affiliation_string":"Intel Corporation, Hillsboro, OR, USA","institution_ids":["https://openalex.org/I1343180700"]},{"raw_affiliation_string":"Intel Corporation, Hillsboro, OR USA#TAB#","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5052811737","display_name":"Qi Wang","orcid":"https://orcid.org/0000-0002-6327-0468"},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Qi Wang","raw_affiliation_strings":["Intel Corporation, Hillsboro, OR, USA","Intel Corporation, Hillsboro, OR USA#TAB#"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Intel Corporation, Hillsboro, OR, USA","institution_ids":["https://openalex.org/I1343180700"]},{"raw_affiliation_string":"Intel Corporation, Hillsboro, OR USA#TAB#","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5062396672","display_name":"Mark Neidengard","orcid":null},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Mark L. Neidengard","raw_affiliation_strings":["Intel Corporation, Hillsboro, OR, USA","Intel Corporation, Hillsboro, OR USA#TAB#"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Intel Corporation, Hillsboro, OR, USA","institution_ids":["https://openalex.org/I1343180700"]},{"raw_affiliation_string":"Intel Corporation, Hillsboro, OR USA#TAB#","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5034919212","display_name":"Nasser Kurd","orcid":null},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Nasser Kurd","raw_affiliation_strings":["Intel Corporation, Hillsboro, OR, USA","Intel Corporation, Hillsboro, OR USA#TAB#"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Intel Corporation, Hillsboro, OR, USA","institution_ids":["https://openalex.org/I1343180700"]},{"raw_affiliation_string":"Intel Corporation, Hillsboro, OR USA#TAB#","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5087380109","display_name":"Amr Elshazly","orcid":"https://orcid.org/0000-0002-0628-9138"},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Amr Elshazly","raw_affiliation_strings":["Intel Corporation, Hillsboro, OR, USA","Intel Corporation, Hillsboro, OR USA#TAB#"],"raw_orcid":"https://orcid.org/0000-0002-0628-9138","affiliations":[{"raw_affiliation_string":"Intel Corporation, Hillsboro, OR, USA","institution_ids":["https://openalex.org/I1343180700"]},{"raw_affiliation_string":"Intel Corporation, Hillsboro, OR USA#TAB#","institution_ids":["https://openalex.org/I1343180700"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":8,"corresponding_author_ids":["https://openalex.org/A5102873292"],"corresponding_institution_ids":["https://openalex.org/I1343180700"],"apc_list":null,"apc_paid":null,"fwci":0.7853,"has_fulltext":false,"cited_by_count":14,"citation_normalized_percentile":{"value":0.72972557,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":90,"max":97},"biblio":{"volume":"65","issue":"7","first_page":"2109","last_page":"2117"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11417","display_name":"Advancements in PLL and VCO Technologies","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11417","display_name":"Advancements in PLL and VCO Technologies","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10187","display_name":"Radio Frequency Integrated Circuit Design","score":0.9984999895095825,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11444","display_name":"Electromagnetic Compatibility and Noise Suppression","score":0.9973000288009644,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/phase-locked-loop","display_name":"Phase-locked loop","score":0.8491330146789551},{"id":"https://openalex.org/keywords/jitter","display_name":"Jitter","score":0.7906606197357178},{"id":"https://openalex.org/keywords/cmos","display_name":"CMOS","score":0.7554922103881836},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.6187613010406494},{"id":"https://openalex.org/keywords/resistor","display_name":"Resistor","score":0.5637933611869812},{"id":"https://openalex.org/keywords/bandwidth","display_name":"Bandwidth (computing)","score":0.5300146341323853},{"id":"https://openalex.org/keywords/capacitor","display_name":"Capacitor","score":0.49918651580810547},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.47476768493652344},{"id":"https://openalex.org/keywords/pll-multibit","display_name":"PLL multibit","score":0.4539782702922821},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.43313854932785034},{"id":"https://openalex.org/keywords/power","display_name":"Power (physics)","score":0.4152461886405945},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.33985137939453125},{"id":"https://openalex.org/keywords/physics","display_name":"Physics","score":0.20047327876091003},{"id":"https://openalex.org/keywords/telecommunications","display_name":"Telecommunications","score":0.1612655520439148},{"id":"https://openalex.org/keywords/voltage","display_name":"Voltage","score":0.14527952671051025}],"concepts":[{"id":"https://openalex.org/C12707504","wikidata":"https://www.wikidata.org/wiki/Q52637","display_name":"Phase-locked loop","level":3,"score":0.8491330146789551},{"id":"https://openalex.org/C134652429","wikidata":"https://www.wikidata.org/wiki/Q1052698","display_name":"Jitter","level":2,"score":0.7906606197357178},{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.7554922103881836},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.6187613010406494},{"id":"https://openalex.org/C137488568","wikidata":"https://www.wikidata.org/wiki/Q5321","display_name":"Resistor","level":3,"score":0.5637933611869812},{"id":"https://openalex.org/C2776257435","wikidata":"https://www.wikidata.org/wiki/Q1576430","display_name":"Bandwidth (computing)","level":2,"score":0.5300146341323853},{"id":"https://openalex.org/C52192207","wikidata":"https://www.wikidata.org/wiki/Q5322","display_name":"Capacitor","level":3,"score":0.49918651580810547},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.47476768493652344},{"id":"https://openalex.org/C77881186","wikidata":"https://www.wikidata.org/wiki/Q7119642","display_name":"PLL multibit","level":4,"score":0.4539782702922821},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.43313854932785034},{"id":"https://openalex.org/C163258240","wikidata":"https://www.wikidata.org/wiki/Q25342","display_name":"Power (physics)","level":2,"score":0.4152461886405945},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.33985137939453125},{"id":"https://openalex.org/C121332964","wikidata":"https://www.wikidata.org/wiki/Q413","display_name":"Physics","level":0,"score":0.20047327876091003},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.1612655520439148},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.14527952671051025},{"id":"https://openalex.org/C62520636","wikidata":"https://www.wikidata.org/wiki/Q944","display_name":"Quantum mechanics","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/tcsi.2017.2784319","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tcsi.2017.2784319","pdf_url":null,"source":{"id":"https://openalex.org/S116977442","display_name":"IEEE Transactions on Circuits and Systems I Regular Papers","issn_l":"1549-8328","issn":["1549-8328","1558-0806"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Circuits and Systems I: Regular Papers","raw_type":"journal-article"}],"best_oa_location":null,"sustainable_development_goals":[{"display_name":"Affordable and clean energy","id":"https://metadata.un.org/sdg/7","score":0.8500000238418579}],"awards":[],"funders":[{"id":"https://openalex.org/F4320307102","display_name":"Intel Corporation","ror":"https://ror.org/01ek73717"},{"id":"https://openalex.org/F4320309668","display_name":"Graduate School, Purdue University","ror":"https://ror.org/02dqehb95"},{"id":"https://openalex.org/F4320311401","display_name":"Oregon State University","ror":"https://ror.org/00ysfqy60"},{"id":"https://openalex.org/F4320322439","display_name":"Northwest University","ror":"https://ror.org/00z3td547"}],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":19,"referenced_works":["https://openalex.org/W1566916904","https://openalex.org/W2035713928","https://openalex.org/W2038284388","https://openalex.org/W2075004943","https://openalex.org/W2087345965","https://openalex.org/W2098555327","https://openalex.org/W2104147443","https://openalex.org/W2108324407","https://openalex.org/W2112008043","https://openalex.org/W2144281377","https://openalex.org/W2153267648","https://openalex.org/W2154332266","https://openalex.org/W2172440946","https://openalex.org/W2291959676","https://openalex.org/W6659905895","https://openalex.org/W6669415149","https://openalex.org/W6672536603","https://openalex.org/W6676844732","https://openalex.org/W6697119272"],"related_works":["https://openalex.org/W1997845338","https://openalex.org/W2066059486","https://openalex.org/W2789658793","https://openalex.org/W2120528056","https://openalex.org/W2025440251","https://openalex.org/W2128445318","https://openalex.org/W2356562257","https://openalex.org/W2022851692","https://openalex.org/W2218086155","https://openalex.org/W1491025498"],"abstract_inverted_index":{"This":[0],"paper":[1],"presents":[2],"a":[3,29],"PLL":[4,40,76,103,108,128],"supporting":[5],"diverse":[6],"low-power":[7,30],"clocking":[8],"needs":[9],"including":[10],"wide":[11],"input":[12],"(6-200":[13],"MHz)":[14],"and":[15,21,51,83],"output":[16],"(0.15-5":[17],"GHz)":[18],"frequency":[19],"ranges":[20],"SSC":[22],"operation.":[23],"Fabricated":[24],"in":[25,99],"14nm":[26],"FinFET":[27],"CMOS,":[28],"switched-cap":[31,93],"loop":[32,77,94],"filter":[33],"is":[34],"employed":[35],"to":[36,86,139],"enable":[37],"high":[38],"-3dB":[39],"bandwidth":[41],"(>40%":[42],"of":[43,92],"f":[44],"<sub":[45],"xmlns:mml=\"http://www.w3.org/1998/Math/MathML\"":[46],"xmlns:xlink=\"http://www.w3.org/1999/xlink\">REF</sub>":[47],"=":[48],"19.2":[49],"MHz),":[50],"the":[52,65,131],"proposed":[53],"reference":[54,119],"current":[55,60],"generator":[56],"(IrefGen)":[57],"provides":[58,84],"accurate":[59],"with":[61],"<;4%":[62],"tolerance":[63],"without":[64,137],"need":[66],"for":[67],"external":[68],"components":[69],"or":[70],"on-chip":[71],"precision":[72],"resistors.":[73],"IrefGen":[74],"decouples":[75],"dynamics":[78],"from":[79,124],"feedback":[80],"divide":[81],"ratio":[82],"immunity":[85],"systematic":[87],"capacitor":[88],"variation.":[89],"Power":[90],"gating":[91],"filter's":[95],"bias":[96],"circuits":[97],"results":[98],"more":[100],"than":[101],"10%":[102],"total":[104],"power":[105],"savings.":[106],"The":[107,127],"achieves":[109],"1.6-ps":[110],"integrated":[111],"RMS":[112],"jitter":[113,135],"at":[114],"4":[115],"GHz":[116],"using":[117],"100-MHz":[118],"while":[120],"consuming":[121],"2.6":[122],"mW":[123],"0.95":[125],"V.":[126],"performance":[129],"satisfies":[130],"stringent":[132],"PCIe":[133],"Gen2/3":[134],"specifications":[136],"resorting":[138],"inductors.":[140]},"counts_by_year":[{"year":2025,"cited_by_count":3},{"year":2024,"cited_by_count":3},{"year":2023,"cited_by_count":1},{"year":2022,"cited_by_count":1},{"year":2021,"cited_by_count":2},{"year":2020,"cited_by_count":2},{"year":2019,"cited_by_count":2}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}
