{"id":"https://openalex.org/W2789805214","doi":"https://doi.org/10.1109/tcsi.2017.2778113","title":"A Resistive RAM-Based FPGA Architecture Equipped With Efficient Programming Circuitry","display_name":"A Resistive RAM-Based FPGA Architecture Equipped With Efficient Programming Circuitry","publication_year":2018,"publication_date":"2018-01-17","ids":{"openalex":"https://openalex.org/W2789805214","doi":"https://doi.org/10.1109/tcsi.2017.2778113","mag":"2789805214"},"language":"en","primary_location":{"id":"doi:10.1109/tcsi.2017.2778113","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tcsi.2017.2778113","pdf_url":null,"source":{"id":"https://openalex.org/S116977442","display_name":"IEEE Transactions on Circuits and Systems I Regular Papers","issn_l":"1549-8328","issn":["1549-8328","1558-0806"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Circuits and Systems I: Regular Papers","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5060490428","display_name":"Behnam Khaleghi","orcid":"https://orcid.org/0000-0002-3655-0501"},"institutions":[{"id":"https://openalex.org/I133529467","display_name":"Sharif University of Technology","ror":"https://ror.org/024c2fq17","country_code":"IR","type":"education","lineage":["https://openalex.org/I133529467"]}],"countries":["IR"],"is_corresponding":false,"raw_author_name":"Behnam Khaleghi","raw_affiliation_strings":["Sharif University of Technology, Tehran, Iran"],"raw_orcid":"https://orcid.org/0000-0002-3655-0501","affiliations":[{"raw_affiliation_string":"Sharif University of Technology, Tehran, Iran","institution_ids":["https://openalex.org/I133529467"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5088069234","display_name":"Hossein Asadi","orcid":"https://orcid.org/0000-0002-0264-3865"},"institutions":[{"id":"https://openalex.org/I133529467","display_name":"Sharif University of Technology","ror":"https://ror.org/024c2fq17","country_code":"IR","type":"education","lineage":["https://openalex.org/I133529467"]}],"countries":["IR"],"is_corresponding":false,"raw_author_name":"Hossein Asadi","raw_affiliation_strings":["Sharif University of Technology, Tehran, Iran"],"raw_orcid":"https://orcid.org/0000-0002-0264-3865","affiliations":[{"raw_affiliation_string":"Sharif University of Technology, Tehran, Iran","institution_ids":["https://openalex.org/I133529467"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":[],"corresponding_institution_ids":["https://openalex.org/I133529467"],"apc_list":null,"apc_paid":null,"fwci":0.7575,"has_fulltext":false,"cited_by_count":16,"citation_normalized_percentile":{"value":0.72125206,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":97},"biblio":{"volume":"65","issue":"7","first_page":"2196","last_page":"2209"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10502","display_name":"Advanced Memory and Neural Computing","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10502","display_name":"Advanced Memory and Neural Computing","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10472","display_name":"Semiconductor materials and devices","score":0.9994999766349792,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T12808","display_name":"Ferroelectric and Negative Capacitance Devices","score":0.9993000030517578,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/static-random-access-memory","display_name":"Static random-access memory","score":0.8280285596847534},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.8050600290298462},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7274966239929199},{"id":"https://openalex.org/keywords/lookup-table","display_name":"Lookup table","score":0.7148762941360474},{"id":"https://openalex.org/keywords/resistive-random-access-memory","display_name":"Resistive random-access memory","score":0.7097998261451721},{"id":"https://openalex.org/keywords/overhead","display_name":"Overhead (engineering)","score":0.6415618658065796},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.6031607389450073},{"id":"https://openalex.org/keywords/reliability","display_name":"Reliability (semiconductor)","score":0.4968872368335724},{"id":"https://openalex.org/keywords/bitstream","display_name":"Bitstream","score":0.4802587330341339},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.4702659547328949},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.3574336767196655},{"id":"https://openalex.org/keywords/power","display_name":"Power (physics)","score":0.33700278401374817},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.14178311824798584},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.14060300588607788},{"id":"https://openalex.org/keywords/decoding-methods","display_name":"Decoding methods","score":0.1150243878364563},{"id":"https://openalex.org/keywords/voltage","display_name":"Voltage","score":0.07385045289993286},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.07254946231842041}],"concepts":[{"id":"https://openalex.org/C68043766","wikidata":"https://www.wikidata.org/wiki/Q267416","display_name":"Static random-access memory","level":2,"score":0.8280285596847534},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.8050600290298462},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7274966239929199},{"id":"https://openalex.org/C134835016","wikidata":"https://www.wikidata.org/wiki/Q690265","display_name":"Lookup table","level":2,"score":0.7148762941360474},{"id":"https://openalex.org/C182019814","wikidata":"https://www.wikidata.org/wiki/Q1143830","display_name":"Resistive random-access memory","level":3,"score":0.7097998261451721},{"id":"https://openalex.org/C2779960059","wikidata":"https://www.wikidata.org/wiki/Q7113681","display_name":"Overhead (engineering)","level":2,"score":0.6415618658065796},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.6031607389450073},{"id":"https://openalex.org/C43214815","wikidata":"https://www.wikidata.org/wiki/Q7310987","display_name":"Reliability (semiconductor)","level":3,"score":0.4968872368335724},{"id":"https://openalex.org/C136695289","wikidata":"https://www.wikidata.org/wiki/Q415568","display_name":"Bitstream","level":3,"score":0.4802587330341339},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.4702659547328949},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.3574336767196655},{"id":"https://openalex.org/C163258240","wikidata":"https://www.wikidata.org/wiki/Q25342","display_name":"Power (physics)","level":2,"score":0.33700278401374817},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.14178311824798584},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.14060300588607788},{"id":"https://openalex.org/C57273362","wikidata":"https://www.wikidata.org/wiki/Q576722","display_name":"Decoding methods","level":2,"score":0.1150243878364563},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.07385045289993286},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.07254946231842041},{"id":"https://openalex.org/C121332964","wikidata":"https://www.wikidata.org/wiki/Q413","display_name":"Physics","level":0,"score":0.0},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.0},{"id":"https://openalex.org/C62520636","wikidata":"https://www.wikidata.org/wiki/Q944","display_name":"Quantum mechanics","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/tcsi.2017.2778113","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tcsi.2017.2778113","pdf_url":null,"source":{"id":"https://openalex.org/S116977442","display_name":"IEEE Transactions on Circuits and Systems I Regular Papers","issn_l":"1549-8328","issn":["1549-8328","1558-0806"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Circuits and Systems I: Regular Papers","raw_type":"journal-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":49,"referenced_works":["https://openalex.org/W1522950391","https://openalex.org/W1871725592","https://openalex.org/W1967542252","https://openalex.org/W1977765713","https://openalex.org/W1977773606","https://openalex.org/W1977850862","https://openalex.org/W2000036939","https://openalex.org/W2002612140","https://openalex.org/W2004823737","https://openalex.org/W2005602803","https://openalex.org/W2010160963","https://openalex.org/W2045617353","https://openalex.org/W2065849008","https://openalex.org/W2076613578","https://openalex.org/W2078177817","https://openalex.org/W2085743209","https://openalex.org/W2086637600","https://openalex.org/W2086709250","https://openalex.org/W2091434737","https://openalex.org/W2095258817","https://openalex.org/W2110321764","https://openalex.org/W2118995854","https://openalex.org/W2120452158","https://openalex.org/W2120544688","https://openalex.org/W2126240789","https://openalex.org/W2126903098","https://openalex.org/W2128473621","https://openalex.org/W2136983830","https://openalex.org/W2139911369","https://openalex.org/W2146437820","https://openalex.org/W2154689013","https://openalex.org/W2155925776","https://openalex.org/W2171888576","https://openalex.org/W2242065935","https://openalex.org/W2263042501","https://openalex.org/W2344619236","https://openalex.org/W2411782263","https://openalex.org/W2557101570","https://openalex.org/W2560332530","https://openalex.org/W2566594221","https://openalex.org/W3143894789","https://openalex.org/W4230995605","https://openalex.org/W4235333556","https://openalex.org/W4236970054","https://openalex.org/W6631403632","https://openalex.org/W6647116859","https://openalex.org/W6668622331","https://openalex.org/W6683119315","https://openalex.org/W6683192216"],"related_works":["https://openalex.org/W3040878082","https://openalex.org/W1491404489","https://openalex.org/W2963819424","https://openalex.org/W3003628452","https://openalex.org/W2390134136","https://openalex.org/W2908650077","https://openalex.org/W2347731430","https://openalex.org/W2384487777","https://openalex.org/W2172988812","https://openalex.org/W3009852985"],"abstract_inverted_index":{"Despite":[0],"the":[1,8,28,36,41,109,113,118,130,136,155,159,164,170,189,193,203],"considerable":[2],"effort":[3],"has":[4],"been":[5],"put":[6],"on":[7],"application":[9],"of":[10,43,124,135,144,158,169],"Non-Volatile":[11],"Memories":[12],"(NVMs)":[13],"in":[14,79,142],"Field-Programmable":[15],"Gate":[16],"Arrays":[17],"FPGAs,":[18],"previously":[19],"suggested":[20],"designs":[21,74,84],"are":[22,174],"not":[23],"mature":[24],"enough":[25],"to":[26,35,97,107,122,140],"substitute":[27],"state":[29],"of-the-art":[30],"SRAM-based":[31,125,181],"counterparts":[32],"mainly":[33],"due":[34],"inefficient":[37],"building":[38],"blocks":[39,161],"and/or":[40],"overhead":[42,96],"programming":[44,76,137],"structure":[45,138],"which":[46,116],"can":[47],"impair":[48],"their":[49],"potential":[50],"benefits.":[51],"In":[52,100],"this":[53],"paper,":[54],"we":[55,102,128],"present":[56,103],"a":[57,185],"Resistive":[58],"Random":[59],"Access":[60],"Memory":[61],"RRAM-based":[62,187],"FPGA":[63,172],"architecture":[64,173,191],"employing":[65],"efficient":[66,90,105],"Switch":[67],"Box":[68],"(SB)":[69],"and":[70,82,88,133,150,167,176,195,199],"Look-Up":[71],"Table":[72],"(LUT)":[73],"with":[75,154,184],"circuitry":[77],"integrated":[78],"both":[80],"SB":[81],"LUT":[83],"that":[85,123,163],"creates":[86],"area":[87,166,194],"power":[89,196],"programmable":[91],"components":[92],"while":[93,201],"precluding":[94],"performance":[95],"these":[98],"blocks.":[99],"addition,":[101],"an":[104],"scheme":[106],"load":[108],"configuration":[110,119],"bitstream":[111],"into":[112],"memory":[114],"elements,":[115],"makes":[117],"time":[120],"comparable":[121],"FPGAs.":[126,182],"Besides,":[127],"investigate":[129],"correct":[131],"functionality":[132],"reliability":[134],"subject":[139],"fluctuations":[141],"attributes":[143],"RRAM":[145],"cells.":[146],"Using":[147],"Versatile":[148],"Place":[149],"Route":[151],"(VTR)":[152],"tool":[153],"obtained":[156],"characteristics":[157],"proposed":[160,171,190],"demonstrate":[162],"average":[165],"delay":[168,204],"59.4%":[175],"20.1%":[177],"less":[178],"than":[179],"conventional":[180],"Compared":[183],"recent":[186],"architecture,":[188],"improves":[192],"by":[197],"49.7%":[198],"33.8%":[200],"keeps":[202],"intact.":[205]},"counts_by_year":[{"year":2025,"cited_by_count":3},{"year":2024,"cited_by_count":2},{"year":2023,"cited_by_count":4},{"year":2022,"cited_by_count":1},{"year":2021,"cited_by_count":3},{"year":2020,"cited_by_count":3}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}
