{"id":"https://openalex.org/W2767231687","doi":"https://doi.org/10.1109/tcsi.2017.2766527","title":"Analysis of Common-Mode Interference and Jitter of Clock Receiver Circuits With Improved Topology","display_name":"Analysis of Common-Mode Interference and Jitter of Clock Receiver Circuits With Improved Topology","publication_year":2017,"publication_date":"2017-11-08","ids":{"openalex":"https://openalex.org/W2767231687","doi":"https://doi.org/10.1109/tcsi.2017.2766527","mag":"2767231687"},"language":"en","primary_location":{"id":"doi:10.1109/tcsi.2017.2766527","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tcsi.2017.2766527","pdf_url":null,"source":{"id":"https://openalex.org/S116977442","display_name":"IEEE Transactions on Circuits and Systems I Regular Papers","issn_l":"1549-8328","issn":["1549-8328","1558-0806"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Circuits and Systems I: Regular Papers","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5063285225","display_name":"Xiaofeng Yang","orcid":"https://orcid.org/0000-0003-1400-7994"},"institutions":[{"id":"https://openalex.org/I204512498","display_name":"University of Macau","ror":"https://ror.org/01r4q9n85","country_code":"MO","type":"education","lineage":["https://openalex.org/I204512498"]}],"countries":["MO"],"is_corresponding":true,"raw_author_name":"Xiaofeng Yang","raw_affiliation_strings":["State Key Laboratory of Analog and Mixed-Signal VLSI, University of Macau, Macau, China"],"affiliations":[{"raw_affiliation_string":"State Key Laboratory of Analog and Mixed-Signal VLSI, University of Macau, Macau, China","institution_ids":["https://openalex.org/I204512498"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5071933088","display_name":"Yan Zhu","orcid":null},"institutions":[{"id":"https://openalex.org/I204512498","display_name":"University of Macau","ror":"https://ror.org/01r4q9n85","country_code":"MO","type":"education","lineage":["https://openalex.org/I204512498"]}],"countries":["MO"],"is_corresponding":false,"raw_author_name":"Yan Zhu","raw_affiliation_strings":["State Key Laboratory of Analog and Mixed-Signal VLSI, University of Macau, Macau, China"],"affiliations":[{"raw_affiliation_string":"State Key Laboratory of Analog and Mixed-Signal VLSI, University of Macau, Macau, China","institution_ids":["https://openalex.org/I204512498"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5035229843","display_name":"Chi\u2010Hang Chan","orcid":"https://orcid.org/0000-0002-7635-1101"},"institutions":[{"id":"https://openalex.org/I204512498","display_name":"University of Macau","ror":"https://ror.org/01r4q9n85","country_code":"MO","type":"education","lineage":["https://openalex.org/I204512498"]}],"countries":["MO"],"is_corresponding":false,"raw_author_name":"Chi-Hang Chan","raw_affiliation_strings":["State Key Laboratory of Analog and Mixed-Signal VLSI, University of Macau, Macau, China"],"affiliations":[{"raw_affiliation_string":"State Key Laboratory of Analog and Mixed-Signal VLSI, University of Macau, Macau, China","institution_ids":["https://openalex.org/I204512498"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5061042931","display_name":"U Seng\u2010Pan","orcid":null},"institutions":[{"id":"https://openalex.org/I204512498","display_name":"University of Macau","ror":"https://ror.org/01r4q9n85","country_code":"MO","type":"education","lineage":["https://openalex.org/I204512498"]}],"countries":["MO"],"is_corresponding":false,"raw_author_name":"Seng-Pan U","raw_affiliation_strings":["Department of Electrical and Computer Engineering, Faculty of Science and Technology, University of Macau, Macao, China","Synopsys Macau Ltd., Macau, China"],"affiliations":[{"raw_affiliation_string":"Department of Electrical and Computer Engineering, Faculty of Science and Technology, University of Macau, Macao, China","institution_ids":["https://openalex.org/I204512498"]},{"raw_affiliation_string":"Synopsys Macau Ltd., Macau, China","institution_ids":[]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5106943352","display_name":"Rui P. Martins","orcid":"https://orcid.org/0000-0003-2821-648X"},"institutions":[{"id":"https://openalex.org/I141596103","display_name":"University of Lisbon","ror":"https://ror.org/01c27hj86","country_code":"PT","type":"education","lineage":["https://openalex.org/I141596103"]},{"id":"https://openalex.org/I203847022","display_name":"Instituto Polit\u00e9cnico de Lisboa","ror":"https://ror.org/04ea70f07","country_code":"PT","type":"education","lineage":["https://openalex.org/I203847022"]},{"id":"https://openalex.org/I204512498","display_name":"University of Macau","ror":"https://ror.org/01r4q9n85","country_code":"MO","type":"education","lineage":["https://openalex.org/I204512498"]}],"countries":["MO","PT"],"is_corresponding":false,"raw_author_name":"Rui P. Martins","raw_affiliation_strings":["Department of Electrical and Computer Engineering, Faculty of Science and Technology, University of Macau, Macao, China","Instituto Superior T\u00e9cnico, Universidade de Lisboa, Lisbon, Portugal"],"affiliations":[{"raw_affiliation_string":"Department of Electrical and Computer Engineering, Faculty of Science and Technology, University of Macau, Macao, China","institution_ids":["https://openalex.org/I204512498"]},{"raw_affiliation_string":"Instituto Superior T\u00e9cnico, Universidade de Lisboa, Lisbon, Portugal","institution_ids":["https://openalex.org/I203847022","https://openalex.org/I141596103"]}]}],"institutions":[],"countries_distinct_count":2,"institutions_distinct_count":5,"corresponding_author_ids":["https://openalex.org/A5063285225"],"corresponding_institution_ids":["https://openalex.org/I204512498"],"apc_list":null,"apc_paid":null,"fwci":0.654,"has_fulltext":false,"cited_by_count":10,"citation_normalized_percentile":{"value":0.68587291,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":97},"biblio":{"volume":"65","issue":"6","first_page":"1819","last_page":"1829"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10323","display_name":"Analog and Mixed-Signal Circuit Design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2204","display_name":"Biomedical Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10323","display_name":"Analog and Mixed-Signal Circuit Design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2204","display_name":"Biomedical Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11417","display_name":"Advancements in PLL and VCO Technologies","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10187","display_name":"Radio Frequency Integrated Circuit Design","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/jitter","display_name":"Jitter","score":0.9182335138320923},{"id":"https://openalex.org/keywords/topology","display_name":"Topology (electrical circuits)","score":0.6149148941040039},{"id":"https://openalex.org/keywords/cmos","display_name":"CMOS","score":0.5759749412536621},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.5469085574150085},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.5235723853111267},{"id":"https://openalex.org/keywords/inverter","display_name":"Inverter","score":0.4902952015399933},{"id":"https://openalex.org/keywords/amplifier","display_name":"Amplifier","score":0.47045648097991943},{"id":"https://openalex.org/keywords/common-mode-signal","display_name":"Common-mode signal","score":0.4133037030696869},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.26338934898376465},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.20354607701301575},{"id":"https://openalex.org/keywords/voltage","display_name":"Voltage","score":0.15917477011680603}],"concepts":[{"id":"https://openalex.org/C134652429","wikidata":"https://www.wikidata.org/wiki/Q1052698","display_name":"Jitter","level":2,"score":0.9182335138320923},{"id":"https://openalex.org/C184720557","wikidata":"https://www.wikidata.org/wiki/Q7825049","display_name":"Topology (electrical circuits)","level":2,"score":0.6149148941040039},{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.5759749412536621},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.5469085574150085},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.5235723853111267},{"id":"https://openalex.org/C11190779","wikidata":"https://www.wikidata.org/wiki/Q664575","display_name":"Inverter","level":3,"score":0.4902952015399933},{"id":"https://openalex.org/C194257627","wikidata":"https://www.wikidata.org/wiki/Q211554","display_name":"Amplifier","level":3,"score":0.47045648097991943},{"id":"https://openalex.org/C189714311","wikidata":"https://www.wikidata.org/wiki/Q1530371","display_name":"Common-mode signal","level":4,"score":0.4133037030696869},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.26338934898376465},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.20354607701301575},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.15917477011680603},{"id":"https://openalex.org/C84462506","wikidata":"https://www.wikidata.org/wiki/Q173142","display_name":"Digital signal processing","level":2,"score":0.0},{"id":"https://openalex.org/C13412647","wikidata":"https://www.wikidata.org/wiki/Q174948","display_name":"Analog signal","level":3,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/tcsi.2017.2766527","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tcsi.2017.2766527","pdf_url":null,"source":{"id":"https://openalex.org/S116977442","display_name":"IEEE Transactions on Circuits and Systems I Regular Papers","issn_l":"1549-8328","issn":["1549-8328","1558-0806"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Circuits and Systems I: Regular Papers","raw_type":"journal-article"}],"best_oa_location":null,"sustainable_development_goals":[{"display_name":"Affordable and clean energy","score":0.7200000286102295,"id":"https://metadata.un.org/sdg/7"}],"awards":[{"id":"https://openalex.org/G344233630","display_name":null,"funder_award_id":"61604180","funder_id":"https://openalex.org/F4320321001","funder_display_name":"National Natural Science Foundation of China"},{"id":"https://openalex.org/G3735653146","display_name":null,"funder_award_id":"117/2016/A3","funder_id":"https://openalex.org/F4320323893","funder_display_name":"Fundo para o Desenvolvimento das Ci\u00eancias e da Tecnologia"}],"funders":[{"id":"https://openalex.org/F4320321001","display_name":"National Natural Science Foundation of China","ror":"https://ror.org/01h0zpd94"},{"id":"https://openalex.org/F4320323893","display_name":"Fundo para o Desenvolvimento das Ci\u00eancias e da Tecnologia","ror":"https://ror.org/05vna4324"}],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":19,"referenced_works":["https://openalex.org/W1499391319","https://openalex.org/W1590762561","https://openalex.org/W1978059276","https://openalex.org/W1990536608","https://openalex.org/W1994307413","https://openalex.org/W2021870901","https://openalex.org/W2028470944","https://openalex.org/W2092437146","https://openalex.org/W2104340505","https://openalex.org/W2108324407","https://openalex.org/W2115712965","https://openalex.org/W2117662511","https://openalex.org/W2129393153","https://openalex.org/W2135281359","https://openalex.org/W2148601149","https://openalex.org/W2159758079","https://openalex.org/W2546613821","https://openalex.org/W4252762980","https://openalex.org/W6647975615"],"related_works":["https://openalex.org/W2121182846","https://openalex.org/W2315668284","https://openalex.org/W2155789024","https://openalex.org/W2109491806","https://openalex.org/W3213608175","https://openalex.org/W2058044441","https://openalex.org/W98453623","https://openalex.org/W2340624421","https://openalex.org/W4389297064","https://openalex.org/W2118090249"],"abstract_inverted_index":{"This":[0],"paper":[1],"presents":[2],"an":[3,44,97],"analysis":[4,69],"based":[5,59],"on":[6,60],"the":[7,16,20,25,31,35,49,61,68,71,74,103,108,121,151,162],"impulse":[8],"sensitivity":[9],"function":[10],"to":[11],"precisely":[12],"characterize":[13],"and":[14,70,82,102,113,147],"estimate":[15],"jitter":[17,37,133,149],"caused":[18],"by":[19,48],"common-mode":[21,27],"interference":[22],"(CMI).":[23],"Unlike":[24],"conventional":[26],"rejection":[28,146],"ratio":[29],"concept,":[30],"proposed":[32,75,104,125,152],"method":[33],"considers":[34],"CMI":[36,145],"in":[38,43,80,89],"a":[39,54,99,117,128,135,143,155],"transient":[40],"rather":[41],"than":[42],"ac":[45],"perspective.":[46],"Inspired":[47],"analytical":[50],"results,":[51],"we":[52],"propose":[53],"clock":[55],"receiver":[56],"circuit":[57],"(CRC)":[58],"self-bias":[62],"amplifier":[63,101],"topology.":[64],"The":[65,124],"accuracy":[66],"of":[67,73],"efficiency":[72],"CRC":[76,126,153],"are":[77],"verified":[78],"both":[79],"simulations":[81],"measurements.":[83],"A":[84],"1-GS/s":[85],"ADC":[86],"was":[87],"fabricated":[88],"65-nm":[90],"CMOS":[91],"containing":[92],"simultaneously":[93],"three":[94],"CRCs,":[95],"including":[96],"inverter-chain,":[98],"differential":[100],"structure,":[105],"serving":[106],"as":[107],"sampling":[109],"clock.":[110],"Both":[111],"simulation":[112],"measurement":[114],"results":[115],"show":[116],"good":[118],"agreement":[119],"with":[120,134,161],"presented":[122],"analysis.":[123],"achieves":[127],"30-fs":[129],"<sub":[130],"xmlns:mml=\"http://www.w3.org/1998/Math/MathML\"":[131],"xmlns:xlink=\"http://www.w3.org/1999/xlink\">ms</sub>":[132],"620-\u03bcW":[136],"power":[137,157],"at":[138],"1.2":[139],"V":[140],"supply.":[141],"With":[142],"similar":[144],"random":[148],"performance,":[150],"exhibits":[154],"20-fold":[156],"reduction":[158],"when":[159],"compared":[160],"state-of-art":[163],"designs.":[164]},"counts_by_year":[{"year":2025,"cited_by_count":1},{"year":2024,"cited_by_count":1},{"year":2023,"cited_by_count":1},{"year":2021,"cited_by_count":2},{"year":2020,"cited_by_count":1},{"year":2019,"cited_by_count":1},{"year":2018,"cited_by_count":3}],"updated_date":"2026-03-27T05:58:40.876381","created_date":"2025-10-10T00:00:00"}