{"id":"https://openalex.org/W2760338732","doi":"https://doi.org/10.1109/tcsi.2017.2750702","title":"BIRA With Optimal Repair Rate Using Fault-Free Memory Region for Area Reduction","display_name":"BIRA With Optimal Repair Rate Using Fault-Free Memory Region for Area Reduction","publication_year":2017,"publication_date":"2017-09-25","ids":{"openalex":"https://openalex.org/W2760338732","doi":"https://doi.org/10.1109/tcsi.2017.2750702","mag":"2760338732"},"language":"en","primary_location":{"id":"doi:10.1109/tcsi.2017.2750702","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tcsi.2017.2750702","pdf_url":null,"source":{"id":"https://openalex.org/S116977442","display_name":"IEEE Transactions on Circuits and Systems I Regular Papers","issn_l":"1549-8328","issn":["1549-8328","1558-0806"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Circuits and Systems I: Regular Papers","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5055315954","display_name":"Chang-Hyun Oh","orcid":"https://orcid.org/0000-0001-6956-0223"},"institutions":[{"id":"https://openalex.org/I848706","display_name":"Sungkyunkwan University","ror":"https://ror.org/04q78tk20","country_code":"KR","type":"education","lineage":["https://openalex.org/I848706"]}],"countries":["KR"],"is_corresponding":true,"raw_author_name":"Chang-Hyun Oh","raw_affiliation_strings":["Department of Semiconductor and Display Engineering, Sungkyunkwan University, Suwon, South Korea"],"raw_orcid":"https://orcid.org/0000-0001-6956-0223","affiliations":[{"raw_affiliation_string":"Department of Semiconductor and Display Engineering, Sungkyunkwan University, Suwon, South Korea","institution_ids":["https://openalex.org/I848706"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5026846247","display_name":"Sae-Eun Kim","orcid":null},"institutions":[{"id":"https://openalex.org/I848706","display_name":"Sungkyunkwan University","ror":"https://ror.org/04q78tk20","country_code":"KR","type":"education","lineage":["https://openalex.org/I848706"]}],"countries":["KR"],"is_corresponding":false,"raw_author_name":"Sae-Eun Kim","raw_affiliation_strings":["Department of Semiconductor and Display Engineering, Sungkyunkwan University, Suwon, South Korea"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Semiconductor and Display Engineering, Sungkyunkwan University, Suwon, South Korea","institution_ids":["https://openalex.org/I848706"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5026627679","display_name":"Joon-Sung Yang","orcid":"https://orcid.org/0000-0002-1502-5353"},"institutions":[{"id":"https://openalex.org/I848706","display_name":"Sungkyunkwan University","ror":"https://ror.org/04q78tk20","country_code":"KR","type":"education","lineage":["https://openalex.org/I848706"]}],"countries":["KR"],"is_corresponding":false,"raw_author_name":"Joon-Sung Yang","raw_affiliation_strings":["Department of Semiconductor and Display Engineering, Sungkyunkwan University, Suwon, South Korea"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Semiconductor and Display Engineering, Sungkyunkwan University, Suwon, South Korea","institution_ids":["https://openalex.org/I848706"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":3,"corresponding_author_ids":["https://openalex.org/A5055315954"],"corresponding_institution_ids":["https://openalex.org/I848706"],"apc_list":null,"apc_paid":null,"fwci":0.7306,"has_fulltext":false,"cited_by_count":11,"citation_normalized_percentile":{"value":0.73870204,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":97},"biblio":{"volume":"64","issue":"12","first_page":"3160","last_page":"3171"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10502","display_name":"Advanced Memory and Neural Computing","score":0.9990000128746033,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10502","display_name":"Advanced Memory and Neural Computing","score":0.9990000128746033,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T12808","display_name":"Ferroelectric and Negative Capacitance Devices","score":0.9987000226974487,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T12326","display_name":"Network Packet Processing and Optimization","score":0.998199999332428,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7478352785110474},{"id":"https://openalex.org/keywords/redundancy","display_name":"Redundancy (engineering)","score":0.6030256152153015},{"id":"https://openalex.org/keywords/spare-part","display_name":"Spare part","score":0.4922737181186676},{"id":"https://openalex.org/keywords/process","display_name":"Process (computing)","score":0.4732658863067627},{"id":"https://openalex.org/keywords/overhead","display_name":"Overhead (engineering)","score":0.4597032964229584},{"id":"https://openalex.org/keywords/memory-management","display_name":"Memory management","score":0.4261781573295593},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.42400062084198},{"id":"https://openalex.org/keywords/memory-cell","display_name":"Memory cell","score":0.4127996563911438},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.32516908645629883},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.28299158811569214},{"id":"https://openalex.org/keywords/semiconductor-memory","display_name":"Semiconductor memory","score":0.2700047791004181},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.15182971954345703},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.1472455859184265}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7478352785110474},{"id":"https://openalex.org/C152124472","wikidata":"https://www.wikidata.org/wiki/Q1204361","display_name":"Redundancy (engineering)","level":2,"score":0.6030256152153015},{"id":"https://openalex.org/C194648553","wikidata":"https://www.wikidata.org/wiki/Q1364774","display_name":"Spare part","level":2,"score":0.4922737181186676},{"id":"https://openalex.org/C98045186","wikidata":"https://www.wikidata.org/wiki/Q205663","display_name":"Process (computing)","level":2,"score":0.4732658863067627},{"id":"https://openalex.org/C2779960059","wikidata":"https://www.wikidata.org/wiki/Q7113681","display_name":"Overhead (engineering)","level":2,"score":0.4597032964229584},{"id":"https://openalex.org/C176649486","wikidata":"https://www.wikidata.org/wiki/Q2308807","display_name":"Memory management","level":3,"score":0.4261781573295593},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.42400062084198},{"id":"https://openalex.org/C2776638159","wikidata":"https://www.wikidata.org/wiki/Q18343761","display_name":"Memory cell","level":4,"score":0.4127996563911438},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.32516908645629883},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.28299158811569214},{"id":"https://openalex.org/C98986596","wikidata":"https://www.wikidata.org/wiki/Q1143031","display_name":"Semiconductor memory","level":2,"score":0.2700047791004181},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.15182971954345703},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.1472455859184265},{"id":"https://openalex.org/C172385210","wikidata":"https://www.wikidata.org/wiki/Q5339","display_name":"Transistor","level":3,"score":0.0},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.0},{"id":"https://openalex.org/C78519656","wikidata":"https://www.wikidata.org/wiki/Q101333","display_name":"Mechanical engineering","level":1,"score":0.0},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/tcsi.2017.2750702","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tcsi.2017.2750702","pdf_url":null,"source":{"id":"https://openalex.org/S116977442","display_name":"IEEE Transactions on Circuits and Systems I Regular Papers","issn_l":"1549-8328","issn":["1549-8328","1558-0806"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Circuits and Systems I: Regular Papers","raw_type":"journal-article"}],"best_oa_location":null,"sustainable_development_goals":[{"score":0.4000000059604645,"id":"https://metadata.un.org/sdg/9","display_name":"Industry, innovation and infrastructure"}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":32,"referenced_works":["https://openalex.org/W1966747106","https://openalex.org/W1982231668","https://openalex.org/W1986005813","https://openalex.org/W1991047274","https://openalex.org/W1991181433","https://openalex.org/W2024567927","https://openalex.org/W2034429812","https://openalex.org/W2050361299","https://openalex.org/W2055411146","https://openalex.org/W2059164349","https://openalex.org/W2062279934","https://openalex.org/W2068746002","https://openalex.org/W2076325543","https://openalex.org/W2098987953","https://openalex.org/W2101739742","https://openalex.org/W2106867391","https://openalex.org/W2116273964","https://openalex.org/W2133550436","https://openalex.org/W2136323667","https://openalex.org/W2136759973","https://openalex.org/W2152425525","https://openalex.org/W2155640457","https://openalex.org/W2342664696","https://openalex.org/W2343549777","https://openalex.org/W2408347471","https://openalex.org/W2522720996","https://openalex.org/W2531632794","https://openalex.org/W2578917161","https://openalex.org/W3203143386","https://openalex.org/W6664188284","https://openalex.org/W6669482785","https://openalex.org/W6704257277"],"related_works":["https://openalex.org/W2376859990","https://openalex.org/W2912704652","https://openalex.org/W2381161177","https://openalex.org/W2319226115","https://openalex.org/W830772239","https://openalex.org/W2970750595","https://openalex.org/W2366601680","https://openalex.org/W2392193501","https://openalex.org/W2738649048","https://openalex.org/W2344117897"],"abstract_inverted_index":{"As":[0,13],"manufacturing":[1],"process":[2],"technology":[3],"scales":[4],"down,":[5],"memory":[6,17,31,42,62,72,150,187,193,203],"capacity":[7],"and":[8,44,67,83,142,162,188],"density":[9],"continue":[10],"to":[11,90,98,112,118,195,224],"grow.":[12],"the":[14,24,30,60,76,85,100,119,124,133,160,164,168,197,208,212,226],"number":[15],"of":[16,26,136],"cells":[18,49],"per":[19],"area":[20,138,213],"increases,":[21],"so":[22],"does":[23,183],"possibility":[25],"having":[27],"defects":[28],"in":[29,207],"cells.":[32,56,92],"Therefore,":[33],"built-in":[34],"redundancy":[35],"analysis":[36,227],"(BIRA)":[37],"is":[38,65,68,166,204,215],"widely":[39],"used":[40],"for":[41,140,159],"test":[43],"repair.":[45],"BIRA":[46,80,106,171,180,210],"repairs":[47],"faulty":[48,61,77,101,114,198],"by":[50,87],"replacing":[51],"them":[52],"with":[53],"healthy":[54],"spare":[55],"To":[57],"perform":[58,84],"BIRA,":[59,141],"cell":[63,78,102,115,199],"information":[64],"required":[66,206],"collected":[69],"via":[70],"a":[71,143,178,191],"test.":[73],"By":[74],"using":[75],"information,":[79],"can":[81,127],"analyze":[82],"repair":[86,125,157,220,233],"assigning":[88],"spares":[89],"defective":[91],"However,":[93,130],"it":[94],"requires":[95],"extra":[96,186,202],"hardware":[97],"store":[99,113,196],"information.":[103,116,200],"Most":[104],"conventional":[105,169],"approaches":[107],"utilize":[108],"content-addressable":[109],"memories":[110],"(CAMs)":[111],"Owing":[117],"CAMs'":[120],"fast":[121],"access":[122],"speed,":[123],"time":[126],"be":[128,146,173],"reduced.":[129],"CAMs":[131],"are":[132],"critical":[134],"source":[135],"an":[137],"overhead":[139,214],"CAM":[144,165],"could":[145],"shared":[147,153],"across":[148],"multiple":[149],"banks.":[151],"The":[152,217],"structure":[154],"limits":[155],"simultaneous":[156],"operations":[158],"banks,":[161],"when":[163],"faulty,":[167],"CAM-based":[170],"cannot":[172],"performed.":[174],"This":[175],"paper":[176],"proposes":[177],"new":[179],"method,":[181,211],"which":[182],"not":[184,205],"require":[185],"instead":[189],"utilizes":[190],"fault-free":[192],"region":[194],"Because":[201],"proposed":[209,218],"decreased.":[216],"hierarchical":[219],"algorithm":[221],"thus":[222],"helps":[223],"reduce":[225],"time,":[228],"while":[229],"achieving":[230],"optimal":[231],"normalized":[232],"rate.":[234]},"counts_by_year":[{"year":2024,"cited_by_count":2},{"year":2023,"cited_by_count":3},{"year":2021,"cited_by_count":1},{"year":2020,"cited_by_count":2},{"year":2019,"cited_by_count":1},{"year":2018,"cited_by_count":2}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}
