{"id":"https://openalex.org/W2598433099","doi":"https://doi.org/10.1109/tcsi.2017.2679748","title":"A 12b 180MS/s 0.068mm<sup>2</sup> With Full-Calibration-Integrated Pipelined-SAR ADC","display_name":"A 12b 180MS/s 0.068mm<sup>2</sup> With Full-Calibration-Integrated Pipelined-SAR ADC","publication_year":2017,"publication_date":"2017-03-25","ids":{"openalex":"https://openalex.org/W2598433099","doi":"https://doi.org/10.1109/tcsi.2017.2679748","mag":"2598433099"},"language":"en","primary_location":{"id":"doi:10.1109/tcsi.2017.2679748","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tcsi.2017.2679748","pdf_url":null,"source":{"id":"https://openalex.org/S116977442","display_name":"IEEE Transactions on Circuits and Systems I Regular Papers","issn_l":"1549-8328","issn":["1549-8328","1558-0806"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Circuits and Systems I: Regular Papers","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5028637596","display_name":"Jianyu Zhong","orcid":"https://orcid.org/0000-0001-5761-2209"},"institutions":[{"id":"https://openalex.org/I204512498","display_name":"University of Macau","ror":"https://ror.org/01r4q9n85","country_code":"MO","type":"education","lineage":["https://openalex.org/I204512498"]}],"countries":["MO"],"is_corresponding":true,"raw_author_name":"Jianyu Zhong","raw_affiliation_strings":["State Key Laboratory of Analog and Mixed-Signal VLSI, University of Macau, Macao, China"],"affiliations":[{"raw_affiliation_string":"State Key Laboratory of Analog and Mixed-Signal VLSI, University of Macau, Macao, China","institution_ids":["https://openalex.org/I204512498"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5071933088","display_name":"Yan Zhu","orcid":"https://orcid.org/0000-0002-8298-3244"},"institutions":[{"id":"https://openalex.org/I204512498","display_name":"University of Macau","ror":"https://ror.org/01r4q9n85","country_code":"MO","type":"education","lineage":["https://openalex.org/I204512498"]}],"countries":["MO"],"is_corresponding":false,"raw_author_name":"Yan Zhu","raw_affiliation_strings":["State Key Laboratory of Analog and Mixed-Signal VLSI, University of Macau, Macao, China"],"affiliations":[{"raw_affiliation_string":"State Key Laboratory of Analog and Mixed-Signal VLSI, University of Macau, Macao, China","institution_ids":["https://openalex.org/I204512498"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5035229843","display_name":"Chi\u2010Hang Chan","orcid":"https://orcid.org/0000-0002-7635-1101"},"institutions":[{"id":"https://openalex.org/I204512498","display_name":"University of Macau","ror":"https://ror.org/01r4q9n85","country_code":"MO","type":"education","lineage":["https://openalex.org/I204512498"]}],"countries":["MO"],"is_corresponding":false,"raw_author_name":"Chi-Hang Chan","raw_affiliation_strings":["State Key Laboratory of Analog and Mixed-Signal VLSI, University of Macau, Macao, China"],"affiliations":[{"raw_affiliation_string":"State Key Laboratory of Analog and Mixed-Signal VLSI, University of Macau, Macao, China","institution_ids":["https://openalex.org/I204512498"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5073702117","display_name":"Sai\u2010Weng Sin","orcid":"https://orcid.org/0000-0001-9346-8291"},"institutions":[{"id":"https://openalex.org/I204512498","display_name":"University of Macau","ror":"https://ror.org/01r4q9n85","country_code":"MO","type":"education","lineage":["https://openalex.org/I204512498"]}],"countries":["MO"],"is_corresponding":false,"raw_author_name":"Sai-Weng Sin","raw_affiliation_strings":["State Key Laboratory of Analog and Mixed-Signal VLSI, University of Macau, Macao, China"],"affiliations":[{"raw_affiliation_string":"State Key Laboratory of Analog and Mixed-Signal VLSI, University of Macau, Macao, China","institution_ids":["https://openalex.org/I204512498"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5061042931","display_name":"U Seng\u2010Pan","orcid":null},"institutions":[{"id":"https://openalex.org/I204512498","display_name":"University of Macau","ror":"https://ror.org/01r4q9n85","country_code":"MO","type":"education","lineage":["https://openalex.org/I204512498"]}],"countries":["MO"],"is_corresponding":false,"raw_author_name":"Seng-Pan U.","raw_affiliation_strings":["University of Macau, Taipa, Macau, MO"],"affiliations":[{"raw_affiliation_string":"University of Macau, Taipa, Macau, MO","institution_ids":["https://openalex.org/I204512498"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5106943352","display_name":"Rui P. Martins","orcid":"https://orcid.org/0000-0003-2821-648X"},"institutions":[{"id":"https://openalex.org/I203847022","display_name":"Instituto Polit\u00e9cnico de Lisboa","ror":"https://ror.org/04ea70f07","country_code":"PT","type":"education","lineage":["https://openalex.org/I203847022"]},{"id":"https://openalex.org/I141596103","display_name":"University of Lisbon","ror":"https://ror.org/01c27hj86","country_code":"PT","type":"education","lineage":["https://openalex.org/I141596103"]},{"id":"https://openalex.org/I204512498","display_name":"University of Macau","ror":"https://ror.org/01r4q9n85","country_code":"MO","type":"education","lineage":["https://openalex.org/I204512498"]}],"countries":["MO","PT"],"is_corresponding":false,"raw_author_name":"Rui Paulo Martins","raw_affiliation_strings":["Department of Electrical and Computer Engineering, Faculty of Science and Technology, University of Macau, Macao, China","Instituto Superior T\u00e9cnico, Universidade de Lisboa, Lisboa, Portugal"],"affiliations":[{"raw_affiliation_string":"Department of Electrical and Computer Engineering, Faculty of Science and Technology, University of Macau, Macao, China","institution_ids":["https://openalex.org/I204512498"]},{"raw_affiliation_string":"Instituto Superior T\u00e9cnico, Universidade de Lisboa, Lisboa, Portugal","institution_ids":["https://openalex.org/I203847022","https://openalex.org/I141596103"]}]}],"institutions":[],"countries_distinct_count":2,"institutions_distinct_count":6,"corresponding_author_ids":["https://openalex.org/A5028637596"],"corresponding_institution_ids":["https://openalex.org/I204512498"],"apc_list":null,"apc_paid":null,"fwci":1.56,"has_fulltext":false,"cited_by_count":32,"citation_normalized_percentile":{"value":0.81399908,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":96,"max":99},"biblio":{"volume":"64","issue":"7","first_page":"1684","last_page":"1695"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10323","display_name":"Analog and Mixed-Signal Circuit Design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2204","display_name":"Biomedical Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10323","display_name":"Analog and Mixed-Signal Circuit Design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2204","display_name":"Biomedical Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10558","display_name":"Advancements in Semiconductor Devices and Circuit Design","score":0.9993000030517578,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10187","display_name":"Radio Frequency Integrated Circuit Design","score":0.9990000128746033,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/successive-approximation-adc","display_name":"Successive approximation ADC","score":0.7984522581100464},{"id":"https://openalex.org/keywords/linearity","display_name":"Linearity","score":0.6867454051971436},{"id":"https://openalex.org/keywords/cmos","display_name":"CMOS","score":0.5698867440223694},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.533611536026001},{"id":"https://openalex.org/keywords/calibration","display_name":"Calibration","score":0.5290915966033936},{"id":"https://openalex.org/keywords/amplifier","display_name":"Amplifier","score":0.5101931095123291},{"id":"https://openalex.org/keywords/offset","display_name":"Offset (computer science)","score":0.5014312267303467},{"id":"https://openalex.org/keywords/comparator","display_name":"Comparator","score":0.4962967038154602},{"id":"https://openalex.org/keywords/chip","display_name":"Chip","score":0.4780578911304474},{"id":"https://openalex.org/keywords/oversampling","display_name":"Oversampling","score":0.4668021500110626},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.42680028080940247},{"id":"https://openalex.org/keywords/physics","display_name":"Physics","score":0.26547545194625854},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.2166765332221985},{"id":"https://openalex.org/keywords/voltage","display_name":"Voltage","score":0.15732896327972412},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.1447111964225769},{"id":"https://openalex.org/keywords/telecommunications","display_name":"Telecommunications","score":0.11975544691085815}],"concepts":[{"id":"https://openalex.org/C60154766","wikidata":"https://www.wikidata.org/wiki/Q2650458","display_name":"Successive approximation ADC","level":4,"score":0.7984522581100464},{"id":"https://openalex.org/C77170095","wikidata":"https://www.wikidata.org/wiki/Q1753188","display_name":"Linearity","level":2,"score":0.6867454051971436},{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.5698867440223694},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.533611536026001},{"id":"https://openalex.org/C165838908","wikidata":"https://www.wikidata.org/wiki/Q736777","display_name":"Calibration","level":2,"score":0.5290915966033936},{"id":"https://openalex.org/C194257627","wikidata":"https://www.wikidata.org/wiki/Q211554","display_name":"Amplifier","level":3,"score":0.5101931095123291},{"id":"https://openalex.org/C175291020","wikidata":"https://www.wikidata.org/wiki/Q1156822","display_name":"Offset (computer science)","level":2,"score":0.5014312267303467},{"id":"https://openalex.org/C155745195","wikidata":"https://www.wikidata.org/wiki/Q1164179","display_name":"Comparator","level":3,"score":0.4962967038154602},{"id":"https://openalex.org/C165005293","wikidata":"https://www.wikidata.org/wiki/Q1074500","display_name":"Chip","level":2,"score":0.4780578911304474},{"id":"https://openalex.org/C197323446","wikidata":"https://www.wikidata.org/wiki/Q331222","display_name":"Oversampling","level":3,"score":0.4668021500110626},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.42680028080940247},{"id":"https://openalex.org/C121332964","wikidata":"https://www.wikidata.org/wiki/Q413","display_name":"Physics","level":0,"score":0.26547545194625854},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.2166765332221985},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.15732896327972412},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.1447111964225769},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.11975544691085815},{"id":"https://openalex.org/C62520636","wikidata":"https://www.wikidata.org/wiki/Q944","display_name":"Quantum mechanics","level":1,"score":0.0},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/tcsi.2017.2679748","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tcsi.2017.2679748","pdf_url":null,"source":{"id":"https://openalex.org/S116977442","display_name":"IEEE Transactions on Circuits and Systems I Regular Papers","issn_l":"1549-8328","issn":["1549-8328","1558-0806"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Circuits and Systems I: Regular Papers","raw_type":"journal-article"}],"best_oa_location":null,"sustainable_development_goals":[{"score":0.75,"id":"https://metadata.un.org/sdg/7","display_name":"Affordable and clean energy"}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":39,"referenced_works":["https://openalex.org/W21385071","https://openalex.org/W1491617848","https://openalex.org/W1967180561","https://openalex.org/W1968315717","https://openalex.org/W2019274525","https://openalex.org/W2033779298","https://openalex.org/W2050902520","https://openalex.org/W2051606634","https://openalex.org/W2078171434","https://openalex.org/W2085967153","https://openalex.org/W2096997321","https://openalex.org/W2099731160","https://openalex.org/W2100749576","https://openalex.org/W2101004723","https://openalex.org/W2101468035","https://openalex.org/W2102696094","https://openalex.org/W2120844337","https://openalex.org/W2131585911","https://openalex.org/W2135751681","https://openalex.org/W2137774000","https://openalex.org/W2157973566","https://openalex.org/W2160620074","https://openalex.org/W2170992050","https://openalex.org/W2172010302","https://openalex.org/W2172236250","https://openalex.org/W2285437171","https://openalex.org/W2323444784","https://openalex.org/W4230544499","https://openalex.org/W4244619305","https://openalex.org/W6663387598","https://openalex.org/W6663410101","https://openalex.org/W6670058427","https://openalex.org/W6671930277","https://openalex.org/W6675613766","https://openalex.org/W6678139478","https://openalex.org/W6679454727","https://openalex.org/W6683103085","https://openalex.org/W6685204329","https://openalex.org/W6812358060"],"related_works":["https://openalex.org/W3213706674","https://openalex.org/W2022951482","https://openalex.org/W2742121197","https://openalex.org/W3119852575","https://openalex.org/W3044833173","https://openalex.org/W2781677288","https://openalex.org/W2802320849","https://openalex.org/W3082868690","https://openalex.org/W2094976268","https://openalex.org/W2096197213"],"abstract_inverted_index":{"This":[0],"paper":[1],"presents":[2],"a":[3,55,65,75,122,127],"12b":[4],"180":[5],"MS/s":[6],"0.068":[7],"mm":[8],"<sup":[9],"xmlns:mml=\"http://www.w3.org/1998/Math/MathML\"":[10],"xmlns:xlink=\"http://www.w3.org/1999/xlink\">2</sup>":[11],"2\u00d7":[12],"time-interleaved":[13],"pipelined-SAR":[14],"analog-to-digital":[15],"converter":[16],"(ADC)":[17],"with":[18],"gain":[19,29,36],"and":[20],"offset":[21],"calibrations":[22],"fully":[23,46],"embedded":[24],"on-chip.":[25],"The":[26,44,89],"proposed":[27,105],"binary-search":[28],"calibration":[30,106],"(BSGC)":[31],"technique":[32,78],"corrects":[33],"the":[34,40,49,60,69,81,85,93,101,104,108,111],"inter-stage":[35],"error":[37],"caused":[38],"by":[39,63],"open-loop":[41],"residue":[42],"amplifier.":[43],"BSGC,":[45],"integrated":[47],"into":[48],"second-stage":[50],"SAR":[51],"ADC,":[52],"contributes":[53],"to":[54,79,113,118,126],"compact":[56],"area.":[57],"We":[58],"improve":[59,80],"noise":[61],"performance":[62],"implementing":[64],"mergedresidue-DAC":[66],"operation":[67],"in":[68,84,96],"first-stage":[70],"ADC.":[71],"Also,":[72],"we":[73],"propose":[74],"dual-phase":[76],"bootstrap":[77],"sampling":[82],"linearity":[83],"partial":[86],"interleaving":[87],"architecture.":[88],"measurement":[90],"results":[91],"of":[92,103,110,129],"ADC":[94],"prototype":[95],"65":[97],"nm":[98],"CMOS":[99],"demonstrate":[100],"effectiveness":[102],"through":[107],"enhancement":[109],"signal":[112],"noise-and-distortion":[114],"ratio":[115],"from":[116],"51.5":[117],"60.9":[119],"dB":[120],"at":[121],"Nyquist":[123],"input,":[124],"leading":[125],"FoM@Nyq":[128],"36.7":[130],"fJ/conversion-step.":[131]},"counts_by_year":[{"year":2026,"cited_by_count":1},{"year":2024,"cited_by_count":7},{"year":2023,"cited_by_count":4},{"year":2022,"cited_by_count":4},{"year":2021,"cited_by_count":4},{"year":2020,"cited_by_count":5},{"year":2019,"cited_by_count":4},{"year":2018,"cited_by_count":3}],"updated_date":"2026-03-04T09:10:02.777135","created_date":"2025-10-10T00:00:00"}