{"id":"https://openalex.org/W2528373198","doi":"https://doi.org/10.1109/tcsi.2016.2600538","title":"Opportunistic Refreshing Algorithm for eDRAM Memories","display_name":"Opportunistic Refreshing Algorithm for eDRAM Memories","publication_year":2016,"publication_date":"2016-10-06","ids":{"openalex":"https://openalex.org/W2528373198","doi":"https://doi.org/10.1109/tcsi.2016.2600538","mag":"2528373198"},"language":"en","primary_location":{"id":"doi:10.1109/tcsi.2016.2600538","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tcsi.2016.2600538","pdf_url":null,"source":{"id":"https://openalex.org/S116977442","display_name":"IEEE Transactions on Circuits and Systems I Regular Papers","issn_l":"1549-8328","issn":["1549-8328","1558-0806"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Circuits and Systems I: Regular Papers","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5025782240","display_name":"Amit Kazimirsky","orcid":null},"institutions":[{"id":"https://openalex.org/I13955877","display_name":"Bar-Ilan University","ror":"https://ror.org/03kgsv495","country_code":"IL","type":"education","lineage":["https://openalex.org/I13955877"]}],"countries":["IL"],"is_corresponding":true,"raw_author_name":"Amit Kazimirsky","raw_affiliation_strings":["Engineering Faculty, Bar-Ilan University, Ramat-Gan, Israel"],"affiliations":[{"raw_affiliation_string":"Engineering Faculty, Bar-Ilan University, Ramat-Gan, Israel","institution_ids":["https://openalex.org/I13955877"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5000817401","display_name":"Shmuel Wimer","orcid":"https://orcid.org/0000-0002-5728-0061"},"institutions":[{"id":"https://openalex.org/I13955877","display_name":"Bar-Ilan University","ror":"https://ror.org/03kgsv495","country_code":"IL","type":"education","lineage":["https://openalex.org/I13955877"]}],"countries":["IL"],"is_corresponding":false,"raw_author_name":"Shmuel Wimer","raw_affiliation_strings":["Engineering Faculty, Bar-Ilan University, Ramat-Gan, Israel"],"affiliations":[{"raw_affiliation_string":"Engineering Faculty, Bar-Ilan University, Ramat-Gan, Israel","institution_ids":["https://openalex.org/I13955877"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":2,"corresponding_author_ids":["https://openalex.org/A5025782240"],"corresponding_institution_ids":["https://openalex.org/I13955877"],"apc_list":null,"apc_paid":null,"fwci":1.5767,"has_fulltext":false,"cited_by_count":17,"citation_normalized_percentile":{"value":0.82631183,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":97},"biblio":{"volume":"63","issue":"11","first_page":"1921","last_page":"1932"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11181","display_name":"Advanced Data Storage Technologies","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7247529029846191},{"id":"https://openalex.org/keywords/dram","display_name":"Dram","score":0.6606287956237793},{"id":"https://openalex.org/keywords/static-random-access-memory","display_name":"Static random-access memory","score":0.6587474942207336},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.5431205034255981},{"id":"https://openalex.org/keywords/cache","display_name":"Cache","score":0.4682767391204834},{"id":"https://openalex.org/keywords/access-time","display_name":"Access time","score":0.4645618498325348},{"id":"https://openalex.org/keywords/universal-memory","display_name":"Universal memory","score":0.42498520016670227},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.41509589552879333},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.40389537811279297},{"id":"https://openalex.org/keywords/interleaved-memory","display_name":"Interleaved memory","score":0.34698155522346497},{"id":"https://openalex.org/keywords/semiconductor-memory","display_name":"Semiconductor memory","score":0.3248278796672821},{"id":"https://openalex.org/keywords/memory-management","display_name":"Memory management","score":0.19359615445137024}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7247529029846191},{"id":"https://openalex.org/C7366592","wikidata":"https://www.wikidata.org/wiki/Q1255620","display_name":"Dram","level":2,"score":0.6606287956237793},{"id":"https://openalex.org/C68043766","wikidata":"https://www.wikidata.org/wiki/Q267416","display_name":"Static random-access memory","level":2,"score":0.6587474942207336},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.5431205034255981},{"id":"https://openalex.org/C115537543","wikidata":"https://www.wikidata.org/wiki/Q165596","display_name":"Cache","level":2,"score":0.4682767391204834},{"id":"https://openalex.org/C194080101","wikidata":"https://www.wikidata.org/wiki/Q46306","display_name":"Access time","level":2,"score":0.4645618498325348},{"id":"https://openalex.org/C195053848","wikidata":"https://www.wikidata.org/wiki/Q7894141","display_name":"Universal memory","level":5,"score":0.42498520016670227},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.41509589552879333},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.40389537811279297},{"id":"https://openalex.org/C63511323","wikidata":"https://www.wikidata.org/wiki/Q908936","display_name":"Interleaved memory","level":4,"score":0.34698155522346497},{"id":"https://openalex.org/C98986596","wikidata":"https://www.wikidata.org/wiki/Q1143031","display_name":"Semiconductor memory","level":2,"score":0.3248278796672821},{"id":"https://openalex.org/C176649486","wikidata":"https://www.wikidata.org/wiki/Q2308807","display_name":"Memory management","level":3,"score":0.19359615445137024}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/tcsi.2016.2600538","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tcsi.2016.2600538","pdf_url":null,"source":{"id":"https://openalex.org/S116977442","display_name":"IEEE Transactions on Circuits and Systems I Regular Papers","issn_l":"1549-8328","issn":["1549-8328","1558-0806"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Circuits and Systems I: Regular Papers","raw_type":"journal-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":33,"referenced_works":["https://openalex.org/W90009797","https://openalex.org/W1827639723","https://openalex.org/W1971936677","https://openalex.org/W1975907171","https://openalex.org/W2002293402","https://openalex.org/W2022820501","https://openalex.org/W2030754768","https://openalex.org/W2034639175","https://openalex.org/W2093163564","https://openalex.org/W2097243222","https://openalex.org/W2097346754","https://openalex.org/W2097538613","https://openalex.org/W2098040113","https://openalex.org/W2105102111","https://openalex.org/W2110999128","https://openalex.org/W2113958750","https://openalex.org/W2116567461","https://openalex.org/W2119092821","https://openalex.org/W2139138768","https://openalex.org/W2139957539","https://openalex.org/W2157587823","https://openalex.org/W2158319074","https://openalex.org/W2159253302","https://openalex.org/W2161091390","https://openalex.org/W3007321493","https://openalex.org/W3021620047","https://openalex.org/W3100461726","https://openalex.org/W4210632566","https://openalex.org/W4234157055","https://openalex.org/W4241412916","https://openalex.org/W4243164749","https://openalex.org/W4252828742","https://openalex.org/W4285719527"],"related_works":["https://openalex.org/W2080843961","https://openalex.org/W2924367614","https://openalex.org/W2127643145","https://openalex.org/W1030357071","https://openalex.org/W4232117715","https://openalex.org/W4238754064","https://openalex.org/W2340699851","https://openalex.org/W2188534734","https://openalex.org/W2183575955","https://openalex.org/W176832019"],"abstract_inverted_index":{"Embedded":[0],"DRAM":[1],"(eDRAM)":[2],"is":[3],"an":[4,25,49],"alternative":[5],"technology":[6],"that":[7],"can":[8],"replace":[9],"the":[10,22,35,55,68,72,76,82,89,95],"area":[11,23],"and":[12,24,59,78,109,118],"power":[13,30],"consumed":[14],"by":[15,41],"SRAM":[16],"cache":[17],"memories.":[18],"eDRAM":[19,116],"consumes":[20],"half":[21],"order":[26],"of":[27,37,67,71,75,81,115],"magnitude":[28],"less":[29],"than":[31],"SRAM,":[32],"but":[33],"has":[34],"drawback":[36],"access":[38,69,107],"blockage":[39],"caused":[40],"its":[42],"periodic":[43],"data":[44],"refreshing.":[45],"This":[46,63,93],"paper":[47],"presents":[48],"opportunistic":[50],"refreshing":[51,83,96],"algorithm":[52,101],"along":[53],"with":[54,88,104],"appropriate":[56],"memory":[57,77,120],"architecture":[58,64],"skim":[60],"control":[61],"logic.":[62],"takes":[65],"advantage":[66],"idleness":[70],"internal":[73,119],"partitions":[74],"enables":[79],"most":[80],"operations":[84],"to":[85],"run":[86],"concurrently":[87],"ordinary":[90],"R/W":[91],"access.":[92],"eliminates":[94],"burden":[97],"almost":[98],"completely.":[99],"The":[100],"was":[102],"simulated":[103],"industrial":[105],"DSP":[106],"traces,":[108],"outperformed":[110],"in":[111],"a":[112],"wide":[113],"range":[114],"technologies":[117],"architectures.":[121]},"counts_by_year":[{"year":2024,"cited_by_count":1},{"year":2023,"cited_by_count":1},{"year":2022,"cited_by_count":4},{"year":2021,"cited_by_count":3},{"year":2020,"cited_by_count":3},{"year":2019,"cited_by_count":2},{"year":2018,"cited_by_count":2},{"year":2017,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}