{"id":"https://openalex.org/W2263042501","doi":"https://doi.org/10.1109/tcsi.2016.2528079","title":"A Study on the Programming Structures for RRAM-Based FPGA Architectures","display_name":"A Study on the Programming Structures for RRAM-Based FPGA Architectures","publication_year":2016,"publication_date":"2016-03-10","ids":{"openalex":"https://openalex.org/W2263042501","doi":"https://doi.org/10.1109/tcsi.2016.2528079","mag":"2263042501"},"language":"en","primary_location":{"id":"doi:10.1109/tcsi.2016.2528079","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tcsi.2016.2528079","pdf_url":null,"source":{"id":"https://openalex.org/S116977442","display_name":"IEEE Transactions on Circuits and Systems I Regular Papers","issn_l":"1549-8328","issn":["1549-8328","1558-0806"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Circuits and Systems I: Regular Papers","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":true,"oa_status":"green","oa_url":"http://infoscience.epfl.ch/record/215924","any_repository_has_fulltext":true},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5103004961","display_name":"Xifan Tang","orcid":"https://orcid.org/0000-0003-2203-3981"},"institutions":[{"id":"https://openalex.org/I5124864","display_name":"\u00c9cole Polytechnique F\u00e9d\u00e9rale de Lausanne","ror":"https://ror.org/02s376052","country_code":"CH","type":"education","lineage":["https://openalex.org/I2799323385","https://openalex.org/I5124864"]}],"countries":["CH"],"is_corresponding":true,"raw_author_name":"Xifan Tang","raw_affiliation_strings":["Integrated Systems Laboratory, School of Computer and Communication Sciences, \u00c9cole Polytechnique F\u00e9d\u00e9rale de Lausanne (EPFL), Vaud, Switzerland"],"affiliations":[{"raw_affiliation_string":"Integrated Systems Laboratory, School of Computer and Communication Sciences, \u00c9cole Polytechnique F\u00e9d\u00e9rale de Lausanne (EPFL), Vaud, Switzerland","institution_ids":["https://openalex.org/I5124864"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5073822029","display_name":"Gain Kim","orcid":"https://orcid.org/0000-0002-3680-8816"},"institutions":[{"id":"https://openalex.org/I5124864","display_name":"\u00c9cole Polytechnique F\u00e9d\u00e9rale de Lausanne","ror":"https://ror.org/02s376052","country_code":"CH","type":"education","lineage":["https://openalex.org/I2799323385","https://openalex.org/I5124864"]}],"countries":["CH"],"is_corresponding":false,"raw_author_name":"Gain Kim","raw_affiliation_strings":["Microelectronic System Laboratory, School of Electrical Engineering, \u00c9cole Polytechnique F\u00e9d\u00e9rale de Lausanne (EPFL), Vaud, Switzerland"],"affiliations":[{"raw_affiliation_string":"Microelectronic System Laboratory, School of Electrical Engineering, \u00c9cole Polytechnique F\u00e9d\u00e9rale de Lausanne (EPFL), Vaud, Switzerland","institution_ids":["https://openalex.org/I5124864"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5002568331","display_name":"Pierre\u2010Emmanuel Gaillardon","orcid":"https://orcid.org/0000-0003-3634-3999"},"institutions":[{"id":"https://openalex.org/I5124864","display_name":"\u00c9cole Polytechnique F\u00e9d\u00e9rale de Lausanne","ror":"https://ror.org/02s376052","country_code":"CH","type":"education","lineage":["https://openalex.org/I2799323385","https://openalex.org/I5124864"]}],"countries":["CH"],"is_corresponding":false,"raw_author_name":"Pierre-Emmanuel Gaillardon","raw_affiliation_strings":["Integrated Systems Laboratory, School of Computer and Communication Sciences, \u00c9cole Polytechnique F\u00e9d\u00e9rale de Lausanne (EPFL), Vaud, Switzerland"],"affiliations":[{"raw_affiliation_string":"Integrated Systems Laboratory, School of Computer and Communication Sciences, \u00c9cole Polytechnique F\u00e9d\u00e9rale de Lausanne (EPFL), Vaud, Switzerland","institution_ids":["https://openalex.org/I5124864"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5072927296","display_name":"Giovanni De Micheli","orcid":"https://orcid.org/0000-0002-7827-3215"},"institutions":[{"id":"https://openalex.org/I5124864","display_name":"\u00c9cole Polytechnique F\u00e9d\u00e9rale de Lausanne","ror":"https://ror.org/02s376052","country_code":"CH","type":"education","lineage":["https://openalex.org/I2799323385","https://openalex.org/I5124864"]}],"countries":["CH"],"is_corresponding":false,"raw_author_name":"Giovanni De Micheli","raw_affiliation_strings":["Integrated Systems Laboratory, School of Computer and Communication Sciences, \u00c9cole Polytechnique F\u00e9d\u00e9rale de Lausanne (EPFL), Vaud, Switzerland"],"affiliations":[{"raw_affiliation_string":"Integrated Systems Laboratory, School of Computer and Communication Sciences, \u00c9cole Polytechnique F\u00e9d\u00e9rale de Lausanne (EPFL), Vaud, Switzerland","institution_ids":["https://openalex.org/I5124864"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":4,"corresponding_author_ids":["https://openalex.org/A5103004961"],"corresponding_institution_ids":["https://openalex.org/I5124864"],"apc_list":null,"apc_paid":null,"fwci":4.9616,"has_fulltext":false,"cited_by_count":44,"citation_normalized_percentile":{"value":0.95491251,"is_in_top_1_percent":false,"is_in_top_10_percent":true},"cited_by_percentile_year":{"min":90,"max":99},"biblio":{"volume":"63","issue":"4","first_page":"503","last_page":"516"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10502","display_name":"Advanced Memory and Neural Computing","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10502","display_name":"Advanced Memory and Neural Computing","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T12808","display_name":"Ferroelectric and Negative Capacitance Devices","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10472","display_name":"Semiconductor materials and devices","score":0.996999979019165,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/resistive-random-access-memory","display_name":"Resistive random-access memory","score":0.8926671147346497},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.7007958292961121},{"id":"https://openalex.org/keywords/boosting","display_name":"Boosting (machine learning)","score":0.6706729531288147},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.5800305604934692},{"id":"https://openalex.org/keywords/datapath","display_name":"Datapath","score":0.4897732734680176},{"id":"https://openalex.org/keywords/programming-paradigm","display_name":"Programming paradigm","score":0.42529261112213135},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.3320152759552002},{"id":"https://openalex.org/keywords/computer-engineering","display_name":"Computer engineering","score":0.3263295292854309},{"id":"https://openalex.org/keywords/artificial-intelligence","display_name":"Artificial intelligence","score":0.32091444730758667},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.2755752205848694},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.27399706840515137},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.25746360421180725},{"id":"https://openalex.org/keywords/voltage","display_name":"Voltage","score":0.25618666410446167},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.16502636671066284},{"id":"https://openalex.org/keywords/programming-language","display_name":"Programming language","score":0.14043325185775757}],"concepts":[{"id":"https://openalex.org/C182019814","wikidata":"https://www.wikidata.org/wiki/Q1143830","display_name":"Resistive random-access memory","level":3,"score":0.8926671147346497},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.7007958292961121},{"id":"https://openalex.org/C46686674","wikidata":"https://www.wikidata.org/wiki/Q466303","display_name":"Boosting (machine learning)","level":2,"score":0.6706729531288147},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.5800305604934692},{"id":"https://openalex.org/C2781198647","wikidata":"https://www.wikidata.org/wiki/Q1633673","display_name":"Datapath","level":2,"score":0.4897732734680176},{"id":"https://openalex.org/C34165917","wikidata":"https://www.wikidata.org/wiki/Q188267","display_name":"Programming paradigm","level":2,"score":0.42529261112213135},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.3320152759552002},{"id":"https://openalex.org/C113775141","wikidata":"https://www.wikidata.org/wiki/Q428691","display_name":"Computer engineering","level":1,"score":0.3263295292854309},{"id":"https://openalex.org/C154945302","wikidata":"https://www.wikidata.org/wiki/Q11660","display_name":"Artificial intelligence","level":1,"score":0.32091444730758667},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.2755752205848694},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.27399706840515137},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.25746360421180725},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.25618666410446167},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.16502636671066284},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.14043325185775757}],"mesh":[],"locations_count":3,"locations":[{"id":"doi:10.1109/tcsi.2016.2528079","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tcsi.2016.2528079","pdf_url":null,"source":{"id":"https://openalex.org/S116977442","display_name":"IEEE Transactions on Circuits and Systems I Regular Papers","issn_l":"1549-8328","issn":["1549-8328","1558-0806"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Circuits and Systems I: Regular Papers","raw_type":"journal-article"},{"id":"pmh:oai:infoscience.epfl.ch:215924","is_oa":true,"landing_page_url":"http://infoscience.epfl.ch/record/215924","pdf_url":null,"source":{"id":"https://openalex.org/S4306400487","display_name":"Infoscience (Ecole Polytechnique F\u00e9d\u00e9rale de Lausanne)","issn_l":null,"issn":null,"is_oa":true,"is_in_doaj":false,"is_core":false,"host_organization":null,"host_organization_name":null,"host_organization_lineage":[],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"","raw_type":"Text"},{"id":"pmh:oai:infoscience.tind.io:215924","is_oa":true,"landing_page_url":"https://infoscience.epfl.ch/handle/20.500.14299/123403","pdf_url":null,"source":{"id":"https://openalex.org/S4306400487","display_name":"Infoscience (Ecole Polytechnique F\u00e9d\u00e9rale de Lausanne)","issn_l":null,"issn":null,"is_oa":true,"is_in_doaj":false,"is_core":false,"host_organization":null,"host_organization_name":null,"host_organization_lineage":[],"host_organization_lineage_names":[],"type":"repository"},"license":"cc-by-nc-nd","license_id":"https://openalex.org/licenses/cc-by-nc-nd","version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":null,"raw_type":"research article"}],"best_oa_location":{"id":"pmh:oai:infoscience.epfl.ch:215924","is_oa":true,"landing_page_url":"http://infoscience.epfl.ch/record/215924","pdf_url":null,"source":{"id":"https://openalex.org/S4306400487","display_name":"Infoscience (Ecole Polytechnique F\u00e9d\u00e9rale de Lausanne)","issn_l":null,"issn":null,"is_oa":true,"is_in_doaj":false,"is_core":false,"host_organization":null,"host_organization_name":null,"host_organization_lineage":[],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"","raw_type":"Text"},"sustainable_development_goals":[],"awards":[{"id":"https://openalex.org/G6748573657","display_name":null,"funder_award_id":"200021-146600","funder_id":"https://openalex.org/F4320320924","funder_display_name":"Schweizerischer Nationalfonds zur F\u00f6rderung der Wissenschaftlichen Forschung"}],"funders":[{"id":"https://openalex.org/F4320320924","display_name":"Schweizerischer Nationalfonds zur F\u00f6rderung der Wissenschaftlichen Forschung","ror":"https://ror.org/00yjd3n13"}],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":24,"referenced_works":["https://openalex.org/W1596998040","https://openalex.org/W1971000062","https://openalex.org/W1977773606","https://openalex.org/W2001744188","https://openalex.org/W2004823737","https://openalex.org/W2006798699","https://openalex.org/W2019965721","https://openalex.org/W2030765577","https://openalex.org/W2033811947","https://openalex.org/W2040094671","https://openalex.org/W2045197688","https://openalex.org/W2078177817","https://openalex.org/W2086709250","https://openalex.org/W2105408739","https://openalex.org/W2120544688","https://openalex.org/W2136983830","https://openalex.org/W2139911369","https://openalex.org/W2146437820","https://openalex.org/W3150512006","https://openalex.org/W4214686615","https://openalex.org/W4243164749","https://openalex.org/W6635836132","https://openalex.org/W6681989696","https://openalex.org/W7054665252"],"related_works":["https://openalex.org/W2109699519","https://openalex.org/W970262775","https://openalex.org/W1831618318","https://openalex.org/W2907761035","https://openalex.org/W2006568360","https://openalex.org/W4244724753","https://openalex.org/W2059591361","https://openalex.org/W2535673728","https://openalex.org/W1972081536","https://openalex.org/W102726818"],"abstract_inverted_index":{"Field":[0],"Programmable":[1],"Gate":[2],"Arrays":[3],"(FPGAs)":[4],"can":[5,33],"benefit":[6],"non-volatility":[7],"and":[8,28,39,109,127,139,161,168,215],"high-performance":[9,44],"by":[10,46,212,218],"exploiting":[11],"Resistive":[12],"Random":[13],"Access":[14],"Memories":[15],"(RRAMs).":[16],"In":[17,94],"RRAM-based":[18,47],"FPGAs,":[19],"the":[20,26,36,51,54,57,67,100,103,115,143,151,175,179,187,201,208],"memories":[21],"do":[22],"not":[23],"only":[24],"replace":[25,35],"SRAMs":[27],"store":[29],"configurations,":[30],"but":[31],"they":[32],"also":[34,173],"transmission":[37,72],"gates":[38],"propagate":[40],"datapath":[41],"signals.":[42],"The":[43],"achievable":[45],"FPGAs":[48],"comes":[49],"from":[50],"fact":[52],"that":[53,193],"on-resistance":[55],"of":[56,70,102,114,155,177,186,207],"memory":[58],"devices":[59],"R":[60],"<sub":[61,183,196],"xmlns:mml=\"http://www.w3.org/1998/Math/MathML\"":[62,184,197],"xmlns:xlink=\"http://www.w3.org/1999/xlink\">LRS</sub>":[63],"is":[64,150],"smaller":[65],"than":[66],"equivalent":[68],"resistance":[69],"a":[71,85,91,124,128],"gate.":[73],"Efficient":[74],"programming":[75,107,132,145,148,180,188,202,210],"structures":[76,203,211],"for":[77,199],"RRAMs":[78],"should":[79],"provide":[80],"high":[81],"current":[82,156,206],"density":[83,157],"with":[84,158],"small":[86],"area":[87,216],"footprint,":[88],"to":[89,166],"obtain":[90],"low":[92],"RLRS.":[93],"this":[95],"paper,":[96],"we":[97,122],"first":[98],"examine":[99],"efficiency":[101,217],"widely-used":[104],"2Transistor/1RRAM":[105],"(2T1R)":[106],"structure":[108,149],"identify":[110],"four":[111],"major":[112],"limitations":[113],"2T1R":[116,167],"structure.":[117],"To":[118],"overcome":[119],"these":[120],"limitations,":[121],"propose":[123],"2Transmission-Gates/1RRAM":[125],"(2TG1R)":[126],"4Transistor/":[129],"1RRAM":[130],"(4T1R)":[131],"structures.":[133,146,189],"We":[134,172],"perform":[135],"both":[136],"theoretical":[137],"analysis":[138],"electrical":[140],"simulations":[141],"on":[142,221],"evaluated":[144,209],"4T1R":[147],"best":[152],"in":[153],"terms":[154],"1.4":[159],"x":[160,163,214,220],"1.1":[162],"as":[164],"compared":[165],"2TG1R":[169],"counterparts,":[170],"respectively.":[171],"investigate":[174],"effect":[176],"boosting":[178,194],"voltage":[181],"V":[182,195],"xmlns:xlink=\"http://www.w3.org/1999/xlink\">prog</sub>":[185,198],"Experimental":[190],"results":[191],"show":[192],"all":[200],"improves":[204],"driving":[205],"3":[213],"1.7":[219],"average.":[222]},"counts_by_year":[{"year":2025,"cited_by_count":2},{"year":2024,"cited_by_count":1},{"year":2023,"cited_by_count":2},{"year":2022,"cited_by_count":4},{"year":2021,"cited_by_count":4},{"year":2020,"cited_by_count":4},{"year":2019,"cited_by_count":7},{"year":2018,"cited_by_count":8},{"year":2017,"cited_by_count":7},{"year":2016,"cited_by_count":5}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}