{"id":"https://openalex.org/W1609990807","doi":"https://doi.org/10.1109/tcsi.2015.2476297","title":"An Interface for Open-Drain Bidirectional Communication in Field Programmable Interconnection Networks","display_name":"An Interface for Open-Drain Bidirectional Communication in Field Programmable Interconnection Networks","publication_year":2015,"publication_date":"2015-09-25","ids":{"openalex":"https://openalex.org/W1609990807","doi":"https://doi.org/10.1109/tcsi.2015.2476297","mag":"1609990807"},"language":"en","primary_location":{"id":"doi:10.1109/tcsi.2015.2476297","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tcsi.2015.2476297","pdf_url":null,"source":{"id":"https://openalex.org/S116977442","display_name":"IEEE Transactions on Circuits and Systems I Regular Papers","issn_l":"1549-8328","issn":["1549-8328","1558-0806"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Circuits and Systems I: Regular Papers","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5051704528","display_name":"Wasim Hussain","orcid":"https://orcid.org/0000-0003-0812-6276"},"institutions":[{"id":"https://openalex.org/I159129438","display_name":"Universit\u00e9 du Qu\u00e9bec \u00e0 Montr\u00e9al","ror":"https://ror.org/002rjbv21","country_code":"CA","type":"education","lineage":["https://openalex.org/I159129438","https://openalex.org/I49663120"]},{"id":"https://openalex.org/I45683168","display_name":"Polytechnique Montr\u00e9al","ror":"https://ror.org/05f8d4e86","country_code":"CA","type":"education","lineage":["https://openalex.org/I45683168"]}],"countries":["CA"],"is_corresponding":false,"raw_author_name":"Wasim Hussain","raw_affiliation_strings":["Polytechnique Montr\u00e9al and Universit\u00e9 du Qu\u00e9bec \u00e1 Montr\u00e9al (UQAM)","Polytechnique Montr\u00e9al and Universit\u00e9 du Qu\u00e9bec \u00e1 Montr\u00e9al (UQAM),"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Polytechnique Montr\u00e9al and Universit\u00e9 du Qu\u00e9bec \u00e1 Montr\u00e9al (UQAM)","institution_ids":["https://openalex.org/I159129438","https://openalex.org/I45683168"]},{"raw_affiliation_string":"Polytechnique Montr\u00e9al and Universit\u00e9 du Qu\u00e9bec \u00e1 Montr\u00e9al (UQAM),","institution_ids":["https://openalex.org/I159129438","https://openalex.org/I45683168"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5071840145","display_name":"Yves Blaqui\u00e8re","orcid":"https://orcid.org/0000-0001-6204-7427"},"institutions":[{"id":"https://openalex.org/I159129438","display_name":"Universit\u00e9 du Qu\u00e9bec \u00e0 Montr\u00e9al","ror":"https://ror.org/002rjbv21","country_code":"CA","type":"education","lineage":["https://openalex.org/I159129438","https://openalex.org/I49663120"]},{"id":"https://openalex.org/I45683168","display_name":"Polytechnique Montr\u00e9al","ror":"https://ror.org/05f8d4e86","country_code":"CA","type":"education","lineage":["https://openalex.org/I45683168"]}],"countries":["CA"],"is_corresponding":false,"raw_author_name":"Yves Blaquiere","raw_affiliation_strings":["Polytechnique Montr\u00e9al and Universit\u00e9 du Qu\u00e9bec \u00e1 Montr\u00e9al (UQAM)","Polytechnique Montr\u00e9al and Universit\u00e9 du Qu\u00e9bec \u00e1 Montr\u00e9al (UQAM),"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Polytechnique Montr\u00e9al and Universit\u00e9 du Qu\u00e9bec \u00e1 Montr\u00e9al (UQAM)","institution_ids":["https://openalex.org/I159129438","https://openalex.org/I45683168"]},{"raw_affiliation_string":"Polytechnique Montr\u00e9al and Universit\u00e9 du Qu\u00e9bec \u00e1 Montr\u00e9al (UQAM),","institution_ids":["https://openalex.org/I159129438","https://openalex.org/I45683168"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5038488044","display_name":"Yvon Savaria","orcid":"https://orcid.org/0000-0002-3404-9959"},"institutions":[{"id":"https://openalex.org/I159129438","display_name":"Universit\u00e9 du Qu\u00e9bec \u00e0 Montr\u00e9al","ror":"https://ror.org/002rjbv21","country_code":"CA","type":"education","lineage":["https://openalex.org/I159129438","https://openalex.org/I49663120"]},{"id":"https://openalex.org/I45683168","display_name":"Polytechnique Montr\u00e9al","ror":"https://ror.org/05f8d4e86","country_code":"CA","type":"education","lineage":["https://openalex.org/I45683168"]}],"countries":["CA"],"is_corresponding":false,"raw_author_name":"Yvon Savaria","raw_affiliation_strings":["Polytechnique Montr\u00e9al and Universit\u00e9 du Qu\u00e9bec \u00e1 Montr\u00e9al (UQAM)","Polytechnique Montr\u00e9al and Universit\u00e9 du Qu\u00e9bec \u00e1 Montr\u00e9al (UQAM),"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Polytechnique Montr\u00e9al and Universit\u00e9 du Qu\u00e9bec \u00e1 Montr\u00e9al (UQAM)","institution_ids":["https://openalex.org/I159129438","https://openalex.org/I45683168"]},{"raw_affiliation_string":"Polytechnique Montr\u00e9al and Universit\u00e9 du Qu\u00e9bec \u00e1 Montr\u00e9al (UQAM),","institution_ids":["https://openalex.org/I159129438","https://openalex.org/I45683168"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":3,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":0,"citation_normalized_percentile":{"value":0.04403296,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":"62","issue":"10","first_page":"2465","last_page":"2475"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9991000294685364,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9991000294685364,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.998199999332428,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9976999759674072,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/interconnection","display_name":"Interconnection","score":0.80030357837677},{"id":"https://openalex.org/keywords/interface","display_name":"Interface (matter)","score":0.7208033800125122},{"id":"https://openalex.org/keywords/topology","display_name":"Topology (electrical circuits)","score":0.6112423539161682},{"id":"https://openalex.org/keywords/integrated-circuit","display_name":"Integrated circuit","score":0.5440359711647034},{"id":"https://openalex.org/keywords/cmos","display_name":"CMOS","score":0.5167164206504822},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.5109571814537048},{"id":"https://openalex.org/keywords/network-interface","display_name":"Network interface","score":0.4714340269565582},{"id":"https://openalex.org/keywords/electronic-circuit","display_name":"Electronic circuit","score":0.4185033440589905},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.39036691188812256},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.3226093649864197},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.2665063738822937},{"id":"https://openalex.org/keywords/computer-network","display_name":"Computer network","score":0.23433133959770203},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.20678234100341797},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.18957999348640442},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.10419014096260071}],"concepts":[{"id":"https://openalex.org/C123745756","wikidata":"https://www.wikidata.org/wiki/Q1665949","display_name":"Interconnection","level":2,"score":0.80030357837677},{"id":"https://openalex.org/C113843644","wikidata":"https://www.wikidata.org/wiki/Q901882","display_name":"Interface (matter)","level":4,"score":0.7208033800125122},{"id":"https://openalex.org/C184720557","wikidata":"https://www.wikidata.org/wiki/Q7825049","display_name":"Topology (electrical circuits)","level":2,"score":0.6112423539161682},{"id":"https://openalex.org/C530198007","wikidata":"https://www.wikidata.org/wiki/Q80831","display_name":"Integrated circuit","level":2,"score":0.5440359711647034},{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.5167164206504822},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.5109571814537048},{"id":"https://openalex.org/C103987645","wikidata":"https://www.wikidata.org/wiki/Q985806","display_name":"Network interface","level":3,"score":0.4714340269565582},{"id":"https://openalex.org/C134146338","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Electronic circuit","level":2,"score":0.4185033440589905},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.39036691188812256},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.3226093649864197},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.2665063738822937},{"id":"https://openalex.org/C31258907","wikidata":"https://www.wikidata.org/wiki/Q1301371","display_name":"Computer network","level":1,"score":0.23433133959770203},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.20678234100341797},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.18957999348640442},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.10419014096260071},{"id":"https://openalex.org/C129307140","wikidata":"https://www.wikidata.org/wiki/Q6795880","display_name":"Maximum bubble pressure method","level":3,"score":0.0},{"id":"https://openalex.org/C157915830","wikidata":"https://www.wikidata.org/wiki/Q2928001","display_name":"Bubble","level":2,"score":0.0},{"id":"https://openalex.org/C172173386","wikidata":"https://www.wikidata.org/wiki/Q79984","display_name":"Ethernet","level":2,"score":0.0}],"mesh":[],"locations_count":3,"locations":[{"id":"doi:10.1109/tcsi.2015.2476297","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tcsi.2015.2476297","pdf_url":null,"source":{"id":"https://openalex.org/S116977442","display_name":"IEEE Transactions on Circuits and Systems I Regular Papers","issn_l":"1549-8328","issn":["1549-8328","1558-0806"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Circuits and Systems I: Regular Papers","raw_type":"journal-article"},{"id":"pmh:oai:www.archipel.uqam.ca:7742","is_oa":false,"landing_page_url":null,"pdf_url":null,"source":{"id":"https://openalex.org/S4306401005","display_name":"Archipelago (Universit\u00e9 du Qu\u00e9bec \u00e0 Montr\u00e9al)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I4210093668","host_organization_name":"Quebec Intensive Silviculture Network","host_organization_lineage":["https://openalex.org/I4210093668"],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":"acceptedVersion","is_accepted":true,"is_published":false,"raw_source_name":"","raw_type":"Article de revue scientifique"},{"id":"pmh:oai:publications.polymtl.ca:34680","is_oa":false,"landing_page_url":"https://publications.polymtl.ca/34680/","pdf_url":null,"source":{"id":"https://openalex.org/S4306401013","display_name":"PolyPublie (\u00c9cole Polytechnique de Montr\u00e9al)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I45683168","host_organization_name":"Polytechnique Montr\u00e9al","host_organization_lineage":["https://openalex.org/I45683168"],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"","raw_type":"Article de revue"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[{"id":"https://openalex.org/F4320310709","display_name":"CMC Microsystems","ror":"https://ror.org/03k70ea39"},{"id":"https://openalex.org/F4320322675","display_name":"Mitacs","ror":"https://ror.org/00cjrc276"},{"id":"https://openalex.org/F4320334593","display_name":"Natural Sciences and Engineering Research Council of Canada","ror":"https://ror.org/01h531d29"}],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":2,"referenced_works":["https://openalex.org/W1534853808","https://openalex.org/W2162221699"],"related_works":["https://openalex.org/W3014521742","https://openalex.org/W2155019192","https://openalex.org/W2389800961","https://openalex.org/W1995389502","https://openalex.org/W2501578203","https://openalex.org/W2113108952","https://openalex.org/W2040773997","https://openalex.org/W3215142653","https://openalex.org/W1487051936","https://openalex.org/W194748710"],"abstract_inverted_index":{"An":[0],"open-drain":[1,52,68,130],"interface":[2,34,85,88,113,182],"circuit":[3],"and":[4,126,141,146,170],"a":[5,16,40,94,155,189],"corresponding":[6],"interconnect":[7,36,120,133],"topology":[8,123],"is":[9,162],"proposed":[10,33,84,119],"to":[11,23],"support":[12],"bidirectional":[13],"communication":[14,191],"in":[15,26,39,93],"field":[17,27],"programmable":[18,28],"interconnection":[19,46],"network":[20,47],"(FPIN),":[21],"similar":[22],"those":[24,57],"implemented":[25,125],"gate":[29],"arrays":[30],"(FPGAs).":[31],"The":[32,87,122,132],"can":[35,75,114,185],"multiple":[37,67],"nodes":[38],"FPIN.":[41],"With":[42],"that":[43,89,108,184],"interface,":[44],"the":[45,49,59,80,83,118,163,171,175,178],"imitates":[48],"behavioral":[50],"of":[51,111,137,157,165,174,181],"(or":[53],"open-collector)":[54],"buses":[55],"(e.g.,":[56],"following":[58],"I":[60,194],"<sup":[61,195],"xmlns:mml=\"http://www.w3.org/1998/Math/MathML\"":[62,196],"xmlns:xlink=\"http://www.w3.org/1999/xlink\">2</sup>":[63,197],"C":[64,198],"protocol).":[65],"Thus,":[66],"I/Os":[69],"from":[70],"external":[71],"integrated":[72],"circuits":[73,183],"(ICs)":[74],"be":[76,115,186],"connected":[77],"together":[78],"through":[79,117],"FPIN":[81,176],"by":[82],"circuit.":[86],"has":[90,134,154],"been":[91],"fabricated":[92],"0.13":[95],"\u03bcm":[96,102],"CMOS":[97],"technology":[98],"takes":[99],"65":[100],"\u03bcm\u00d722":[101],"per":[103],"pin.":[104],"Test":[105],"results":[106],"show":[107],"several":[109],"instances":[110],"this":[112],"interconnected":[116,166,187],"topology.":[121],"was":[124],"tested":[127],"combining":[128],"six":[129],"I/Os.":[131],"propagation":[135,172],"delays":[136,169,173],"approximately":[138],"0.26\u00b7n+51":[139],"ns":[140,143],"0.26\u00b7n+94":[142],"for":[144,188],"rising":[145],"falling":[147],"edge":[148],"transitions":[149],"respectively,":[150],"when":[151],"each":[152],"pin":[153],"capacitance":[156],"15":[158],"pF,":[159],"where":[160],"n":[161],"number":[164,180],"interfaces.":[167],"These":[168],"limit":[177],"maximum":[179],"given":[190],"speed":[192],"(":[193],"fast-mode":[199],"plus":[200],"with":[201],"3.4":[202],"Mbit/s).":[203]},"counts_by_year":[],"updated_date":"2026-06-11T09:08:48.828518","created_date":"2025-10-10T00:00:00"}