{"id":"https://openalex.org/W2012889040","doi":"https://doi.org/10.1109/tcsi.2014.2334791","title":"A Low Power Logic-Compatible Multi-Bit Memory Bit Cell Architecture With Differential Pair and Current Stop Constructs","display_name":"A Low Power Logic-Compatible Multi-Bit Memory Bit Cell Architecture With Differential Pair and Current Stop Constructs","publication_year":2014,"publication_date":"2014-09-17","ids":{"openalex":"https://openalex.org/W2012889040","doi":"https://doi.org/10.1109/tcsi.2014.2334791","mag":"2012889040"},"language":"en","primary_location":{"id":"doi:10.1109/tcsi.2014.2334791","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tcsi.2014.2334791","pdf_url":null,"source":{"id":"https://openalex.org/S116977442","display_name":"IEEE Transactions on Circuits and Systems I Regular Papers","issn_l":"1549-8328","issn":["1549-8328","1558-0806"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Circuits and Systems I: Regular Papers","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5052839842","display_name":"John Lynch","orcid":null},"institutions":[{"id":"https://openalex.org/I219193219","display_name":"Purdue University West Lafayette","ror":"https://ror.org/02dqehb95","country_code":"US","type":"education","lineage":["https://openalex.org/I219193219"]}],"countries":["US"],"is_corresponding":true,"raw_author_name":"John Lynch","raw_affiliation_strings":["Weldon School of Biomedical Engineering, Purdue University, West Lafayette, IN, USA","Weldon School of Biomedical Engineering, Purdue University, West Lafayette, IN, USA#TAB#"],"affiliations":[{"raw_affiliation_string":"Weldon School of Biomedical Engineering, Purdue University, West Lafayette, IN, USA","institution_ids":["https://openalex.org/I219193219"]},{"raw_affiliation_string":"Weldon School of Biomedical Engineering, Purdue University, West Lafayette, IN, USA#TAB#","institution_ids":["https://openalex.org/I219193219"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5088246631","display_name":"Pedro P. Irazoqui","orcid":"https://orcid.org/0000-0002-4791-4593"},"institutions":[{"id":"https://openalex.org/I219193219","display_name":"Purdue University West Lafayette","ror":"https://ror.org/02dqehb95","country_code":"US","type":"education","lineage":["https://openalex.org/I219193219"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Pedro P. Irazoqui","raw_affiliation_strings":["Weldon School of Biomedical Engineering, Purdue University, West Lafayette, IN, USA","Weldon School of Biomedical Engineering, Purdue University, West Lafayette, IN, USA#TAB#"],"affiliations":[{"raw_affiliation_string":"Weldon School of Biomedical Engineering, Purdue University, West Lafayette, IN, USA","institution_ids":["https://openalex.org/I219193219"]},{"raw_affiliation_string":"Weldon School of Biomedical Engineering, Purdue University, West Lafayette, IN, USA#TAB#","institution_ids":["https://openalex.org/I219193219"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":2,"corresponding_author_ids":["https://openalex.org/A5052839842"],"corresponding_institution_ids":["https://openalex.org/I219193219"],"apc_list":null,"apc_paid":null,"fwci":0.2093,"has_fulltext":false,"cited_by_count":1,"citation_normalized_percentile":{"value":0.578578,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":90,"max":94},"biblio":{"volume":"61","issue":"12","first_page":"3367","last_page":"3375"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10472","display_name":"Semiconductor materials and devices","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10558","display_name":"Advancements in Semiconductor Devices and Circuit Design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/dram","display_name":"Dram","score":0.6073664426803589},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.5876715779304504},{"id":"https://openalex.org/keywords/cmos","display_name":"CMOS","score":0.5172329545021057},{"id":"https://openalex.org/keywords/voltage","display_name":"Voltage","score":0.48012804985046387},{"id":"https://openalex.org/keywords/megabit","display_name":"Megabit","score":0.46739205718040466},{"id":"https://openalex.org/keywords/memory-architecture","display_name":"Memory architecture","score":0.45570099353790283},{"id":"https://openalex.org/keywords/power","display_name":"Power (physics)","score":0.45294779539108276},{"id":"https://openalex.org/keywords/memory-cell","display_name":"Memory cell","score":0.4441296458244324},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.43557676672935486},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.3708978295326233},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.32511889934539795},{"id":"https://openalex.org/keywords/physics","display_name":"Physics","score":0.20104637742042542},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.18906521797180176},{"id":"https://openalex.org/keywords/transistor","display_name":"Transistor","score":0.11827525496482849},{"id":"https://openalex.org/keywords/telecommunications","display_name":"Telecommunications","score":0.09768721461296082}],"concepts":[{"id":"https://openalex.org/C7366592","wikidata":"https://www.wikidata.org/wiki/Q1255620","display_name":"Dram","level":2,"score":0.6073664426803589},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.5876715779304504},{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.5172329545021057},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.48012804985046387},{"id":"https://openalex.org/C185177783","wikidata":"https://www.wikidata.org/wiki/Q3332814","display_name":"Megabit","level":2,"score":0.46739205718040466},{"id":"https://openalex.org/C2779602883","wikidata":"https://www.wikidata.org/wiki/Q15544750","display_name":"Memory architecture","level":2,"score":0.45570099353790283},{"id":"https://openalex.org/C163258240","wikidata":"https://www.wikidata.org/wiki/Q25342","display_name":"Power (physics)","level":2,"score":0.45294779539108276},{"id":"https://openalex.org/C2776638159","wikidata":"https://www.wikidata.org/wiki/Q18343761","display_name":"Memory cell","level":4,"score":0.4441296458244324},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.43557676672935486},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.3708978295326233},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.32511889934539795},{"id":"https://openalex.org/C121332964","wikidata":"https://www.wikidata.org/wiki/Q413","display_name":"Physics","level":0,"score":0.20104637742042542},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.18906521797180176},{"id":"https://openalex.org/C172385210","wikidata":"https://www.wikidata.org/wiki/Q5339","display_name":"Transistor","level":3,"score":0.11827525496482849},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.09768721461296082},{"id":"https://openalex.org/C62520636","wikidata":"https://www.wikidata.org/wiki/Q944","display_name":"Quantum mechanics","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/tcsi.2014.2334791","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tcsi.2014.2334791","pdf_url":null,"source":{"id":"https://openalex.org/S116977442","display_name":"IEEE Transactions on Circuits and Systems I Regular Papers","issn_l":"1549-8328","issn":["1549-8328","1558-0806"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Circuits and Systems I: Regular Papers","raw_type":"journal-article"}],"best_oa_location":null,"sustainable_development_goals":[{"score":0.7599999904632568,"id":"https://metadata.un.org/sdg/7","display_name":"Affordable and clean energy"}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":10,"referenced_works":["https://openalex.org/W2002293402","https://openalex.org/W2082055514","https://openalex.org/W2084514439","https://openalex.org/W2096417874","https://openalex.org/W2108281294","https://openalex.org/W2131434692","https://openalex.org/W2140281076","https://openalex.org/W2501878154","https://openalex.org/W6671281726","https://openalex.org/W6679139576"],"related_works":["https://openalex.org/W2155719671","https://openalex.org/W3148726441","https://openalex.org/W2138592424","https://openalex.org/W2469229085","https://openalex.org/W2542548909","https://openalex.org/W1983214964","https://openalex.org/W2467408428","https://openalex.org/W2082547827","https://openalex.org/W1552191932","https://openalex.org/W2154754646"],"abstract_inverted_index":{"The":[0,15,37,52,121],"architecture":[1,90,169],"in":[2,56,88,103,136,144,161],"this":[3,89],"work":[4],"uses":[5],"a":[6,92,118,173],"logic-compatible":[7],"CMOS":[8,108],"process":[9,30],"particularly":[10],"suitable":[11],"for":[12,67],"embedded":[13],"applications.":[14],"differential":[16],"pair":[17],"construct":[18],"causes":[19],"the":[20,33,42,68,81,104,159,162,165],"read":[21,43,50,69],"and":[22,61,130,139],"refresh":[23,154,174],"power":[24,155,175],"to":[25,47],"be":[26],"independent":[27],"of":[28,84],"any":[29,182],"parameter":[31],"including":[32],"within-die":[34],"threshold":[35,85],"voltage.":[36],"current":[38],"stop":[39],"feature":[40],"keeps":[41],"voltage":[44,86],"transition":[45],"low":[46],"further":[48],"minimize":[49],"power.":[51],"bit":[53,59,74,98,167],"cell":[54,75,99,168],"operates":[55],"both":[57],"single":[58],"BASE2":[60,137],"multi-bit":[62],"BASE4":[63,145],"modes.":[64],"An":[65],"expression":[66],"signal":[70],"was":[71,101,125],"verified":[72],"with":[73,91],"simulations.":[76],"These":[77],"simulations":[78],"also":[79],"compare":[80],"performance":[82],"impact":[83],"variance":[87],"standard":[93],"gain":[94],"cell.":[95],"A":[96],"DRAM":[97],"array":[100],"fabricated":[102],"XFab":[105],"180":[106,147],"nm":[107],"process.":[109],"Measured":[110],"waveforms":[111],"closely":[112],"match":[113],"theoretical":[114],"results":[115],"obtained":[116],"from":[117],"system":[119],"simulation.":[120],"silicon":[122],"retention":[123],"time":[124],"measured":[126],"at":[127,156],"room":[128],"temperature":[129],"is":[131],"greater":[132,140],"than":[133,141,181],"150":[134],"ms":[135,143],"mode":[138],"75":[142],"mode.":[146],"nm,":[148],"25C":[149],"analysis":[150],"predicts":[151],"0.8":[152],"uW/Mbit":[153],"630":[157],"MHz,":[158],"lowest":[160],"literature.":[163],"Further:":[164],"memory":[166],"presented":[170],"here":[171],"has":[172],"delay":[176],"product":[177],"several":[178],"times":[179],"lower":[180],"other":[183],"published":[184],"architecture.":[185]},"counts_by_year":[{"year":2016,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}