{"id":"https://openalex.org/W2048360376","doi":"https://doi.org/10.1109/tcsi.2013.2295028","title":"An Analytical Delay Model for Mechanical Stress Induced Systematic Variability Analysis in Nanoscale Circuit Design","display_name":"An Analytical Delay Model for Mechanical Stress Induced Systematic Variability Analysis in Nanoscale Circuit Design","publication_year":2014,"publication_date":"2014-01-31","ids":{"openalex":"https://openalex.org/W2048360376","doi":"https://doi.org/10.1109/tcsi.2013.2295028","mag":"2048360376"},"language":"en","primary_location":{"id":"doi:10.1109/tcsi.2013.2295028","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tcsi.2013.2295028","pdf_url":null,"source":{"id":"https://openalex.org/S116977442","display_name":"IEEE Transactions on Circuits and Systems I Regular Papers","issn_l":"1549-8328","issn":["1549-8328","1558-0806"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Circuits and Systems I: Regular Papers","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5043959897","display_name":"Naushad Alam","orcid":"https://orcid.org/0000-0002-1636-7080"},"institutions":[{"id":"https://openalex.org/I154851008","display_name":"Indian Institute of Technology Roorkee","ror":"https://ror.org/00582g326","country_code":"IN","type":"education","lineage":["https://openalex.org/I154851008"]}],"countries":["IN"],"is_corresponding":true,"raw_author_name":"Naushad Alam","raw_affiliation_strings":["Microelectronics and VLSI Group, Indian Institute of Technology, Roorkee, India"],"affiliations":[{"raw_affiliation_string":"Microelectronics and VLSI Group, Indian Institute of Technology, Roorkee, India","institution_ids":["https://openalex.org/I154851008"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5031850929","display_name":"Anand Bulusu","orcid":"https://orcid.org/0000-0002-3986-3730"},"institutions":[{"id":"https://openalex.org/I154851008","display_name":"Indian Institute of Technology Roorkee","ror":"https://ror.org/00582g326","country_code":"IN","type":"education","lineage":["https://openalex.org/I154851008"]}],"countries":["IN"],"is_corresponding":false,"raw_author_name":"Bulusu Anand","raw_affiliation_strings":["Microelectronics and VLSI Group, Indian Institute of Technology, Roorkee, India"],"affiliations":[{"raw_affiliation_string":"Microelectronics and VLSI Group, Indian Institute of Technology, Roorkee, India","institution_ids":["https://openalex.org/I154851008"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5064560509","display_name":"Sudeb Dasgupta","orcid":"https://orcid.org/0000-0002-4044-1594"},"institutions":[{"id":"https://openalex.org/I154851008","display_name":"Indian Institute of Technology Roorkee","ror":"https://ror.org/00582g326","country_code":"IN","type":"education","lineage":["https://openalex.org/I154851008"]}],"countries":["IN"],"is_corresponding":false,"raw_author_name":"S. Dasgupta","raw_affiliation_strings":["Microelectronics and VLSI Group, Indian Institute of Technology, Roorkee, India"],"affiliations":[{"raw_affiliation_string":"Microelectronics and VLSI Group, Indian Institute of Technology, Roorkee, India","institution_ids":["https://openalex.org/I154851008"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":3,"corresponding_author_ids":["https://openalex.org/A5043959897"],"corresponding_institution_ids":["https://openalex.org/I154851008"],"apc_list":null,"apc_paid":null,"fwci":0.8373,"has_fulltext":false,"cited_by_count":7,"citation_normalized_percentile":{"value":0.77248507,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":96},"biblio":{"volume":"61","issue":"6","first_page":"1714","last_page":"1726"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10472","display_name":"Semiconductor materials and devices","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10472","display_name":"Semiconductor materials and devices","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10558","display_name":"Advancements in Semiconductor Devices and Circuit Design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T14117","display_name":"Integrated Circuits and Semiconductor Failure Analysis","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/inverter","display_name":"Inverter","score":0.6921327710151672},{"id":"https://openalex.org/keywords/robustness","display_name":"Robustness (evolution)","score":0.6307766437530518},{"id":"https://openalex.org/keywords/cmos","display_name":"CMOS","score":0.5758118629455566},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.5542516112327576},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.49378594756126404},{"id":"https://openalex.org/keywords/transistor","display_name":"Transistor","score":0.4914013147354126},{"id":"https://openalex.org/keywords/nand-gate","display_name":"NAND gate","score":0.4753565490245819},{"id":"https://openalex.org/keywords/circuit-design","display_name":"Circuit design","score":0.4320374131202698},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.3461011052131653},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.24037855863571167},{"id":"https://openalex.org/keywords/voltage","display_name":"Voltage","score":0.20152488350868225},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.1953245997428894}],"concepts":[{"id":"https://openalex.org/C11190779","wikidata":"https://www.wikidata.org/wiki/Q664575","display_name":"Inverter","level":3,"score":0.6921327710151672},{"id":"https://openalex.org/C63479239","wikidata":"https://www.wikidata.org/wiki/Q7353546","display_name":"Robustness (evolution)","level":3,"score":0.6307766437530518},{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.5758118629455566},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.5542516112327576},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.49378594756126404},{"id":"https://openalex.org/C172385210","wikidata":"https://www.wikidata.org/wiki/Q5339","display_name":"Transistor","level":3,"score":0.4914013147354126},{"id":"https://openalex.org/C124296912","wikidata":"https://www.wikidata.org/wiki/Q575178","display_name":"NAND gate","level":3,"score":0.4753565490245819},{"id":"https://openalex.org/C190560348","wikidata":"https://www.wikidata.org/wiki/Q3245116","display_name":"Circuit design","level":2,"score":0.4320374131202698},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.3461011052131653},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.24037855863571167},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.20152488350868225},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.1953245997428894},{"id":"https://openalex.org/C104317684","wikidata":"https://www.wikidata.org/wiki/Q7187","display_name":"Gene","level":2,"score":0.0},{"id":"https://openalex.org/C55493867","wikidata":"https://www.wikidata.org/wiki/Q7094","display_name":"Biochemistry","level":1,"score":0.0},{"id":"https://openalex.org/C185592680","wikidata":"https://www.wikidata.org/wiki/Q2329","display_name":"Chemistry","level":0,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/tcsi.2013.2295028","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tcsi.2013.2295028","pdf_url":null,"source":{"id":"https://openalex.org/S116977442","display_name":"IEEE Transactions on Circuits and Systems I Regular Papers","issn_l":"1549-8328","issn":["1549-8328","1558-0806"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Circuits and Systems I: Regular Papers","raw_type":"journal-article"}],"best_oa_location":null,"sustainable_development_goals":[{"score":0.4300000071525574,"display_name":"Affordable and clean energy","id":"https://metadata.un.org/sdg/7"}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":37,"referenced_works":["https://openalex.org/W1560300163","https://openalex.org/W1987176210","https://openalex.org/W1993164156","https://openalex.org/W1997782294","https://openalex.org/W2015428081","https://openalex.org/W2022972579","https://openalex.org/W2044857102","https://openalex.org/W2055212628","https://openalex.org/W2055510065","https://openalex.org/W2061015558","https://openalex.org/W2064576566","https://openalex.org/W2078481340","https://openalex.org/W2081825298","https://openalex.org/W2088115909","https://openalex.org/W2091881407","https://openalex.org/W2093085569","https://openalex.org/W2093862902","https://openalex.org/W2100272847","https://openalex.org/W2102467527","https://openalex.org/W2104616525","https://openalex.org/W2106314093","https://openalex.org/W2108923470","https://openalex.org/W2109674204","https://openalex.org/W2112184874","https://openalex.org/W2118294059","https://openalex.org/W2128369443","https://openalex.org/W2128613910","https://openalex.org/W2130582063","https://openalex.org/W2138558886","https://openalex.org/W2148720570","https://openalex.org/W2154930846","https://openalex.org/W2159398026","https://openalex.org/W2161300695","https://openalex.org/W2249092350","https://openalex.org/W6670936756","https://openalex.org/W6680481314","https://openalex.org/W6691306134"],"related_works":["https://openalex.org/W98453623","https://openalex.org/W2340624421","https://openalex.org/W3165307257","https://openalex.org/W2515312339","https://openalex.org/W2145098804","https://openalex.org/W4226211266","https://openalex.org/W2991151827","https://openalex.org/W2130440338","https://openalex.org/W1574518580","https://openalex.org/W2791832526"],"abstract_inverted_index":{"Strain":[0],"engineering":[1],"for":[2,78,116],"performance":[3,21,64],"enhancement":[4],"is":[5,37],"an":[6,74],"integral":[7],"part":[8],"of":[9,17,22,34,93],"a":[10],"state-of-the-art":[11],"CMOS":[12,23],"process":[13],"flow.":[14],"However,":[15],"use":[16,33,92],"stressors":[18],"makes":[19],"the":[20,32,91],"devices":[24],"layout":[25],"dependent.":[26],"Performance":[27],"variability":[28,88],"arising":[29],"due":[30,89],"to":[31,40,90],"stressor":[35],"materials":[36],"often":[38],"referred":[39],"as":[41],"Layout":[42],"Dependent":[43],"Effect":[44],"(LDE)":[45],"variability.":[46],"The":[47],"existing":[48],"delay":[49,76,114],"models":[50],"do":[51],"not":[52],"take":[53],"LDE":[54,87],"into":[55,60],"consideration":[56],"and,":[57],"therefore,":[58],"results":[59,107],"unaccounted":[61],"change":[62],"in":[63],"and":[65,82,108,122],"degraded":[66],"design":[67],"robustness.":[68],"In":[69],"this":[70],"paper":[71],"we":[72],"propose":[73],"analytical":[75],"model":[77,101,112],"Inverter,":[79],"2-input":[80],"NAND":[81],"NOR":[83],"gates":[84],"while":[85],"considering":[86],"strain":[94],"engineered":[95],"devices.":[96],"We":[97],"compare":[98],"our":[99,111],"derived":[100],"with":[102],"TCAD":[103],"calibrated":[104],"HSPICE":[105],"simulation":[106],"observe":[109],"that":[110],"estimates":[113],"well":[115],"varying":[117],"transistor":[118],"sizes,":[119],"load":[120],"capacitances":[121],"input":[123],"signal":[124],"transition":[125],"times.":[126]},"counts_by_year":[{"year":2020,"cited_by_count":1},{"year":2018,"cited_by_count":2},{"year":2017,"cited_by_count":1},{"year":2016,"cited_by_count":2},{"year":2015,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}
