{"id":"https://openalex.org/W1991754897","doi":"https://doi.org/10.1109/tcsi.2013.2264690","title":"HAPL: Heterogeneous Array of Programmable Logic Using Selective Mask Patterning","display_name":"HAPL: Heterogeneous Array of Programmable Logic Using Selective Mask Patterning","publication_year":2013,"publication_date":"2013-06-11","ids":{"openalex":"https://openalex.org/W1991754897","doi":"https://doi.org/10.1109/tcsi.2013.2264690","mag":"1991754897"},"language":"en","primary_location":{"id":"doi:10.1109/tcsi.2013.2264690","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tcsi.2013.2264690","pdf_url":null,"source":{"id":"https://openalex.org/S116977442","display_name":"IEEE Transactions on Circuits and Systems I Regular Papers","issn_l":"1549-8328","issn":["1549-8328","1558-0806"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Circuits and Systems I: Regular Papers","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5020011072","display_name":"Youngsoo Shin","orcid":"https://orcid.org/0000-0002-7474-9212"},"institutions":[{"id":"https://openalex.org/I157485424","display_name":"Korea Advanced Institute of Science and Technology","ror":"https://ror.org/05apxxy63","country_code":"KR","type":"education","lineage":["https://openalex.org/I157485424"]}],"countries":["KR"],"is_corresponding":false,"raw_author_name":"Youngsoo Shin","raw_affiliation_strings":["Department of Electrical Engineering, Korea Advanced Institute of Science and Technology, Daejeon, Korea","[Dept. of Electr. Eng., Korea Adv. Inst. of Sci. & Technol., Daejeon, South Korea]"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Electrical Engineering, Korea Advanced Institute of Science and Technology, Daejeon, Korea","institution_ids":["https://openalex.org/I157485424"]},{"raw_affiliation_string":"[Dept. of Electr. Eng., Korea Adv. Inst. of Sci. & Technol., Daejeon, South Korea]","institution_ids":["https://openalex.org/I157485424"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5021863397","display_name":"Insup Shin","orcid":null},"institutions":[{"id":"https://openalex.org/I157485424","display_name":"Korea Advanced Institute of Science and Technology","ror":"https://ror.org/05apxxy63","country_code":"KR","type":"education","lineage":["https://openalex.org/I157485424"]}],"countries":["KR"],"is_corresponding":false,"raw_author_name":"Insup Shin","raw_affiliation_strings":["Department of Electrical Engineering, Korea Advanced Institute of Science and Technology, Daejeon, Korea","[Dept. of Electr. Eng., Korea Adv. Inst. of Sci. & Technol., Daejeon, South Korea]"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Electrical Engineering, Korea Advanced Institute of Science and Technology, Daejeon, Korea","institution_ids":["https://openalex.org/I157485424"]},{"raw_affiliation_string":"[Dept. of Electr. Eng., Korea Adv. Inst. of Sci. & Technol., Daejeon, South Korea]","institution_ids":["https://openalex.org/I157485424"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5069520131","display_name":"Donkyu Baek","orcid":"https://orcid.org/0000-0002-8056-744X"},"institutions":[{"id":"https://openalex.org/I157485424","display_name":"Korea Advanced Institute of Science and Technology","ror":"https://ror.org/05apxxy63","country_code":"KR","type":"education","lineage":["https://openalex.org/I157485424"]}],"countries":["KR"],"is_corresponding":false,"raw_author_name":"Donkyu Baek","raw_affiliation_strings":["Department of Electrical Engineering, Korea Advanced Institute of Science and Technology, Daejeon, Korea","[Dept. of Electr. Eng., Korea Adv. Inst. of Sci. & Technol., Daejeon, South Korea]"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Electrical Engineering, Korea Advanced Institute of Science and Technology, Daejeon, Korea","institution_ids":["https://openalex.org/I157485424"]},{"raw_affiliation_string":"[Dept. of Electr. Eng., Korea Adv. Inst. of Sci. & Technol., Daejeon, South Korea]","institution_ids":["https://openalex.org/I157485424"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5041847927","display_name":"Duck-Hwan Kim","orcid":"https://orcid.org/0000-0002-6494-2182"},"institutions":[{"id":"https://openalex.org/I130701444","display_name":"Georgia Institute of Technology","ror":"https://ror.org/01zkghx44","country_code":"US","type":"education","lineage":["https://openalex.org/I130701444"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Duckhwan Kim","raw_affiliation_strings":["School of Electrical and Computer Engineering, Georgia Institute of Technology, Atlanta, GA, USA","Sch. of Electr. & Comput. Eng.,, Georgia Inst. of Technol., Atlanta, GA, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"School of Electrical and Computer Engineering, Georgia Institute of Technology, Atlanta, GA, USA","institution_ids":["https://openalex.org/I130701444"]},{"raw_affiliation_string":"Sch. of Electr. & Comput. Eng.,, Georgia Inst. of Technol., Atlanta, GA, USA","institution_ids":["https://openalex.org/I130701444"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5108744170","display_name":"Seungwhun Paik","orcid":null},"institutions":[{"id":"https://openalex.org/I1335490905","display_name":"Synopsys (Switzerland)","ror":"https://ror.org/03mb54f81","country_code":"CH","type":"company","lineage":["https://openalex.org/I1335490905","https://openalex.org/I4210088951"]},{"id":"https://openalex.org/I4210088951","display_name":"Synopsys (United States)","ror":"https://ror.org/013by2m91","country_code":"US","type":"company","lineage":["https://openalex.org/I4210088951"]}],"countries":["CH","US"],"is_corresponding":false,"raw_author_name":"Seungwhun Paik","raw_affiliation_strings":["Synopsys Inc., Moundtain, CA, USA","Synopsys Inc., Moundtain View, CA, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Synopsys Inc., Moundtain, CA, USA","institution_ids":["https://openalex.org/I4210088951"]},{"raw_affiliation_string":"Synopsys Inc., Moundtain View, CA, USA","institution_ids":["https://openalex.org/I1335490905"]}]}],"institutions":[],"countries_distinct_count":3,"institutions_distinct_count":5,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":3,"citation_normalized_percentile":{"value":0.06676474,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":90,"max":96},"biblio":{"volume":"61","issue":"1","first_page":"146","last_page":"159"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9993000030517578,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9991999864578247,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/application-specific-integrated-circuit","display_name":"Application-specific integrated circuit","score":0.8625355362892151},{"id":"https://openalex.org/keywords/programmable-logic-device","display_name":"Programmable logic device","score":0.733892560005188},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.637263834476471},{"id":"https://openalex.org/keywords/programmable-array-logic","display_name":"Programmable Array Logic","score":0.5974319577217102},{"id":"https://openalex.org/keywords/routing","display_name":"Routing (electronic design automation)","score":0.5898637771606445},{"id":"https://openalex.org/keywords/programmable-logic-array","display_name":"Programmable logic array","score":0.5088686943054199},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.4625970423221588},{"id":"https://openalex.org/keywords/erasable-programmable-logic-device","display_name":"Erasable programmable logic device","score":0.4616844058036804},{"id":"https://openalex.org/keywords/complex-programmable-logic-device","display_name":"Complex programmable logic device","score":0.43796035647392273},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.4295700490474701},{"id":"https://openalex.org/keywords/logic-synthesis","display_name":"Logic synthesis","score":0.4281395375728607},{"id":"https://openalex.org/keywords/homogeneous","display_name":"Homogeneous","score":0.4180072546005249},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.4066617786884308},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.35302427411079407},{"id":"https://openalex.org/keywords/logic-family","display_name":"Logic family","score":0.29030904173851013},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.16417109966278076},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.0926605761051178}],"concepts":[{"id":"https://openalex.org/C77390884","wikidata":"https://www.wikidata.org/wiki/Q217302","display_name":"Application-specific integrated circuit","level":2,"score":0.8625355362892151},{"id":"https://openalex.org/C206274596","wikidata":"https://www.wikidata.org/wiki/Q1063837","display_name":"Programmable logic device","level":2,"score":0.733892560005188},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.637263834476471},{"id":"https://openalex.org/C113323844","wikidata":"https://www.wikidata.org/wiki/Q1378651","display_name":"Programmable Array Logic","level":5,"score":0.5974319577217102},{"id":"https://openalex.org/C74172769","wikidata":"https://www.wikidata.org/wiki/Q1446839","display_name":"Routing (electronic design automation)","level":2,"score":0.5898637771606445},{"id":"https://openalex.org/C182322920","wikidata":"https://www.wikidata.org/wiki/Q2112217","display_name":"Programmable logic array","level":3,"score":0.5088686943054199},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.4625970423221588},{"id":"https://openalex.org/C110050671","wikidata":"https://www.wikidata.org/wiki/Q1063837","display_name":"Erasable programmable logic device","level":5,"score":0.4616844058036804},{"id":"https://openalex.org/C128315158","wikidata":"https://www.wikidata.org/wiki/Q1063858","display_name":"Complex programmable logic device","level":2,"score":0.43796035647392273},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.4295700490474701},{"id":"https://openalex.org/C157922185","wikidata":"https://www.wikidata.org/wiki/Q173198","display_name":"Logic synthesis","level":3,"score":0.4281395375728607},{"id":"https://openalex.org/C66882249","wikidata":"https://www.wikidata.org/wiki/Q169336","display_name":"Homogeneous","level":2,"score":0.4180072546005249},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.4066617786884308},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.35302427411079407},{"id":"https://openalex.org/C162454741","wikidata":"https://www.wikidata.org/wiki/Q173359","display_name":"Logic family","level":4,"score":0.29030904173851013},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.16417109966278076},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.0926605761051178},{"id":"https://openalex.org/C114614502","wikidata":"https://www.wikidata.org/wiki/Q76592","display_name":"Combinatorics","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/tcsi.2013.2264690","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tcsi.2013.2264690","pdf_url":null,"source":{"id":"https://openalex.org/S116977442","display_name":"IEEE Transactions on Circuits and Systems I Regular Papers","issn_l":"1549-8328","issn":["1549-8328","1558-0806"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Circuits and Systems I: Regular Papers","raw_type":"journal-article"}],"best_oa_location":null,"sustainable_development_goals":[{"score":0.4099999964237213,"id":"https://metadata.un.org/sdg/9","display_name":"Industry, innovation and infrastructure"}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":24,"referenced_works":["https://openalex.org/W1503082651","https://openalex.org/W1977850862","https://openalex.org/W1989882158","https://openalex.org/W2021819509","https://openalex.org/W2028705851","https://openalex.org/W2062221600","https://openalex.org/W2065951698","https://openalex.org/W2097000220","https://openalex.org/W2097774291","https://openalex.org/W2104308620","https://openalex.org/W2116075993","https://openalex.org/W2123815308","https://openalex.org/W2137530134","https://openalex.org/W2139637699","https://openalex.org/W2153580689","https://openalex.org/W2157054705","https://openalex.org/W2157128002","https://openalex.org/W2222512263","https://openalex.org/W2487708677","https://openalex.org/W2534824542","https://openalex.org/W3146873982","https://openalex.org/W6655854877","https://openalex.org/W6675744748","https://openalex.org/W6682909919"],"related_works":["https://openalex.org/W3013792460","https://openalex.org/W1904803855","https://openalex.org/W2376859467","https://openalex.org/W4389045693","https://openalex.org/W2990957507","https://openalex.org/W2374125170","https://openalex.org/W2360552902","https://openalex.org/W1839326631","https://openalex.org/W2169333805","https://openalex.org/W79431907"],"abstract_inverted_index":{"A":[0,192,209],"structured":[1,51,75,154],"ASIC,":[2],"one":[3],"kind":[4,36],"of":[5,11,15,24,37,74,86,89,106,133,146,159,205,223],"programmable":[6,16,147],"logic":[7,17,38,148],"device":[8],"(PLD),":[9],"consists":[10],"a":[12,50,60,83,107,116,152,214],"homogeneous":[13],"array":[14,145],"elements,":[18],"or":[19],"called":[20,120],"tiles.":[21],"The":[22],"architecture":[23],"each":[25,91],"tile":[26,165],"is":[27,45,112,151,196,200],"supposed":[28],"to":[29,65,184],"be":[30,40,98],"very":[31],"general":[32],"so":[33],"that":[34,195,222],"any":[35],"can":[39,97],"implemented":[41],"on":[42,219],"it;":[43],"this":[44,79],"the":[46,70,104,130,143,203],"main":[47],"reason":[48],"why":[49],"ASIC":[52,155,207],"has":[53,162],"an":[54,66,224],"inherently":[55],"limited":[56],"performance,":[57],"together":[58],"with":[59,92,190],"large":[61],"area":[62,199],"requirement":[63],"compared":[64],"ASIC.":[67,76,191,226],"This":[68,111],"balances":[69],"little":[71],"mask":[72,136],"cost":[73,137],"We":[77,128,141],"tilt":[78],"balance":[80],"by":[81,103,115],"introducing":[82],"small":[84],"number":[85],"different":[87,101],"types":[88],"tile,":[90],"its":[93,163,206],"own":[94,164],"architecture,":[95],"which":[96,125,150,156,217],"deployed":[99],"across":[100],"designs":[102],"use":[105],"simple":[108],"blocking":[109],"mask.":[110],"made":[113],"possible":[114],"new":[117,153],"photolithography":[118],"concept":[119],"selectively":[121],"patterned":[122],"masks":[123],"(SPM),":[124],"we":[126],"propose.":[127],"address":[129],"practical":[131],"issues":[132],"SPM,":[134],"including":[135],"and":[138,166,169,175,187],"manufacturing":[139],"time.":[140],"introduce":[142],"heterogeneous":[144],"(HAPL),":[149],"takes":[157],"advantage":[158],"SPM.":[160],"HAPL":[161,186,193,211],"routing":[167],"architectures,":[168],"supporting":[170],"CAD":[171],"tools":[172],"for":[173,198],"packing":[174],"routing.":[176],"Extensive":[177],"experiments":[178],"in":[179],"45-nm":[180],"technology":[181],"are":[182],"used":[183],"assess":[185],"compare":[188],"it":[189],"design":[194,212],"optimized":[197],"about":[201],"twice":[202],"size":[204],"counterpart.":[208],"delay-optimized":[210],"exhibits":[213],"post-layout":[215],"delay":[216],"is,":[218],"average,":[220],"1.35":[221],"equivalent":[225]},"counts_by_year":[{"year":2025,"cited_by_count":2},{"year":2024,"cited_by_count":1}],"updated_date":"2026-06-11T09:08:48.828518","created_date":"2025-10-10T00:00:00"}