{"id":"https://openalex.org/W2088743615","doi":"https://doi.org/10.1109/tcsi.2012.2215696","title":"A 6.0\u201313.5 GHz Alias-Locked Loop Frequency Synthesizer in 130 nm CMOS","display_name":"A 6.0\u201313.5 GHz Alias-Locked Loop Frequency Synthesizer in 130 nm CMOS","publication_year":2012,"publication_date":"2012-10-16","ids":{"openalex":"https://openalex.org/W2088743615","doi":"https://doi.org/10.1109/tcsi.2012.2215696","mag":"2088743615"},"language":"en","primary_location":{"id":"doi:10.1109/tcsi.2012.2215696","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tcsi.2012.2215696","pdf_url":null,"source":{"id":"https://openalex.org/S116977442","display_name":"IEEE Transactions on Circuits and Systems I Regular Papers","issn_l":"1549-8328","issn":["1549-8328","1558-0806"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Circuits and Systems I: Regular Papers","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5111719252","display_name":"Jinghang Liang","orcid":null},"institutions":[{"id":"https://openalex.org/I154425047","display_name":"University of Alberta","ror":"https://ror.org/0160cpw27","country_code":"CA","type":"education","lineage":["https://openalex.org/I154425047"]}],"countries":["CA"],"is_corresponding":true,"raw_author_name":"Jinghang Liang","raw_affiliation_strings":["Department of Electrical and Computer Engineering, University of Alberta, Edmonton, AB, Canada","Dept. of Electr. & Comput. Eng., Univ. of Alberta, Edmonton, AB, Canada#TAB#"],"affiliations":[{"raw_affiliation_string":"Department of Electrical and Computer Engineering, University of Alberta, Edmonton, AB, Canada","institution_ids":["https://openalex.org/I154425047"]},{"raw_affiliation_string":"Dept. of Electr. & Comput. Eng., Univ. of Alberta, Edmonton, AB, Canada#TAB#","institution_ids":["https://openalex.org/I154425047"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5019643741","display_name":"Zhiyin Zhou","orcid":"https://orcid.org/0000-0003-4013-8162"},"institutions":[{"id":"https://openalex.org/I154425047","display_name":"University of Alberta","ror":"https://ror.org/0160cpw27","country_code":"CA","type":"education","lineage":["https://openalex.org/I154425047"]}],"countries":["CA"],"is_corresponding":false,"raw_author_name":"Zhiyin Zhou","raw_affiliation_strings":["Department of Electrical and Computer Engineering, University of Alberta, Edmonton, AB, Canada","Dept. of Electr. & Comput. Eng., Univ. of Alberta, Edmonton, AB, Canada#TAB#"],"affiliations":[{"raw_affiliation_string":"Department of Electrical and Computer Engineering, University of Alberta, Edmonton, AB, Canada","institution_ids":["https://openalex.org/I154425047"]},{"raw_affiliation_string":"Dept. of Electr. & Comput. Eng., Univ. of Alberta, Edmonton, AB, Canada#TAB#","institution_ids":["https://openalex.org/I154425047"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5005550142","display_name":"Jie Han","orcid":"https://orcid.org/0000-0002-8849-4994"},"institutions":[{"id":"https://openalex.org/I154425047","display_name":"University of Alberta","ror":"https://ror.org/0160cpw27","country_code":"CA","type":"education","lineage":["https://openalex.org/I154425047"]}],"countries":["CA"],"is_corresponding":false,"raw_author_name":"Jie Han","raw_affiliation_strings":["Department of Electrical and Computer Engineering, University of Alberta, Edmonton, AB, Canada","Dept. of Electr. & Comput. Eng., Univ. of Alberta, Edmonton, AB, Canada#TAB#"],"affiliations":[{"raw_affiliation_string":"Department of Electrical and Computer Engineering, University of Alberta, Edmonton, AB, Canada","institution_ids":["https://openalex.org/I154425047"]},{"raw_affiliation_string":"Dept. of Electr. & Comput. Eng., Univ. of Alberta, Edmonton, AB, Canada#TAB#","institution_ids":["https://openalex.org/I154425047"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5066973305","display_name":"D.G. Elliott","orcid":"https://orcid.org/0000-0003-0438-1800"},"institutions":[{"id":"https://openalex.org/I154425047","display_name":"University of Alberta","ror":"https://ror.org/0160cpw27","country_code":"CA","type":"education","lineage":["https://openalex.org/I154425047"]}],"countries":["CA"],"is_corresponding":false,"raw_author_name":"Duncan G. Elliott","raw_affiliation_strings":["Department of Electrical and Computer Engineering, University of Alberta, Edmonton, AB, Canada","Dept. of Electr. & Comput. Eng., Univ. of Alberta, Edmonton, AB, Canada#TAB#"],"affiliations":[{"raw_affiliation_string":"Department of Electrical and Computer Engineering, University of Alberta, Edmonton, AB, Canada","institution_ids":["https://openalex.org/I154425047"]},{"raw_affiliation_string":"Dept. of Electr. & Comput. Eng., Univ. of Alberta, Edmonton, AB, Canada#TAB#","institution_ids":["https://openalex.org/I154425047"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":4,"corresponding_author_ids":["https://openalex.org/A5111719252"],"corresponding_institution_ids":["https://openalex.org/I154425047"],"apc_list":null,"apc_paid":null,"fwci":1.473,"has_fulltext":false,"cited_by_count":14,"citation_normalized_percentile":{"value":0.84190504,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":98},"biblio":{"volume":"60","issue":"1","first_page":"108","last_page":"115"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11417","display_name":"Advancements in PLL and VCO Technologies","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11417","display_name":"Advancements in PLL and VCO Technologies","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10187","display_name":"Radio Frequency Integrated Circuit Design","score":0.9979000091552734,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10323","display_name":"Analog and Mixed-Signal Circuit Design","score":0.9936000108718872,"subfield":{"id":"https://openalex.org/subfields/2204","display_name":"Biomedical Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/frequency-divider","display_name":"Frequency divider","score":0.7803390026092529},{"id":"https://openalex.org/keywords/phase-locked-loop","display_name":"Phase-locked loop","score":0.6336121559143066},{"id":"https://openalex.org/keywords/cmos","display_name":"CMOS","score":0.6288599967956543},{"id":"https://openalex.org/keywords/frequency-synthesizer","display_name":"Frequency synthesizer","score":0.5979135632514954},{"id":"https://openalex.org/keywords/ring-oscillator","display_name":"Ring oscillator","score":0.5506073832511902},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.5086232423782349},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.4953855276107788},{"id":"https://openalex.org/keywords/alias","display_name":"Alias","score":0.4925881028175354},{"id":"https://openalex.org/keywords/loop","display_name":"Loop (graph theory)","score":0.4311996102333069},{"id":"https://openalex.org/keywords/aliasing","display_name":"Aliasing","score":0.4269216060638428},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.42301174998283386},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.3170210123062134},{"id":"https://openalex.org/keywords/phase-noise","display_name":"Phase noise","score":0.20989274978637695},{"id":"https://openalex.org/keywords/filter","display_name":"Filter (signal processing)","score":0.19714781641960144},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.12939199805259705}],"concepts":[{"id":"https://openalex.org/C74982907","wikidata":"https://www.wikidata.org/wiki/Q1455624","display_name":"Frequency divider","level":3,"score":0.7803390026092529},{"id":"https://openalex.org/C12707504","wikidata":"https://www.wikidata.org/wiki/Q52637","display_name":"Phase-locked loop","level":3,"score":0.6336121559143066},{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.6288599967956543},{"id":"https://openalex.org/C182099602","wikidata":"https://www.wikidata.org/wiki/Q2660678","display_name":"Frequency synthesizer","level":4,"score":0.5979135632514954},{"id":"https://openalex.org/C104111718","wikidata":"https://www.wikidata.org/wiki/Q2153973","display_name":"Ring oscillator","level":3,"score":0.5506073832511902},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.5086232423782349},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.4953855276107788},{"id":"https://openalex.org/C46681722","wikidata":"https://www.wikidata.org/wiki/Q4725589","display_name":"Alias","level":2,"score":0.4925881028175354},{"id":"https://openalex.org/C184670325","wikidata":"https://www.wikidata.org/wiki/Q512604","display_name":"Loop (graph theory)","level":2,"score":0.4311996102333069},{"id":"https://openalex.org/C4069607","wikidata":"https://www.wikidata.org/wiki/Q868732","display_name":"Aliasing","level":3,"score":0.4269216060638428},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.42301174998283386},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.3170210123062134},{"id":"https://openalex.org/C89631360","wikidata":"https://www.wikidata.org/wiki/Q1428766","display_name":"Phase noise","level":2,"score":0.20989274978637695},{"id":"https://openalex.org/C106131492","wikidata":"https://www.wikidata.org/wiki/Q3072260","display_name":"Filter (signal processing)","level":2,"score":0.19714781641960144},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.12939199805259705},{"id":"https://openalex.org/C114614502","wikidata":"https://www.wikidata.org/wiki/Q76592","display_name":"Combinatorics","level":1,"score":0.0},{"id":"https://openalex.org/C77088390","wikidata":"https://www.wikidata.org/wiki/Q8513","display_name":"Database","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/tcsi.2012.2215696","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tcsi.2012.2215696","pdf_url":null,"source":{"id":"https://openalex.org/S116977442","display_name":"IEEE Transactions on Circuits and Systems I Regular Papers","issn_l":"1549-8328","issn":["1549-8328","1558-0806"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Circuits and Systems I: Regular Papers","raw_type":"journal-article"}],"best_oa_location":null,"sustainable_development_goals":[{"display_name":"Affordable and clean energy","id":"https://metadata.un.org/sdg/7","score":0.8399999737739563}],"awards":[],"funders":[{"id":"https://openalex.org/F4320322392","display_name":"Tsinghua University","ror":"https://ror.org/03cve4549"},{"id":"https://openalex.org/F4320324852","display_name":"Nanjing University","ror":"https://ror.org/01rxvg760"}],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":15,"referenced_works":["https://openalex.org/W1500201982","https://openalex.org/W1677884181","https://openalex.org/W1980301043","https://openalex.org/W1994625839","https://openalex.org/W2029938543","https://openalex.org/W2053503063","https://openalex.org/W2085732029","https://openalex.org/W2105014900","https://openalex.org/W2109769819","https://openalex.org/W2113500612","https://openalex.org/W2116417852","https://openalex.org/W2135441328","https://openalex.org/W2164002677","https://openalex.org/W6645128165","https://openalex.org/W6657965889"],"related_works":["https://openalex.org/W1504255744","https://openalex.org/W2156709612","https://openalex.org/W2787928226","https://openalex.org/W2044306001","https://openalex.org/W1526852205","https://openalex.org/W183731308","https://openalex.org/W2375805238","https://openalex.org/W2088484122","https://openalex.org/W2087544024","https://openalex.org/W1971788493"],"abstract_inverted_index":{"A":[0],"6.0-13.5":[1],"GHz":[2,104],"alias-locked":[3],"loop":[4],"(ALL)":[5],"frequency":[6,29,55,71,81],"synthesizer":[7],"is":[8,58],"designed":[9],"and":[10,64,82,98],"simulated":[11],"in":[12,43],"130":[13],"nm":[14],"CMOS.":[15],"Using":[16],"an":[17],"aliasing":[18],"divider,":[19],"the":[20,44,92,95],"ALL":[21],"architecture":[22,52],"makes":[23],"it":[24],"possible":[25],"to":[26],"create":[27],"high-speed":[28],"synthesis":[30],"circuits":[31],"without":[32],"relying":[33],"on":[34],"a":[35,50,61,78,83,106],"traditional":[36],"divider":[37],"clocked":[38],"at":[39],"<i":[40],"xmlns:mml=\"http://www.w3.org/1998/Math/MathML\"":[41],"xmlns:xlink=\"http://www.w3.org/1999/xlink\">fVCO</i>":[42],"feedback":[45],"path.":[46],"In":[47],"this":[48],"implementation,":[49],"new":[51],"of":[53,67],"high":[54,79],"ring":[56,74],"oscillator":[57,75],"proposed":[59],"with":[60,105],"feedforward":[62],"path":[63],"selectable":[65],"modes":[66],"operation":[68],"for":[69],"different":[70],"ranges.":[72],"This":[73],"provides":[76],"both":[77],"oscillating":[80],"wide":[84],"tuning":[85],"range.":[86],"Simulation":[87],"results":[88],"have":[89],"shown":[90],"that":[91],"design":[93],"synthesizes":[94],"desired":[96],"frequencies":[97],"consumes":[99],"30.01":[100],"mW":[101],"@":[102],"13.0":[103],"1.2":[107],"V":[108],"power":[109],"supply.":[110]},"counts_by_year":[{"year":2024,"cited_by_count":1},{"year":2021,"cited_by_count":2},{"year":2018,"cited_by_count":1},{"year":2017,"cited_by_count":1},{"year":2016,"cited_by_count":3},{"year":2015,"cited_by_count":5},{"year":2013,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}
