{"id":"https://openalex.org/W2139582289","doi":"https://doi.org/10.1109/tcsi.2012.2190677","title":"Integer-N PLLs Verification Methodology: Large Signal Steady State and Noise Analysis","display_name":"Integer-N PLLs Verification Methodology: Large Signal Steady State and Noise Analysis","publication_year":2012,"publication_date":"2012-04-16","ids":{"openalex":"https://openalex.org/W2139582289","doi":"https://doi.org/10.1109/tcsi.2012.2190677","mag":"2139582289"},"language":"en","primary_location":{"id":"doi:10.1109/tcsi.2012.2190677","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tcsi.2012.2190677","pdf_url":null,"source":{"id":"https://openalex.org/S116977442","display_name":"IEEE Transactions on Circuits and Systems I Regular Papers","issn_l":"1549-8328","issn":["1549-8328","1558-0806"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Circuits and Systems I: Regular Papers","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5100408002","display_name":"Bo Wang","orcid":"https://orcid.org/0000-0001-7257-0684"},"institutions":[{"id":"https://openalex.org/I20231570","display_name":"Peking University","ror":"https://ror.org/02v51f717","country_code":"CN","type":"education","lineage":["https://openalex.org/I20231570"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Bo Wang","raw_affiliation_strings":["The Key Laboratory of Integrated Microsystems, Shenzhen Graduate School of Peking University, Shenzhen, China","Shenzhen Grad. Sch., Key Lab. of Integrated Microsyst., Peking Univ., Shenzhen, China"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"The Key Laboratory of Integrated Microsystems, Shenzhen Graduate School of Peking University, Shenzhen, China","institution_ids":["https://openalex.org/I20231570"]},{"raw_affiliation_string":"Shenzhen Grad. Sch., Key Lab. of Integrated Microsyst., Peking Univ., Shenzhen, China","institution_ids":["https://openalex.org/I20231570"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5009834903","display_name":"Edouard Ngoya","orcid":null},"institutions":[{"id":"https://openalex.org/I1294671590","display_name":"Centre National de la Recherche Scientifique","ror":"https://ror.org/02feahw73","country_code":"FR","type":"government","lineage":["https://openalex.org/I1294671590"]},{"id":"https://openalex.org/I65806277","display_name":"Universit\u00e9 de Limoges","ror":"https://ror.org/02cp04407","country_code":"FR","type":"education","lineage":["https://openalex.org/I65806277"]}],"countries":["FR"],"is_corresponding":false,"raw_author_name":"Edouard Ngoya","raw_affiliation_strings":["XLIM, UMR-CNRS 6172, University of Limoges, Limoges, France","XLIM - University of Limoges - Limoges, France"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"XLIM, UMR-CNRS 6172, University of Limoges, Limoges, France","institution_ids":["https://openalex.org/I65806277","https://openalex.org/I1294671590"]},{"raw_affiliation_string":"XLIM - University of Limoges - Limoges, France","institution_ids":["https://openalex.org/I65806277"]}]}],"institutions":[],"countries_distinct_count":2,"institutions_distinct_count":2,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":0.2498,"has_fulltext":false,"cited_by_count":4,"citation_normalized_percentile":{"value":0.6297395,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":90,"max":97},"biblio":{"volume":"59","issue":"11","first_page":"2738","last_page":"2748"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11417","display_name":"Advancements in PLL and VCO Technologies","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11417","display_name":"Advancements in PLL and VCO Technologies","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10187","display_name":"Radio Frequency Integrated Circuit Design","score":0.9995999932289124,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11444","display_name":"Electromagnetic Compatibility and Noise Suppression","score":0.9991000294685364,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/phase-locked-loop","display_name":"Phase-locked loop","score":0.8879414796829224},{"id":"https://openalex.org/keywords/rfic","display_name":"RFIC","score":0.7965423464775085},{"id":"https://openalex.org/keywords/noise","display_name":"Noise (video)","score":0.5840005874633789},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.5748562812805176},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.5503135323524475},{"id":"https://openalex.org/keywords/integer","display_name":"Integer (computer science)","score":0.543129026889801},{"id":"https://openalex.org/keywords/phase-noise","display_name":"Phase noise","score":0.5194496512413025},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.30660754442214966},{"id":"https://openalex.org/keywords/cmos","display_name":"CMOS","score":0.17740550637245178}],"concepts":[{"id":"https://openalex.org/C12707504","wikidata":"https://www.wikidata.org/wiki/Q52637","display_name":"Phase-locked loop","level":3,"score":0.8879414796829224},{"id":"https://openalex.org/C121152627","wikidata":"https://www.wikidata.org/wiki/Q6095735","display_name":"RFIC","level":3,"score":0.7965423464775085},{"id":"https://openalex.org/C99498987","wikidata":"https://www.wikidata.org/wiki/Q2210247","display_name":"Noise (video)","level":3,"score":0.5840005874633789},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.5748562812805176},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.5503135323524475},{"id":"https://openalex.org/C97137487","wikidata":"https://www.wikidata.org/wiki/Q729138","display_name":"Integer (computer science)","level":2,"score":0.543129026889801},{"id":"https://openalex.org/C89631360","wikidata":"https://www.wikidata.org/wiki/Q1428766","display_name":"Phase noise","level":2,"score":0.5194496512413025},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.30660754442214966},{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.17740550637245178},{"id":"https://openalex.org/C154945302","wikidata":"https://www.wikidata.org/wiki/Q11660","display_name":"Artificial intelligence","level":1,"score":0.0},{"id":"https://openalex.org/C115961682","wikidata":"https://www.wikidata.org/wiki/Q860623","display_name":"Image (mathematics)","level":2,"score":0.0},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.0}],"mesh":[],"locations_count":2,"locations":[{"id":"doi:10.1109/tcsi.2012.2190677","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tcsi.2012.2190677","pdf_url":null,"source":{"id":"https://openalex.org/S116977442","display_name":"IEEE Transactions on Circuits and Systems I Regular Papers","issn_l":"1549-8328","issn":["1549-8328","1558-0806"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Circuits and Systems I: Regular Papers","raw_type":"journal-article"},{"id":"pmh:oai:HAL:hal-00921679v1","is_oa":false,"landing_page_url":"https://unilim.hal.science/hal-00921679","pdf_url":null,"source":{"id":"https://openalex.org/S4306402512","display_name":"HAL (Le Centre pour la Communication Scientifique Directe)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I1294671590","host_organization_name":"Centre National de la Recherche Scientifique","host_organization_lineage":["https://openalex.org/I1294671590"],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"IEEE Transactions on Circuits and Systems Part 1 Fundamental Theory and Applications, 2012, 59 (11), pp. 2738 - 2748. ⟨10.1109/TCSI.2012.2190677⟩","raw_type":"Journal articles"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":18,"referenced_works":["https://openalex.org/W1500373038","https://openalex.org/W1775840686","https://openalex.org/W1998752433","https://openalex.org/W2033874189","https://openalex.org/W2099126831","https://openalex.org/W2102302415","https://openalex.org/W2104147443","https://openalex.org/W2111079473","https://openalex.org/W2124729073","https://openalex.org/W2127567917","https://openalex.org/W2153267648","https://openalex.org/W2160797709","https://openalex.org/W2161865343","https://openalex.org/W2165639899","https://openalex.org/W2167168835","https://openalex.org/W2172110286","https://openalex.org/W2892151252","https://openalex.org/W6684481982"],"related_works":["https://openalex.org/W2358678416","https://openalex.org/W2474043983","https://openalex.org/W2566880546","https://openalex.org/W2078513307","https://openalex.org/W2544336511","https://openalex.org/W2144737022","https://openalex.org/W2000633969","https://openalex.org/W1978186604","https://openalex.org/W2884743660","https://openalex.org/W4289752806"],"abstract_inverted_index":{"The":[0],"need":[1],"for":[2,30,108,120,128],"accurate":[3],"and":[4,35,44,51,95,114],"fast":[5],"verification":[6],"of":[7,58,101],"the":[8,20,56,70,81,85,109,121,129],"phase":[9,36,122],"locked":[10],"loop":[11],"(PLL)":[12],"circuits":[13],"is":[14,42,48,99],"a":[15,104,115],"designers'":[16],"important":[17],"concern":[18],"before":[19],"chip":[21],"tape-out.":[22],"This":[23],"paper":[24],"covers":[25],"two":[26,102],"major":[27],"PLL":[28,133],"characteristics":[29,79],"circuit":[31,64],"verification:":[32],"steady-state":[33],"response":[34,112],"noise.":[37],"A":[38],"new":[39,71],"simulation":[40,66,89],"methodology":[41],"proposed":[43],"comprehensively":[45],"described.":[46],"It":[47,98],"general":[49],"purpose":[50],"can":[52],"be":[53],"implemented":[54],"within":[55],"framework":[57],"all":[59,132],"commercial":[60],"radio":[61],"frequency":[62],"integrated":[63],"(RFIC)":[65],"tools.":[67],"By":[68],"using":[69],"algorithm,":[72],"we":[73],"succeed":[74],"in":[75,131],"predicting":[76],"integer-N":[77],"PLL's":[78],"with":[80],"same":[82],"precision":[83],"as":[84],"conventional":[86],"brute-force":[87],"transistor-level":[88],"while":[90],"spending":[91],"much":[92],"less":[93],"time":[94],"computer":[96],"memory.":[97],"composed":[100],"stages,":[103],"hierarchical":[105],"analysis":[106,124],"algorithm":[107],"steady":[110],"state":[111],"calculation":[113],"bottom-up":[116],"behavioral":[117],"modeling":[118],"strategy":[119],"noise":[123],"that":[125],"accurately":[126],"accounts":[127],"non-idealities":[130],"blocks.":[134]},"counts_by_year":[{"year":2016,"cited_by_count":3},{"year":2013,"cited_by_count":1}],"updated_date":"2026-06-11T09:08:48.828518","created_date":"2025-10-10T00:00:00"}