{"id":"https://openalex.org/W2057240801","doi":"https://doi.org/10.1109/tcsi.2011.2180453","title":"A DLL With Dual Edge Triggered Phase Detector for Fast Lock and Low Jitter Clock Generator","display_name":"A DLL With Dual Edge Triggered Phase Detector for Fast Lock and Low Jitter Clock Generator","publication_year":2012,"publication_date":"2012-01-12","ids":{"openalex":"https://openalex.org/W2057240801","doi":"https://doi.org/10.1109/tcsi.2011.2180453","mag":"2057240801"},"language":"en","primary_location":{"id":"doi:10.1109/tcsi.2011.2180453","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tcsi.2011.2180453","pdf_url":null,"source":{"id":"https://openalex.org/S116977442","display_name":"IEEE Transactions on Circuits and Systems I Regular Papers","issn_l":"1549-8328","issn":["1549-8328","1558-0806"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Circuits and Systems I: Regular Papers","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5084041151","display_name":"Kyungho Ryu","orcid":"https://orcid.org/0000-0002-0354-4797"},"institutions":[{"id":"https://openalex.org/I193775966","display_name":"Yonsei University","ror":"https://ror.org/01wjejq96","country_code":"KR","type":"education","lineage":["https://openalex.org/I193775966"]}],"countries":["KR"],"is_corresponding":false,"raw_author_name":"Kyungho Ryu","raw_affiliation_strings":["School of Electrical and Electronic Engineering, Yonsei University, Seoul, South Korea","[Sch. of Electr. & Electron. Eng., Yonsei Univ., Seoul, South Korea]"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"School of Electrical and Electronic Engineering, Yonsei University, Seoul, South Korea","institution_ids":["https://openalex.org/I193775966"]},{"raw_affiliation_string":"[Sch. of Electr. & Electron. Eng., Yonsei Univ., Seoul, South Korea]","institution_ids":["https://openalex.org/I193775966"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5109180346","display_name":"Dong\u2010Hoon Jung","orcid":null},"institutions":[{"id":"https://openalex.org/I193775966","display_name":"Yonsei University","ror":"https://ror.org/01wjejq96","country_code":"KR","type":"education","lineage":["https://openalex.org/I193775966"]}],"countries":["KR"],"is_corresponding":false,"raw_author_name":"Dong-Hoon Jung","raw_affiliation_strings":["School of Electrical and Electronic Engineering, Yonsei University, Seoul, South Korea","[Sch. of Electr. & Electron. Eng., Yonsei Univ., Seoul, South Korea]"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"School of Electrical and Electronic Engineering, Yonsei University, Seoul, South Korea","institution_ids":["https://openalex.org/I193775966"]},{"raw_affiliation_string":"[Sch. of Electr. & Electron. Eng., Yonsei Univ., Seoul, South Korea]","institution_ids":["https://openalex.org/I193775966"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5037010076","display_name":"Seong\u2010Ook Jung","orcid":"https://orcid.org/0000-0003-0757-2581"},"institutions":[{"id":"https://openalex.org/I193775966","display_name":"Yonsei University","ror":"https://ror.org/01wjejq96","country_code":"KR","type":"education","lineage":["https://openalex.org/I193775966"]}],"countries":["KR"],"is_corresponding":false,"raw_author_name":"Seong-Ook Jung","raw_affiliation_strings":["School of Electrical and Electronic Engineering, Yonsei University, Seoul, South Korea","[Sch. of Electr. & Electron. Eng., Yonsei Univ., Seoul, South Korea]"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"School of Electrical and Electronic Engineering, Yonsei University, Seoul, South Korea","institution_ids":["https://openalex.org/I193775966"]},{"raw_affiliation_string":"[Sch. of Electr. & Electron. Eng., Yonsei Univ., Seoul, South Korea]","institution_ids":["https://openalex.org/I193775966"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":[],"corresponding_institution_ids":["https://openalex.org/I193775966"],"apc_list":null,"apc_paid":null,"fwci":3.9972,"has_fulltext":false,"cited_by_count":44,"citation_normalized_percentile":{"value":0.94068653,"is_in_top_1_percent":false,"is_in_top_10_percent":true},"cited_by_percentile_year":{"min":90,"max":99},"biblio":{"volume":"59","issue":"9","first_page":"1860","last_page":"1870"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11417","display_name":"Advancements in PLL and VCO Technologies","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11417","display_name":"Advancements in PLL and VCO Technologies","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10323","display_name":"Analog and Mixed-Signal Circuit Design","score":0.9991999864578247,"subfield":{"id":"https://openalex.org/subfields/2204","display_name":"Biomedical Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10472","display_name":"Semiconductor materials and devices","score":0.9991999864578247,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/jitter","display_name":"Jitter","score":0.9030684232711792},{"id":"https://openalex.org/keywords/clock-generator","display_name":"Clock generator","score":0.7267211675643921},{"id":"https://openalex.org/keywords/duty-cycle","display_name":"Duty cycle","score":0.722244143486023},{"id":"https://openalex.org/keywords/detector","display_name":"Detector","score":0.6489099264144897},{"id":"https://openalex.org/keywords/phase-detector","display_name":"Phase detector","score":0.5970080494880676},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.44413551688194275},{"id":"https://openalex.org/keywords/signal-edge","display_name":"Signal edge","score":0.41757112741470337},{"id":"https://openalex.org/keywords/power","display_name":"Power (physics)","score":0.3622187376022339},{"id":"https://openalex.org/keywords/physics","display_name":"Physics","score":0.35927391052246094},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.33517828583717346},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.2804431915283203},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.22521287202835083},{"id":"https://openalex.org/keywords/voltage","display_name":"Voltage","score":0.2175634205341339},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.14250555634498596},{"id":"https://openalex.org/keywords/clock-signal","display_name":"Clock signal","score":0.13637515902519226},{"id":"https://openalex.org/keywords/telecommunications","display_name":"Telecommunications","score":0.07097792625427246},{"id":"https://openalex.org/keywords/digital-signal-processing","display_name":"Digital signal processing","score":0.06853213906288147}],"concepts":[{"id":"https://openalex.org/C134652429","wikidata":"https://www.wikidata.org/wiki/Q1052698","display_name":"Jitter","level":2,"score":0.9030684232711792},{"id":"https://openalex.org/C2778023540","wikidata":"https://www.wikidata.org/wiki/Q2164847","display_name":"Clock generator","level":4,"score":0.7267211675643921},{"id":"https://openalex.org/C199822604","wikidata":"https://www.wikidata.org/wiki/Q557120","display_name":"Duty cycle","level":3,"score":0.722244143486023},{"id":"https://openalex.org/C94915269","wikidata":"https://www.wikidata.org/wiki/Q1834857","display_name":"Detector","level":2,"score":0.6489099264144897},{"id":"https://openalex.org/C110086884","wikidata":"https://www.wikidata.org/wiki/Q2085341","display_name":"Phase detector","level":3,"score":0.5970080494880676},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.44413551688194275},{"id":"https://openalex.org/C117525741","wikidata":"https://www.wikidata.org/wiki/Q775654","display_name":"Signal edge","level":4,"score":0.41757112741470337},{"id":"https://openalex.org/C163258240","wikidata":"https://www.wikidata.org/wiki/Q25342","display_name":"Power (physics)","level":2,"score":0.3622187376022339},{"id":"https://openalex.org/C121332964","wikidata":"https://www.wikidata.org/wiki/Q413","display_name":"Physics","level":0,"score":0.35927391052246094},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.33517828583717346},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.2804431915283203},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.22521287202835083},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.2175634205341339},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.14250555634498596},{"id":"https://openalex.org/C137059387","wikidata":"https://www.wikidata.org/wiki/Q426882","display_name":"Clock signal","level":3,"score":0.13637515902519226},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.07097792625427246},{"id":"https://openalex.org/C84462506","wikidata":"https://www.wikidata.org/wiki/Q173142","display_name":"Digital signal processing","level":2,"score":0.06853213906288147},{"id":"https://openalex.org/C13412647","wikidata":"https://www.wikidata.org/wiki/Q174948","display_name":"Analog signal","level":3,"score":0.0},{"id":"https://openalex.org/C62520636","wikidata":"https://www.wikidata.org/wiki/Q944","display_name":"Quantum mechanics","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/tcsi.2011.2180453","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tcsi.2011.2180453","pdf_url":null,"source":{"id":"https://openalex.org/S116977442","display_name":"IEEE Transactions on Circuits and Systems I Regular Papers","issn_l":"1549-8328","issn":["1549-8328","1558-0806"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Circuits and Systems I: Regular Papers","raw_type":"journal-article"}],"best_oa_location":null,"sustainable_development_goals":[{"score":0.8799999952316284,"display_name":"Affordable and clean energy","id":"https://metadata.un.org/sdg/7"}],"awards":[],"funders":[{"id":"https://openalex.org/F4320322202","display_name":"IC Design Education Center","ror":"https://ror.org/005v57z85"}],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":23,"referenced_works":["https://openalex.org/W1527137186","https://openalex.org/W1985636967","https://openalex.org/W1993107416","https://openalex.org/W1997549152","https://openalex.org/W2034433683","https://openalex.org/W2039706313","https://openalex.org/W2050310926","https://openalex.org/W2057240801","https://openalex.org/W2065318410","https://openalex.org/W2098302131","https://openalex.org/W2098317737","https://openalex.org/W2103628070","https://openalex.org/W2115448026","https://openalex.org/W2118131649","https://openalex.org/W2126244313","https://openalex.org/W2132604329","https://openalex.org/W2133079932","https://openalex.org/W2134067926","https://openalex.org/W2137378553","https://openalex.org/W2143232235","https://openalex.org/W2161139924","https://openalex.org/W2163751571","https://openalex.org/W2587442922"],"related_works":["https://openalex.org/W2369998856","https://openalex.org/W114500912","https://openalex.org/W1969806930","https://openalex.org/W2002107209","https://openalex.org/W2141337820","https://openalex.org/W4238211836","https://openalex.org/W25960601","https://openalex.org/W3120154297","https://openalex.org/W2163751571","https://openalex.org/W2152364944"],"abstract_inverted_index":{"A":[0],"DLL":[1,22,37,99,104,129,133,173],"based":[2,38,174],"on":[3,39,175],"a":[4,14,24,40,53,151],"dual":[5],"edge":[6,110],"triggered":[7,42],"phase":[8,43,59,82],"detector":[9,44,60],"(DET-PD)":[10],"is":[11,134,164],"proposed":[12,21,47,70,116,132],"for":[13],"clock":[15],"generator":[16],"in":[17,80],"low-power":[18],"systems.":[19],"The":[20,46,131],"has":[23,141],"faster":[25,168],"lock":[26,162],"speed":[27,163],"with":[28,63],"the":[29,35,50,64,69,78,81,85,89,98,103,108,115,122,128,172,176,180],"same":[30],"loop":[31],"dynamics":[32],"compared":[33],"to":[34,88,101],"conventional":[36,65],"single-edge":[41],"(SET-PD).":[45],"DET-PD":[48,90],"solves":[49],"problem":[51],"of":[52,127,144,154,171],"narrow":[54],"capture":[55],"range":[56,126],"or":[57],"low":[58],"gain":[61],"associated":[62],"DET-PD.":[66],"In":[67],"addition,":[68],"duty":[71,93,117,123],"cycle":[72,118,124],"difference":[73,112],"compensation":[74],"circuit":[75],"(DDC)":[76],"prevents":[77],"increase":[79],"offset":[83],"when":[84],"two":[86],"inputs":[87],"have":[91],"different":[92],"cycle.":[94],"It":[95,140],"also":[96],"controls":[97],"bandwidth":[100],"maintain":[102],"jitter":[105],"by":[106],"controlling":[107],"negative":[109],"delay":[111],"tracking.":[113],"Finally,":[114],"keeper":[119],"(DCK)":[120],"enlarges":[121],"keeping":[125],"output.":[130],"fabricated":[135],"using":[136],"0.18-\u03bcm":[137],"process":[138],"technology.":[139],"an":[142],"area":[143],"0.035":[145],"mm":[146],"<sup":[147],"xmlns:mml=\"http://www.w3.org/1998/Math/MathML\"":[148],"xmlns:xlink=\"http://www.w3.org/1999/xlink\">2</sup>":[149],"and":[150],"power":[152],"consumption":[153],"19":[155],"mW":[156],"at":[157],"800":[158],"MHz":[159],"operation.":[160],"Its":[161],"over":[165],"1.9":[166],"times":[167],"than":[169],"that":[170],"SET-PD":[177],"without":[178],"degrading":[179],"jitter.":[181]},"counts_by_year":[{"year":2025,"cited_by_count":1},{"year":2024,"cited_by_count":4},{"year":2023,"cited_by_count":5},{"year":2022,"cited_by_count":2},{"year":2021,"cited_by_count":2},{"year":2020,"cited_by_count":2},{"year":2019,"cited_by_count":3},{"year":2018,"cited_by_count":5},{"year":2017,"cited_by_count":1},{"year":2016,"cited_by_count":2},{"year":2015,"cited_by_count":2},{"year":2014,"cited_by_count":6},{"year":2013,"cited_by_count":7},{"year":2012,"cited_by_count":1}],"updated_date":"2026-06-26T08:34:08.712188","created_date":"2025-10-10T00:00:00"}