{"id":"https://openalex.org/W2113458531","doi":"https://doi.org/10.1109/tcsi.2009.2030113","title":"Flip-Flop Energy/Performance Versus Clock Slope and Impact on the Clock Network Design","display_name":"Flip-Flop Energy/Performance Versus Clock Slope and Impact on the Clock Network Design","publication_year":2010,"publication_date":"2010-01-08","ids":{"openalex":"https://openalex.org/W2113458531","doi":"https://doi.org/10.1109/tcsi.2009.2030113","mag":"2113458531"},"language":"en","primary_location":{"id":"doi:10.1109/tcsi.2009.2030113","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tcsi.2009.2030113","pdf_url":null,"source":{"id":"https://openalex.org/S116977442","display_name":"IEEE Transactions on Circuits and Systems I Regular Papers","issn_l":"1549-8328","issn":["1549-8328","1558-0806"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Circuits and Systems I: Regular Papers","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5052037141","display_name":"Massimo Alioto","orcid":"https://orcid.org/0000-0002-4127-8258"},"institutions":[{"id":"https://openalex.org/I102064193","display_name":"University of Siena","ror":"https://ror.org/01tevnk56","country_code":"IT","type":"education","lineage":["https://openalex.org/I102064193"]}],"countries":["IT"],"is_corresponding":true,"raw_author_name":"Massimo Alioto","raw_affiliation_strings":["Dipartimento di Ingegneria Informazione (DII), Universit\u00e0 di Siena, Siena, Italy","Dipt. di Ing. dellTnformazione (DII), Univ. di Siena, Siena, Italy"],"affiliations":[{"raw_affiliation_string":"Dipartimento di Ingegneria Informazione (DII), Universit\u00e0 di Siena, Siena, Italy","institution_ids":["https://openalex.org/I102064193"]},{"raw_affiliation_string":"Dipt. di Ing. dellTnformazione (DII), Univ. di Siena, Siena, Italy","institution_ids":["https://openalex.org/I102064193"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5052270052","display_name":"Elio Consoli","orcid":null},"institutions":[{"id":"https://openalex.org/I39063666","display_name":"University of Catania","ror":"https://ror.org/03a64bh57","country_code":"IT","type":"education","lineage":["https://openalex.org/I39063666"]}],"countries":["IT"],"is_corresponding":false,"raw_author_name":"Elio Consoli","raw_affiliation_strings":["Dipartimento di Ingegneria Elettrica, Elettronica e dei Sistemi (DIEES), Universit\u00e0 di Catania, Catania, Italy","Dipt. di Ing. Elettr., Elettron. e dei Sist. (DIEES), Univ. di Catania, Catania, Italy"],"affiliations":[{"raw_affiliation_string":"Dipartimento di Ingegneria Elettrica, Elettronica e dei Sistemi (DIEES), Universit\u00e0 di Catania, Catania, Italy","institution_ids":["https://openalex.org/I39063666"]},{"raw_affiliation_string":"Dipt. di Ing. Elettr., Elettron. e dei Sist. (DIEES), Univ. di Catania, Catania, Italy","institution_ids":["https://openalex.org/I39063666"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5044422028","display_name":"G. Palumbo","orcid":"https://orcid.org/0000-0002-8011-8660"},"institutions":[{"id":"https://openalex.org/I39063666","display_name":"University of Catania","ror":"https://ror.org/03a64bh57","country_code":"IT","type":"education","lineage":["https://openalex.org/I39063666"]}],"countries":["IT"],"is_corresponding":false,"raw_author_name":"Gaetano Palumbo","raw_affiliation_strings":["Dipartimento di Ingegneria Elettrica, Elettronica e dei Sistemi (DIEES), Universit\u00e0 di Catania, Catania, Italy","Dipt. di Ing. Elettr., Elettron. e dei Sist. (DIEES), Univ. di Catania, Catania, Italy"],"affiliations":[{"raw_affiliation_string":"Dipartimento di Ingegneria Elettrica, Elettronica e dei Sistemi (DIEES), Universit\u00e0 di Catania, Catania, Italy","institution_ids":["https://openalex.org/I39063666"]},{"raw_affiliation_string":"Dipt. di Ing. Elettr., Elettron. e dei Sist. (DIEES), Univ. di Catania, Catania, Italy","institution_ids":["https://openalex.org/I39063666"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":3,"corresponding_author_ids":["https://openalex.org/A5052037141"],"corresponding_institution_ids":["https://openalex.org/I102064193"],"apc_list":null,"apc_paid":null,"fwci":7.5047,"has_fulltext":false,"cited_by_count":53,"citation_normalized_percentile":{"value":0.97548046,"is_in_top_1_percent":false,"is_in_top_10_percent":true},"cited_by_percentile_year":{"min":90,"max":99},"biblio":{"volume":"57","issue":"6","first_page":"1273","last_page":"1286"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9991000294685364,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/clock-network","display_name":"Clock network","score":0.6957540512084961},{"id":"https://openalex.org/keywords/jitter","display_name":"Jitter","score":0.6883417963981628},{"id":"https://openalex.org/keywords/clock-skew","display_name":"Clock skew","score":0.68071049451828},{"id":"https://openalex.org/keywords/flops","display_name":"FLOPS","score":0.6705929040908813},{"id":"https://openalex.org/keywords/flip-flop","display_name":"Flip-flop","score":0.6318627595901489},{"id":"https://openalex.org/keywords/skew","display_name":"Skew","score":0.5913280248641968},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.5840204954147339},{"id":"https://openalex.org/keywords/dissipation","display_name":"Dissipation","score":0.5563122630119324},{"id":"https://openalex.org/keywords/cpu-multiplier","display_name":"CPU multiplier","score":0.5122122168540955},{"id":"https://openalex.org/keywords/digital-clock-manager","display_name":"Digital clock manager","score":0.4714720547199249},{"id":"https://openalex.org/keywords/clock-synchronization","display_name":"Clock synchronization","score":0.4678160846233368},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.4519301950931549},{"id":"https://openalex.org/keywords/clock-gating","display_name":"Clock gating","score":0.4436630308628082},{"id":"https://openalex.org/keywords/energy","display_name":"Energy (signal processing)","score":0.4367890954017639},{"id":"https://openalex.org/keywords/clock-domain-crossing","display_name":"Clock domain crossing","score":0.4363937973976135},{"id":"https://openalex.org/keywords/cmos","display_name":"CMOS","score":0.4094211757183075},{"id":"https://openalex.org/keywords/synchronization","display_name":"Synchronization (alternating current)","score":0.27923256158828735},{"id":"https://openalex.org/keywords/synchronous-circuit","display_name":"Synchronous circuit","score":0.26634520292282104},{"id":"https://openalex.org/keywords/clock-signal","display_name":"Clock signal","score":0.24866405129432678},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.24070680141448975},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.1989884376525879},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.18364351987838745},{"id":"https://openalex.org/keywords/channel","display_name":"Channel (broadcasting)","score":0.17862725257873535},{"id":"https://openalex.org/keywords/physics","display_name":"Physics","score":0.10908225178718567},{"id":"https://openalex.org/keywords/telecommunications","display_name":"Telecommunications","score":0.08048054575920105},{"id":"https://openalex.org/keywords/statistics","display_name":"Statistics","score":0.07983878254890442}],"concepts":[{"id":"https://openalex.org/C2778182565","wikidata":"https://www.wikidata.org/wiki/Q1752879","display_name":"Clock network","level":5,"score":0.6957540512084961},{"id":"https://openalex.org/C134652429","wikidata":"https://www.wikidata.org/wiki/Q1052698","display_name":"Jitter","level":2,"score":0.6883417963981628},{"id":"https://openalex.org/C60501442","wikidata":"https://www.wikidata.org/wiki/Q4382014","display_name":"Clock skew","level":4,"score":0.68071049451828},{"id":"https://openalex.org/C3826847","wikidata":"https://www.wikidata.org/wiki/Q188768","display_name":"FLOPS","level":2,"score":0.6705929040908813},{"id":"https://openalex.org/C2781007278","wikidata":"https://www.wikidata.org/wiki/Q183406","display_name":"Flip-flop","level":3,"score":0.6318627595901489},{"id":"https://openalex.org/C43711488","wikidata":"https://www.wikidata.org/wiki/Q7534783","display_name":"Skew","level":2,"score":0.5913280248641968},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.5840204954147339},{"id":"https://openalex.org/C135402231","wikidata":"https://www.wikidata.org/wiki/Q898440","display_name":"Dissipation","level":2,"score":0.5563122630119324},{"id":"https://openalex.org/C125576049","wikidata":"https://www.wikidata.org/wiki/Q2246273","display_name":"CPU multiplier","level":5,"score":0.5122122168540955},{"id":"https://openalex.org/C113074038","wikidata":"https://www.wikidata.org/wiki/Q5276052","display_name":"Digital clock manager","level":5,"score":0.4714720547199249},{"id":"https://openalex.org/C129891060","wikidata":"https://www.wikidata.org/wiki/Q1513059","display_name":"Clock synchronization","level":4,"score":0.4678160846233368},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.4519301950931549},{"id":"https://openalex.org/C22716491","wikidata":"https://www.wikidata.org/wiki/Q590170","display_name":"Clock gating","level":5,"score":0.4436630308628082},{"id":"https://openalex.org/C186370098","wikidata":"https://www.wikidata.org/wiki/Q442787","display_name":"Energy (signal processing)","level":2,"score":0.4367890954017639},{"id":"https://openalex.org/C127204226","wikidata":"https://www.wikidata.org/wiki/Q5134799","display_name":"Clock domain crossing","level":5,"score":0.4363937973976135},{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.4094211757183075},{"id":"https://openalex.org/C2778562939","wikidata":"https://www.wikidata.org/wiki/Q1298791","display_name":"Synchronization (alternating current)","level":3,"score":0.27923256158828735},{"id":"https://openalex.org/C42196554","wikidata":"https://www.wikidata.org/wiki/Q1186179","display_name":"Synchronous circuit","level":4,"score":0.26634520292282104},{"id":"https://openalex.org/C137059387","wikidata":"https://www.wikidata.org/wiki/Q426882","display_name":"Clock signal","level":3,"score":0.24866405129432678},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.24070680141448975},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.1989884376525879},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.18364351987838745},{"id":"https://openalex.org/C127162648","wikidata":"https://www.wikidata.org/wiki/Q16858953","display_name":"Channel (broadcasting)","level":2,"score":0.17862725257873535},{"id":"https://openalex.org/C121332964","wikidata":"https://www.wikidata.org/wiki/Q413","display_name":"Physics","level":0,"score":0.10908225178718567},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.08048054575920105},{"id":"https://openalex.org/C105795698","wikidata":"https://www.wikidata.org/wiki/Q12483","display_name":"Statistics","level":1,"score":0.07983878254890442},{"id":"https://openalex.org/C97355855","wikidata":"https://www.wikidata.org/wiki/Q11473","display_name":"Thermodynamics","level":1,"score":0.0}],"mesh":[],"locations_count":2,"locations":[{"id":"doi:10.1109/tcsi.2009.2030113","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tcsi.2009.2030113","pdf_url":null,"source":{"id":"https://openalex.org/S116977442","display_name":"IEEE Transactions on Circuits and Systems I Regular Papers","issn_l":"1549-8328","issn":["1549-8328","1558-0806"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Circuits and Systems I: Regular Papers","raw_type":"journal-article"},{"id":"pmh:oai:usiena-air.unisi.it:11365/25815","is_oa":false,"landing_page_url":"http://hdl.handle.net/11365/25815","pdf_url":null,"source":{"id":"https://openalex.org/S4377196319","display_name":"Use Siena air (University of Siena)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I102064193","host_organization_name":"University of Siena","host_organization_lineage":["https://openalex.org/I102064193"],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":null,"raw_type":"info:eu-repo/semantics/article"}],"best_oa_location":null,"sustainable_development_goals":[{"id":"https://metadata.un.org/sdg/7","display_name":"Affordable and clean energy","score":0.9100000262260437}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":58,"referenced_works":["https://openalex.org/W63306999","https://openalex.org/W153999141","https://openalex.org/W252582478","https://openalex.org/W270615609","https://openalex.org/W601470542","https://openalex.org/W1483794920","https://openalex.org/W1484135661","https://openalex.org/W1488567546","https://openalex.org/W1527137186","https://openalex.org/W1594033353","https://openalex.org/W1776668917","https://openalex.org/W1826155151","https://openalex.org/W1986907977","https://openalex.org/W1995522027","https://openalex.org/W2056378213","https://openalex.org/W2068316116","https://openalex.org/W2088115909","https://openalex.org/W2097193789","https://openalex.org/W2109195618","https://openalex.org/W2112096506","https://openalex.org/W2118177820","https://openalex.org/W2121694082","https://openalex.org/W2124460294","https://openalex.org/W2125117969","https://openalex.org/W2127639550","https://openalex.org/W2128218350","https://openalex.org/W2128335981","https://openalex.org/W2129458767","https://openalex.org/W2131239505","https://openalex.org/W2133667515","https://openalex.org/W2134890590","https://openalex.org/W2136964362","https://openalex.org/W2137616964","https://openalex.org/W2138724413","https://openalex.org/W2139250338","https://openalex.org/W2148565312","https://openalex.org/W2150547314","https://openalex.org/W2151092072","https://openalex.org/W2157024459","https://openalex.org/W2157465781","https://openalex.org/W2163605226","https://openalex.org/W2164002677","https://openalex.org/W2164209491","https://openalex.org/W2164875860","https://openalex.org/W2171825402","https://openalex.org/W2273929568","https://openalex.org/W3089937351","https://openalex.org/W3103339143","https://openalex.org/W4229627167","https://openalex.org/W4231252248","https://openalex.org/W4236892114","https://openalex.org/W4237189364","https://openalex.org/W4237249613","https://openalex.org/W4239106567","https://openalex.org/W6628733527","https://openalex.org/W6638000668","https://openalex.org/W6678264165","https://openalex.org/W6819126557"],"related_works":["https://openalex.org/W2088914741","https://openalex.org/W4247180033","https://openalex.org/W2559451387","https://openalex.org/W4313332229","https://openalex.org/W2090213929","https://openalex.org/W2165139624","https://openalex.org/W2474747038","https://openalex.org/W3006003651","https://openalex.org/W2137310043","https://openalex.org/W2803012234"],"abstract_inverted_index":{"In":[0],"this":[1],"paper,":[2],"the":[3,6,10,20,43,53,84,93,116,119,136,139],"influence":[4],"of":[5,12,15,24,83,96,100,106,118,121,138],"clock":[7,28,38,48,54,85],"slope":[8,39,55,86],"on":[9,19,127],"speed":[11,78],"various":[13],"classes":[14,95],"flip-flops":[16],"(FFs)":[17],"and":[18,27,73,109,142],"overall":[21],"energy":[22,44,71],"dissipation":[23],"both":[25],"FFs":[26],"domain":[29],"buffers":[30],"is":[31,88,112],"analyzed.":[32],"Analysis":[33],"shows":[34],"that":[35,52],"an":[36,102],"optimum":[37],"exists,":[40],"which":[41],"minimizes":[42],"spent":[45],"in":[46,90,104],"a":[47,75,128],"domain.":[49],"Results":[50],"show":[51],"requirement":[56],"can":[57],"be":[58],"relaxed":[59],"with":[60],"respect":[61],"to":[62,67,115,134],"traditional":[63],"assumptions,":[64],"leading":[65],"up":[66],"30":[68],"\u00f740":[69],"%":[70],"savings":[72],"at":[74],"very":[76],"small":[77],"performance":[79],"penalty.":[80],"The":[81,98],"effectiveness":[82],"optimization":[87,103],"discussed":[89],"detail":[91],"for":[92],"existing":[94],"FFs.":[97],"impact":[99,120],"such":[101],"terms":[105],"additive":[107],"skew":[108],"jitter":[110],"contributions":[111],"discussed,":[113],"together":[114],"analysis":[117],"technology":[122,131],"scaling.":[123],"Extensive":[124],"post-layout":[125],"simulations":[126],"65-nm":[129],"CMOS":[130],"are":[132],"performed":[133],"check":[135],"validity":[137],"underlying":[140],"assumptions":[141],"approximations.":[143]},"counts_by_year":[{"year":2024,"cited_by_count":3},{"year":2022,"cited_by_count":3},{"year":2021,"cited_by_count":3},{"year":2019,"cited_by_count":4},{"year":2018,"cited_by_count":2},{"year":2017,"cited_by_count":2},{"year":2016,"cited_by_count":1},{"year":2015,"cited_by_count":6},{"year":2014,"cited_by_count":3},{"year":2013,"cited_by_count":7},{"year":2012,"cited_by_count":2}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}