{"id":"https://openalex.org/W2100605856","doi":"https://doi.org/10.1109/tcsi.2009.2027799","title":"An Analog-Node Model for VHDL-Based Simulation of RF Integrated Circuits","display_name":"An Analog-Node Model for VHDL-Based Simulation of RF Integrated Circuits","publication_year":2009,"publication_date":"2009-07-15","ids":{"openalex":"https://openalex.org/W2100605856","doi":"https://doi.org/10.1109/tcsi.2009.2027799","mag":"2100605856"},"language":"en","primary_location":{"id":"doi:10.1109/tcsi.2009.2027799","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tcsi.2009.2027799","pdf_url":null,"source":{"id":"https://openalex.org/S116977442","display_name":"IEEE Transactions on Circuits and Systems I Regular Papers","issn_l":"1549-8328","issn":["1549-8328","1558-0806"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Circuits and Systems I: Regular Papers","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5038859625","display_name":"Martin Schubert","orcid":"https://orcid.org/0000-0003-4495-6533"},"institutions":[{"id":"https://openalex.org/I120163777","display_name":"OTH Regensburg","ror":"https://ror.org/04b9vrm74","country_code":"DE","type":"education","lineage":["https://openalex.org/I120163777"]}],"countries":["DE"],"is_corresponding":true,"raw_author_name":"M.J.W. Schubert","raw_affiliation_strings":["Regensburg University of Applied Sciences, Regensburg, Germany","Regensburg Univ. of Appl. Sci., Regensburg, Germany"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Regensburg University of Applied Sciences, Regensburg, Germany","institution_ids":["https://openalex.org/I120163777"]},{"raw_affiliation_string":"Regensburg Univ. of Appl. Sci., Regensburg, Germany","institution_ids":[]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":["https://openalex.org/A5038859625"],"corresponding_institution_ids":["https://openalex.org/I120163777"],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":12,"citation_normalized_percentile":{"value":0.11708159,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":97},"biblio":{"volume":"56","issue":"12","first_page":"2717","last_page":"2727"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10187","display_name":"Radio Frequency Integrated Circuit Design","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10187","display_name":"Radio Frequency Integrated Circuit Design","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T12495","display_name":"Electrostatic Discharge in Electronics","score":0.9990000128746033,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/vhdl","display_name":"VHDL","score":0.7382509708404541},{"id":"https://openalex.org/keywords/node","display_name":"Node (physics)","score":0.6700044870376587},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6139377355575562},{"id":"https://openalex.org/keywords/signal","display_name":"SIGNAL (programming language)","score":0.5572780966758728},{"id":"https://openalex.org/keywords/mixed-signal-integrated-circuit","display_name":"Mixed-signal integrated circuit","score":0.5324094891548157},{"id":"https://openalex.org/keywords/vhdl-ams","display_name":"VHDL-AMS","score":0.5006387233734131},{"id":"https://openalex.org/keywords/electronic-circuit","display_name":"Electronic circuit","score":0.4197833836078644},{"id":"https://openalex.org/keywords/integrated-circuit","display_name":"Integrated circuit","score":0.41456297039985657},{"id":"https://openalex.org/keywords/hardware-description-language","display_name":"Hardware description language","score":0.37617969512939453},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.23713678121566772},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.22858926653862},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.12883320450782776},{"id":"https://openalex.org/keywords/programming-language","display_name":"Programming language","score":0.0922415554523468}],"concepts":[{"id":"https://openalex.org/C36941000","wikidata":"https://www.wikidata.org/wiki/Q209455","display_name":"VHDL","level":3,"score":0.7382509708404541},{"id":"https://openalex.org/C62611344","wikidata":"https://www.wikidata.org/wiki/Q1062658","display_name":"Node (physics)","level":2,"score":0.6700044870376587},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6139377355575562},{"id":"https://openalex.org/C2779843651","wikidata":"https://www.wikidata.org/wiki/Q7390335","display_name":"SIGNAL (programming language)","level":2,"score":0.5572780966758728},{"id":"https://openalex.org/C62907940","wikidata":"https://www.wikidata.org/wiki/Q1541329","display_name":"Mixed-signal integrated circuit","level":3,"score":0.5324094891548157},{"id":"https://openalex.org/C2776513426","wikidata":"https://www.wikidata.org/wiki/Q2744740","display_name":"VHDL-AMS","level":4,"score":0.5006387233734131},{"id":"https://openalex.org/C134146338","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Electronic circuit","level":2,"score":0.4197833836078644},{"id":"https://openalex.org/C530198007","wikidata":"https://www.wikidata.org/wiki/Q80831","display_name":"Integrated circuit","level":2,"score":0.41456297039985657},{"id":"https://openalex.org/C42143788","wikidata":"https://www.wikidata.org/wiki/Q173341","display_name":"Hardware description language","level":3,"score":0.37617969512939453},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.23713678121566772},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.22858926653862},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.12883320450782776},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.0922415554523468},{"id":"https://openalex.org/C66938386","wikidata":"https://www.wikidata.org/wiki/Q633538","display_name":"Structural engineering","level":1,"score":0.0},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.0},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/tcsi.2009.2027799","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tcsi.2009.2027799","pdf_url":null,"source":{"id":"https://openalex.org/S116977442","display_name":"IEEE Transactions on Circuits and Systems I Regular Papers","issn_l":"1549-8328","issn":["1549-8328","1558-0806"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Circuits and Systems I: Regular Papers","raw_type":"journal-article"}],"best_oa_location":null,"sustainable_development_goals":[{"id":"https://metadata.un.org/sdg/16","score":0.5,"display_name":"Peace, Justice and strong institutions"}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":57,"referenced_works":["https://openalex.org/W605564925","https://openalex.org/W1495182304","https://openalex.org/W1925461521","https://openalex.org/W1928957284","https://openalex.org/W1965413459","https://openalex.org/W1966457520","https://openalex.org/W1977246873","https://openalex.org/W1996535435","https://openalex.org/W2003695094","https://openalex.org/W2014795898","https://openalex.org/W2020870047","https://openalex.org/W2054251091","https://openalex.org/W2074245272","https://openalex.org/W2089904582","https://openalex.org/W2098866711","https://openalex.org/W2099428766","https://openalex.org/W2101751538","https://openalex.org/W2103868891","https://openalex.org/W2105379209","https://openalex.org/W2105903359","https://openalex.org/W2106570300","https://openalex.org/W2111152992","https://openalex.org/W2112017015","https://openalex.org/W2113547115","https://openalex.org/W2115959172","https://openalex.org/W2121442313","https://openalex.org/W2126190772","https://openalex.org/W2126790057","https://openalex.org/W2134730059","https://openalex.org/W2135334457","https://openalex.org/W2137339287","https://openalex.org/W2140953980","https://openalex.org/W2143119800","https://openalex.org/W2147630201","https://openalex.org/W2152098049","https://openalex.org/W2154989823","https://openalex.org/W2155705742","https://openalex.org/W2157204690","https://openalex.org/W2160797709","https://openalex.org/W2164286861","https://openalex.org/W2165581685","https://openalex.org/W2165630788","https://openalex.org/W2165759561","https://openalex.org/W2172233479","https://openalex.org/W2304802780","https://openalex.org/W2536248141","https://openalex.org/W3147311224","https://openalex.org/W4234589815","https://openalex.org/W4236013290","https://openalex.org/W4237589244","https://openalex.org/W4242383160","https://openalex.org/W4285719527","https://openalex.org/W4301627548","https://openalex.org/W6649339291","https://openalex.org/W6682765900","https://openalex.org/W6684580518","https://openalex.org/W6698535467"],"related_works":["https://openalex.org/W1586741485","https://openalex.org/W2070083638","https://openalex.org/W2543386576","https://openalex.org/W1576549604","https://openalex.org/W3021694037","https://openalex.org/W2091509145","https://openalex.org/W2096642685","https://openalex.org/W2357636087","https://openalex.org/W2536306358","https://openalex.org/W2129583176"],"abstract_inverted_index":{"This":[0,72],"paper":[1],"describes":[2],"a":[3,43,60,181],"very-high-speed":[4],"integrated-circuit":[5],"hardware":[6],"description":[7],"language":[8],"(VHDL)-based":[9],"analog-node":[10],"model,":[11],"an":[12,64,69,139,175],"associated":[13,140],"driver":[14,141],"component":[15,142],"for":[16],"the":[17,34,74,87,127,178],"mixed-signal":[18,169],"event-driven":[19],"(MixED)":[20],"simulation":[21,52,150,179],"technique,":[22],"and":[23,138,145,158],"some":[24],"primitive":[25],"device":[26],"models":[27],"applied":[28],"to":[29,80,85,147,166,188],"radio-frequency":[30],"integrated":[31],"circuits.":[32],"With":[33],"presented":[35,144],"MixED":[36,55],"method,":[37],"analog":[38,51],"circuits":[39],"are":[40,143,186],"modeled":[41],"as":[42,153],"composition":[44],"of":[45,76,97,126,180],"controlled":[46],"sources.":[47],"Unlike":[48],"other":[49],"VHDL-based":[50],"methods,":[53],"these":[54],"sources":[56,79],"compute":[57],"not":[58],"only":[59],"real":[61],"number":[62],"representing":[63],"output":[65,70],"voltage":[66,96],"but":[67],"also":[68],"impedance.":[71],"allows":[73],"outputs":[75],"several":[77],"MiXED":[78],"be":[81],"connected":[82],"in":[83,117],"order":[84],"drive":[86],"same":[88],"node":[89,128],"signal":[90,100,129],"<i":[91,107,111,130],"xmlns:mml=\"http://www.w3.org/1998/Math/MathML\"":[92,108,112,131],"xmlns:xlink=\"http://www.w3.org/1999/xlink\">n</i>":[93,109,132],".":[94,110],"The":[95,123],"this":[98,172],"record-type":[99],"is":[101],"automatically":[102],"computed":[103],"at":[104],"its":[105,134],"element":[106],"xmlns:xlink=\"http://www.w3.org/1999/xlink\">u</i>":[113],"by":[114],"resolution":[115,136],"functions":[116],"compliance":[118],"with":[119,171,174],"Kirchhoff's":[120],"current":[121,156],"law.":[122],"data":[124],"structure":[125],",":[133],"self-defined":[135],"functions,":[137],"discussed":[146],"meet":[148],"different":[149],"requirements,":[151],"such":[152],"speed,":[154],"versatility,":[155],"accuracy,":[157],"adaptive":[159],"time":[160],"stepping.":[161],"Several":[162],"examples":[163],"demonstrate":[164],"how":[165],"behaviorally":[167],"model":[168],"components":[170],"method":[173],"emphasis":[176],"on":[177],"heterodyne":[182],"receiver.":[183],"Simulation":[184],"speeds":[185],"compared":[187],"VHDL-AMS":[189],"tools.":[190]},"counts_by_year":[{"year":2024,"cited_by_count":1},{"year":2022,"cited_by_count":1},{"year":2021,"cited_by_count":1},{"year":2016,"cited_by_count":3},{"year":2015,"cited_by_count":2},{"year":2014,"cited_by_count":2},{"year":2013,"cited_by_count":2}],"updated_date":"2026-07-22T07:51:19.307946","created_date":"2025-10-10T00:00:00"}