{"id":"https://openalex.org/W2112328125","doi":"https://doi.org/10.1109/tcsi.2009.2023945","title":"Time-to-Digital Converter for Frequency Synthesis Based on a Digital Bang-Bang DLL","display_name":"Time-to-Digital Converter for Frequency Synthesis Based on a Digital Bang-Bang DLL","publication_year":2009,"publication_date":"2009-06-02","ids":{"openalex":"https://openalex.org/W2112328125","doi":"https://doi.org/10.1109/tcsi.2009.2023945","mag":"2112328125"},"language":"en","primary_location":{"id":"doi:10.1109/tcsi.2009.2023945","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tcsi.2009.2023945","pdf_url":null,"source":{"id":"https://openalex.org/S116977442","display_name":"IEEE Transactions on Circuits and Systems I Regular Papers","issn_l":"1549-8328","issn":["1549-8328","1558-0806"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Circuits and Systems I: Regular Papers","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5111978359","display_name":"Marco Zanuso","orcid":null},"institutions":[{"id":"https://openalex.org/I93860229","display_name":"Politecnico di Milano","ror":"https://ror.org/01nffqt88","country_code":"IT","type":"education","lineage":["https://openalex.org/I93860229"]}],"countries":["IT"],"is_corresponding":true,"raw_author_name":"M. Zanuso","raw_affiliation_strings":["Dipartimento di Elettronica e Informazione, Politecnico di Milano, Milan, Italy"],"affiliations":[{"raw_affiliation_string":"Dipartimento di Elettronica e Informazione, Politecnico di Milano, Milan, Italy","institution_ids":["https://openalex.org/I93860229"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5072673563","display_name":"Paolo Madoglio","orcid":"https://orcid.org/0000-0002-6205-9724"},"institutions":[{"id":"https://openalex.org/I93860229","display_name":"Politecnico di Milano","ror":"https://ror.org/01nffqt88","country_code":"IT","type":"education","lineage":["https://openalex.org/I93860229"]},{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["IT","US"],"is_corresponding":false,"raw_author_name":"P. Madoglio","raw_affiliation_strings":["Intel Corporation, Hillsboro, OR, USA","Politecnico di Milano, Milan, Italy"],"affiliations":[{"raw_affiliation_string":"Intel Corporation, Hillsboro, OR, USA","institution_ids":["https://openalex.org/I1343180700"]},{"raw_affiliation_string":"Politecnico di Milano, Milan, Italy","institution_ids":["https://openalex.org/I93860229"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5085904857","display_name":"Salvatore Levantino","orcid":"https://orcid.org/0000-0003-0895-1700"},"institutions":[{"id":"https://openalex.org/I93860229","display_name":"Politecnico di Milano","ror":"https://ror.org/01nffqt88","country_code":"IT","type":"education","lineage":["https://openalex.org/I93860229"]}],"countries":["IT"],"is_corresponding":false,"raw_author_name":"S. Levantino","raw_affiliation_strings":["Dipartimento di Elettronica e Informazione, Politecnico di Milano, Milan, Italy"],"affiliations":[{"raw_affiliation_string":"Dipartimento di Elettronica e Informazione, Politecnico di Milano, Milan, Italy","institution_ids":["https://openalex.org/I93860229"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5073514694","display_name":"Carlo Samori","orcid":"https://orcid.org/0000-0002-7084-0721"},"institutions":[{"id":"https://openalex.org/I93860229","display_name":"Politecnico di Milano","ror":"https://ror.org/01nffqt88","country_code":"IT","type":"education","lineage":["https://openalex.org/I93860229"]}],"countries":["IT"],"is_corresponding":false,"raw_author_name":"C. Samori","raw_affiliation_strings":["Dipartimento di Elettronica e Informazione, Politecnico di Milano, Milan, Italy"],"affiliations":[{"raw_affiliation_string":"Dipartimento di Elettronica e Informazione, Politecnico di Milano, Milan, Italy","institution_ids":["https://openalex.org/I93860229"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5051946676","display_name":"Andrea L. Lacaita","orcid":"https://orcid.org/0000-0003-0315-514X"},"institutions":[{"id":"https://openalex.org/I93860229","display_name":"Politecnico di Milano","ror":"https://ror.org/01nffqt88","country_code":"IT","type":"education","lineage":["https://openalex.org/I93860229"]}],"countries":["IT"],"is_corresponding":false,"raw_author_name":"A.L. Lacaita","raw_affiliation_strings":["Dipartimento di Elettronica e Informazione, Politecnico di Milano, Milan, Italy"],"affiliations":[{"raw_affiliation_string":"Dipartimento di Elettronica e Informazione, Politecnico di Milano, Milan, Italy","institution_ids":["https://openalex.org/I93860229"]}]}],"institutions":[],"countries_distinct_count":2,"institutions_distinct_count":5,"corresponding_author_ids":["https://openalex.org/A5111978359"],"corresponding_institution_ids":["https://openalex.org/I93860229"],"apc_list":null,"apc_paid":null,"fwci":5.6824,"has_fulltext":false,"cited_by_count":62,"citation_normalized_percentile":{"value":0.96246351,"is_in_top_1_percent":false,"is_in_top_10_percent":true},"cited_by_percentile_year":{"min":90,"max":99},"biblio":{"volume":"57","issue":"3","first_page":"548","last_page":"555"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11417","display_name":"Advancements in PLL and VCO Technologies","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11417","display_name":"Advancements in PLL and VCO Technologies","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10187","display_name":"Radio Frequency Integrated Circuit Design","score":0.9976999759674072,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10323","display_name":"Analog and Mixed-Signal Circuit Design","score":0.9965000152587891,"subfield":{"id":"https://openalex.org/subfields/2204","display_name":"Biomedical Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/phase-locked-loop","display_name":"Phase-locked loop","score":0.8144357800483704},{"id":"https://openalex.org/keywords/dbc","display_name":"dBc","score":0.7881710529327393},{"id":"https://openalex.org/keywords/time-to-digital-converter","display_name":"Time-to-digital converter","score":0.5823107957839966},{"id":"https://openalex.org/keywords/cmos","display_name":"CMOS","score":0.5365142226219177},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.5199353098869324},{"id":"https://openalex.org/keywords/chip","display_name":"Chip","score":0.5170519948005676},{"id":"https://openalex.org/keywords/phase-noise","display_name":"Phase noise","score":0.5075267553329468},{"id":"https://openalex.org/keywords/pll-multibit","display_name":"PLL multibit","score":0.4842255115509033},{"id":"https://openalex.org/keywords/lock","display_name":"Lock (firearm)","score":0.4711669385433197},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.469030499458313},{"id":"https://openalex.org/keywords/physics","display_name":"Physics","score":0.36272889375686646},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.3395170569419861},{"id":"https://openalex.org/keywords/jitter","display_name":"Jitter","score":0.24458390474319458},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.23444807529449463},{"id":"https://openalex.org/keywords/telecommunications","display_name":"Telecommunications","score":0.157408207654953},{"id":"https://openalex.org/keywords/clock-signal","display_name":"Clock signal","score":0.15699315071105957}],"concepts":[{"id":"https://openalex.org/C12707504","wikidata":"https://www.wikidata.org/wiki/Q52637","display_name":"Phase-locked loop","level":3,"score":0.8144357800483704},{"id":"https://openalex.org/C193523891","wikidata":"https://www.wikidata.org/wiki/Q1771950","display_name":"dBc","level":3,"score":0.7881710529327393},{"id":"https://openalex.org/C99594498","wikidata":"https://www.wikidata.org/wiki/Q2434524","display_name":"Time-to-digital converter","level":4,"score":0.5823107957839966},{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.5365142226219177},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.5199353098869324},{"id":"https://openalex.org/C165005293","wikidata":"https://www.wikidata.org/wiki/Q1074500","display_name":"Chip","level":2,"score":0.5170519948005676},{"id":"https://openalex.org/C89631360","wikidata":"https://www.wikidata.org/wiki/Q1428766","display_name":"Phase noise","level":2,"score":0.5075267553329468},{"id":"https://openalex.org/C77881186","wikidata":"https://www.wikidata.org/wiki/Q7119642","display_name":"PLL multibit","level":4,"score":0.4842255115509033},{"id":"https://openalex.org/C174839445","wikidata":"https://www.wikidata.org/wiki/Q1134386","display_name":"Lock (firearm)","level":2,"score":0.4711669385433197},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.469030499458313},{"id":"https://openalex.org/C121332964","wikidata":"https://www.wikidata.org/wiki/Q413","display_name":"Physics","level":0,"score":0.36272889375686646},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.3395170569419861},{"id":"https://openalex.org/C134652429","wikidata":"https://www.wikidata.org/wiki/Q1052698","display_name":"Jitter","level":2,"score":0.24458390474319458},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.23444807529449463},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.157408207654953},{"id":"https://openalex.org/C137059387","wikidata":"https://www.wikidata.org/wiki/Q426882","display_name":"Clock signal","level":3,"score":0.15699315071105957},{"id":"https://openalex.org/C78519656","wikidata":"https://www.wikidata.org/wiki/Q101333","display_name":"Mechanical engineering","level":1,"score":0.0}],"mesh":[],"locations_count":2,"locations":[{"id":"doi:10.1109/tcsi.2009.2023945","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tcsi.2009.2023945","pdf_url":null,"source":{"id":"https://openalex.org/S116977442","display_name":"IEEE Transactions on Circuits and Systems I Regular Papers","issn_l":"1549-8328","issn":["1549-8328","1558-0806"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Circuits and Systems I: Regular Papers","raw_type":"journal-article"},{"id":"pmh:oai:re.public.polimi.it:11311/560588","is_oa":false,"landing_page_url":"http://hdl.handle.net/11311/560588","pdf_url":null,"source":{"id":"https://openalex.org/S4306400312","display_name":"Virtual Community of Pathological Anatomy (University of Castilla La Mancha)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I79189158","host_organization_name":"University of Castilla-La Mancha","host_organization_lineage":["https://openalex.org/I79189158"],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"","raw_type":"info:eu-repo/semantics/article"}],"best_oa_location":null,"sustainable_development_goals":[{"score":0.8700000047683716,"display_name":"Affordable and clean energy","id":"https://metadata.un.org/sdg/7"}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":19,"referenced_works":["https://openalex.org/W1974534995","https://openalex.org/W2062952706","https://openalex.org/W2084208879","https://openalex.org/W2101597431","https://openalex.org/W2110815580","https://openalex.org/W2112713971","https://openalex.org/W2127383597","https://openalex.org/W2128282260","https://openalex.org/W2132523705","https://openalex.org/W2143432773","https://openalex.org/W2150783292","https://openalex.org/W2154332266","https://openalex.org/W2154563098","https://openalex.org/W2163630970","https://openalex.org/W2164002677","https://openalex.org/W2166268103","https://openalex.org/W2168543008","https://openalex.org/W2171210937","https://openalex.org/W4242444796"],"related_works":["https://openalex.org/W1576949837","https://openalex.org/W984417604","https://openalex.org/W2498262093","https://openalex.org/W2188779191","https://openalex.org/W3134930219","https://openalex.org/W2967785526","https://openalex.org/W2162551450","https://openalex.org/W2372909716","https://openalex.org/W1912065184","https://openalex.org/W2036880312"],"abstract_inverted_index":{"This":[0],"paper":[1],"presents":[2],"the":[3,49,58,84,103,107,112,129],"design":[4],"of":[5,48,70,118],"a":[6,12,23,71],"time-to-digital":[7],"converter":[8,19],"(TDC)":[9],"suitable":[10],"for":[11],"3.5-GHz":[13,59],"all-digital":[14],"phase-lock":[15],"loop":[16],"(PLL).":[17],"The":[18,45,68,90,116,139,149,157],"is":[20,52,74,88,133,152,160],"based":[21],"on":[22,83],"digital":[24,50],"bang-bang":[25],"delay-lock":[26],"loop,":[27],"which":[28,100],"allows":[29],"constant":[30],"resolution":[31,132],"over":[32],"process":[33],"and":[34,41,77,80,128,145],"temperatures":[35],"spreads,":[36],"avoids":[37],"an":[38],"off-chip":[39],"filter":[40,51],"guarantees":[42],"fast":[43],"lock.":[44],"clock":[46],"rate":[47],"scaled":[53],"down":[54],"by":[55,111],"eight":[56],"from":[57],"input":[60,104],"to":[61,102],"allow":[62],"its":[63,81],"implementation":[64],"with":[65,125],"standard":[66],"cells.":[67],"occurrence":[69],"limit":[72],"cycle":[73],"analytically":[75],"predicted":[76],"properly":[78],"minimized,":[79],"effect":[82],"PLL":[85],"phase":[86],"noise":[87],"discussed.":[89],"circuit":[91],"fabricated":[92],"in":[93,106],"90-nm":[94],"CMOS":[95],"entails":[96],"16":[97,134],"delay":[98,117],"stages,":[99],"lock":[101],"frequency":[105],"2.9-3.9-GHz":[108],"range":[109],"(limited":[110],"available":[113],"signal":[114],"source).":[115],"each":[119],"TDC":[120,130],"cell":[121],"can":[122],"be":[123],"controlled":[124],"50-fs":[126],"step":[127],"time":[131],"ps":[135],"at":[136],"3.9":[137],"GHz.":[138],"power":[140],"consumption":[141],"ranges":[142],"between":[143],"8.1":[144],"16.5":[146],"mW,":[147],"respectively.":[148],"limit-cycle-induced":[150],"spur":[151],"below":[153],"-":[154],"50":[155],"dBc.":[156],"area":[158],"occupation":[159],"0.032":[161],"mm":[162],"<sup":[163],"xmlns:mml=\"http://www.w3.org/1998/Math/MathML\"":[164],"xmlns:xlink=\"http://www.w3.org/1999/xlink\">2</sup>":[165],".":[166]},"counts_by_year":[{"year":2024,"cited_by_count":1},{"year":2022,"cited_by_count":3},{"year":2021,"cited_by_count":6},{"year":2020,"cited_by_count":3},{"year":2019,"cited_by_count":2},{"year":2018,"cited_by_count":1},{"year":2017,"cited_by_count":5},{"year":2016,"cited_by_count":5},{"year":2015,"cited_by_count":7},{"year":2014,"cited_by_count":3},{"year":2013,"cited_by_count":7},{"year":2012,"cited_by_count":5}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}