{"id":"https://openalex.org/W2071060149","doi":"https://doi.org/10.1109/tcsi.2009.2019396","title":"Modeling $R{-}2R$ Segmented-Ladder DACs","display_name":"Modeling $R{-}2R$ Segmented-Ladder DACs","publication_year":2009,"publication_date":"2009-03-30","ids":{"openalex":"https://openalex.org/W2071060149","doi":"https://doi.org/10.1109/tcsi.2009.2019396","mag":"2071060149"},"language":"en","primary_location":{"id":"doi:10.1109/tcsi.2009.2019396","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tcsi.2009.2019396","pdf_url":null,"source":{"id":"https://openalex.org/S116977442","display_name":"IEEE Transactions on Circuits and Systems I Regular Papers","issn_l":"1549-8328","issn":["1549-8328","1558-0806"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Circuits and Systems I: Regular Papers","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5017693534","display_name":"D. Marche","orcid":null},"institutions":[{"id":"https://openalex.org/I45683168","display_name":"Polytechnique Montr\u00e9al","ror":"https://ror.org/05f8d4e86","country_code":"CA","type":"education","lineage":["https://openalex.org/I45683168"]},{"id":"https://openalex.org/I29607241","display_name":"\u00c9cole Normale Sup\u00e9rieure - PSL","ror":"https://ror.org/05a0dhs15","country_code":"FR","type":"funder","lineage":["https://openalex.org/I2746051580","https://openalex.org/I29607241"]}],"countries":["CA","FR"],"is_corresponding":true,"raw_author_name":"D. Marche","raw_affiliation_strings":["Department of Electrical Engineering, \u00c9cole Polytechnique de Montr\u00e9al, Montreal, QUE, Canada","Dept. of Electr. Eng., Ecole Polytech. de Montreal, Montre\u0301al, QC, Canada"],"affiliations":[{"raw_affiliation_string":"Department of Electrical Engineering, \u00c9cole Polytechnique de Montr\u00e9al, Montreal, QUE, Canada","institution_ids":["https://openalex.org/I45683168"]},{"raw_affiliation_string":"Dept. of Electr. Eng., Ecole Polytech. de Montreal, Montre\u0301al, QC, Canada","institution_ids":["https://openalex.org/I29607241"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5038488044","display_name":"Yvon Savaria","orcid":"https://orcid.org/0000-0002-3404-9959"},"institutions":[{"id":"https://openalex.org/I45683168","display_name":"Polytechnique Montr\u00e9al","ror":"https://ror.org/05f8d4e86","country_code":"CA","type":"education","lineage":["https://openalex.org/I45683168"]},{"id":"https://openalex.org/I29607241","display_name":"\u00c9cole Normale Sup\u00e9rieure - PSL","ror":"https://ror.org/05a0dhs15","country_code":"FR","type":"funder","lineage":["https://openalex.org/I2746051580","https://openalex.org/I29607241"]}],"countries":["CA","FR"],"is_corresponding":false,"raw_author_name":"Y. Savaria","raw_affiliation_strings":["Department of Electrical Engineering, \u00c9cole Polytechnique de Montr\u00e9al, Montreal, QUE, Canada","Dept. of Electr. Eng., Ecole Polytech. de Montreal, Montre\u0301al, QC, Canada"],"affiliations":[{"raw_affiliation_string":"Department of Electrical Engineering, \u00c9cole Polytechnique de Montr\u00e9al, Montreal, QUE, Canada","institution_ids":["https://openalex.org/I45683168"]},{"raw_affiliation_string":"Dept. of Electr. Eng., Ecole Polytech. de Montreal, Montre\u0301al, QC, Canada","institution_ids":["https://openalex.org/I29607241"]}]}],"institutions":[],"countries_distinct_count":2,"institutions_distinct_count":2,"corresponding_author_ids":["https://openalex.org/A5017693534"],"corresponding_institution_ids":["https://openalex.org/I29607241","https://openalex.org/I45683168"],"apc_list":null,"apc_paid":null,"fwci":0.6845,"has_fulltext":false,"cited_by_count":56,"citation_normalized_percentile":{"value":0.72713963,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":99},"biblio":{"volume":"57","issue":"1","first_page":"31","last_page":"43"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10323","display_name":"Analog and Mixed-Signal Circuit Design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2204","display_name":"Biomedical Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10323","display_name":"Analog and Mixed-Signal Circuit Design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2204","display_name":"Biomedical Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/converters","display_name":"Converters","score":0.7480615973472595},{"id":"https://openalex.org/keywords/electrical-impedance","display_name":"Electrical impedance","score":0.6351462006568909},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.5595051050186157},{"id":"https://openalex.org/keywords/voltage","display_name":"Voltage","score":0.5145828127861023},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.5016062259674072},{"id":"https://openalex.org/keywords/code","display_name":"Code (set theory)","score":0.4616135358810425},{"id":"https://openalex.org/keywords/equivalent-circuit","display_name":"Equivalent circuit","score":0.44684308767318726},{"id":"https://openalex.org/keywords/output-impedance","display_name":"Output impedance","score":0.4467509388923645},{"id":"https://openalex.org/keywords/mode","display_name":"Mode (computer interface)","score":0.4433681070804596},{"id":"https://openalex.org/keywords/segmentation","display_name":"Segmentation","score":0.4343652129173279},{"id":"https://openalex.org/keywords/limit","display_name":"Limit (mathematics)","score":0.4139457941055298},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.3770759701728821},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.23915579915046692},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.19586265087127686},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.17192527651786804},{"id":"https://openalex.org/keywords/artificial-intelligence","display_name":"Artificial intelligence","score":0.12893319129943848}],"concepts":[{"id":"https://openalex.org/C2778422915","wikidata":"https://www.wikidata.org/wiki/Q10302051","display_name":"Converters","level":3,"score":0.7480615973472595},{"id":"https://openalex.org/C17829176","wikidata":"https://www.wikidata.org/wiki/Q179043","display_name":"Electrical impedance","level":2,"score":0.6351462006568909},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.5595051050186157},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.5145828127861023},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.5016062259674072},{"id":"https://openalex.org/C2776760102","wikidata":"https://www.wikidata.org/wiki/Q5139990","display_name":"Code (set theory)","level":3,"score":0.4616135358810425},{"id":"https://openalex.org/C23572009","wikidata":"https://www.wikidata.org/wiki/Q964981","display_name":"Equivalent circuit","level":3,"score":0.44684308767318726},{"id":"https://openalex.org/C58112919","wikidata":"https://www.wikidata.org/wiki/Q631203","display_name":"Output impedance","level":3,"score":0.4467509388923645},{"id":"https://openalex.org/C48677424","wikidata":"https://www.wikidata.org/wiki/Q6888088","display_name":"Mode (computer interface)","level":2,"score":0.4433681070804596},{"id":"https://openalex.org/C89600930","wikidata":"https://www.wikidata.org/wiki/Q1423946","display_name":"Segmentation","level":2,"score":0.4343652129173279},{"id":"https://openalex.org/C151201525","wikidata":"https://www.wikidata.org/wiki/Q177239","display_name":"Limit (mathematics)","level":2,"score":0.4139457941055298},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.3770759701728821},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.23915579915046692},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.19586265087127686},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.17192527651786804},{"id":"https://openalex.org/C154945302","wikidata":"https://www.wikidata.org/wiki/Q11660","display_name":"Artificial intelligence","level":1,"score":0.12893319129943848},{"id":"https://openalex.org/C177264268","wikidata":"https://www.wikidata.org/wiki/Q1514741","display_name":"Set (abstract data type)","level":2,"score":0.0},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.0},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.0},{"id":"https://openalex.org/C134306372","wikidata":"https://www.wikidata.org/wiki/Q7754","display_name":"Mathematical analysis","level":1,"score":0.0}],"mesh":[],"locations_count":2,"locations":[{"id":"doi:10.1109/tcsi.2009.2019396","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tcsi.2009.2019396","pdf_url":null,"source":{"id":"https://openalex.org/S116977442","display_name":"IEEE Transactions on Circuits and Systems I Regular Papers","issn_l":"1549-8328","issn":["1549-8328","1558-0806"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Circuits and Systems I: Regular Papers","raw_type":"journal-article"},{"id":"pmh:oai:publications.polymtl.ca:17924","is_oa":false,"landing_page_url":"https://publications.polymtl.ca/17924/","pdf_url":null,"source":{"id":"https://openalex.org/S4306401013","display_name":"PolyPublie (\u00c9cole Polytechnique de Montr\u00e9al)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I45683168","host_organization_name":"Polytechnique Montr\u00e9al","host_organization_lineage":["https://openalex.org/I45683168"],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"","raw_type":"Article de revue"}],"best_oa_location":null,"sustainable_development_goals":[{"score":0.5,"display_name":"Affordable and clean energy","id":"https://metadata.un.org/sdg/7"}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":13,"referenced_works":["https://openalex.org/W1823104629","https://openalex.org/W1991051966","https://openalex.org/W2055968329","https://openalex.org/W2137161160","https://openalex.org/W2155964836","https://openalex.org/W2164038418","https://openalex.org/W2164243714","https://openalex.org/W2166227439","https://openalex.org/W2169604307","https://openalex.org/W2229388803","https://openalex.org/W2245952785","https://openalex.org/W2277687644","https://openalex.org/W2816494736"],"related_works":["https://openalex.org/W3022092883","https://openalex.org/W2076512880","https://openalex.org/W2735416316","https://openalex.org/W3096630859","https://openalex.org/W2891786578","https://openalex.org/W26276653","https://openalex.org/W2896558437","https://openalex.org/W2614356215","https://openalex.org/W2111494589","https://openalex.org/W2104381207"],"abstract_inverted_index":{"Although":[0],"R-2R":[1,39,97,114],"ladders":[2,40],"are":[3,14,41,62,107],"commonly":[4],"used":[5,25],"as":[6],"digital-to-analog":[7],"converter":[8],"(DAC)":[9],"cores,":[10],"complete":[11],"equivalent":[12,84],"circuits":[13],"still":[15],"missing":[16],"from":[17],"the":[18,23,33,59,72,94,104,127],"literature":[19],"for":[20,32,43,65,88],"most":[21,95],"of":[22,38,130],"configurations":[24],"in":[26],"practice.":[27],"In":[28,48],"this":[29],"paper,":[30],"expressions":[31,61],"input":[34],"and":[35,45,81],"output":[36],"impedances":[37],"derived":[42],"current-":[44],"voltage-mode":[46,89],"operations.":[47],"addition,":[49],"since":[50],"many":[51],"DACs":[52],"use":[53],"segmentation":[54,67],"to":[55,78,109],"reach":[56],"higher":[57],"resolutions,":[58],"impedance":[60,121],"also":[63],"obtained":[64],"different":[66],"schemes.":[68],"Using":[69],"these":[70],"expressions,":[71],"existing":[73],"current-mode":[74],"model":[75],"is":[76,86],"extended":[77],"segmented":[79],"architectures,":[80],"a":[82],"new":[83],"circuit":[85],"proposed":[87,105],"designs.":[90,99],"This":[91],"allows":[92],"modeling":[93],"common":[96],"DAC":[98,115],"Simulation":[100],"results":[101,118],"produced":[102],"with":[103,123],"models":[106],"compared":[108],"measurements":[110],"on":[111],"two":[112],"14-bit":[113],"prototypes.":[116],"These":[117],"demonstrate":[119],"how":[120],"variation":[122],"code":[124],"can":[125],"limit":[126],"static":[128],"performances":[129],"high-resolution":[131],"converters.":[132]},"counts_by_year":[{"year":2025,"cited_by_count":5},{"year":2024,"cited_by_count":7},{"year":2023,"cited_by_count":7},{"year":2022,"cited_by_count":5},{"year":2021,"cited_by_count":3},{"year":2020,"cited_by_count":2},{"year":2019,"cited_by_count":2},{"year":2018,"cited_by_count":5},{"year":2017,"cited_by_count":2},{"year":2016,"cited_by_count":3},{"year":2015,"cited_by_count":7},{"year":2014,"cited_by_count":1},{"year":2013,"cited_by_count":4},{"year":2012,"cited_by_count":1}],"updated_date":"2026-03-20T23:20:44.827607","created_date":"2025-10-10T00:00:00"}
