{"id":"https://openalex.org/W1990147374","doi":"https://doi.org/10.1109/tcsi.2009.2017133","title":"Settling Time Optimization for Three-Stage CMOS Amplifier Topologies","display_name":"Settling Time Optimization for Three-Stage CMOS Amplifier Topologies","publication_year":2009,"publication_date":"2009-03-12","ids":{"openalex":"https://openalex.org/W1990147374","doi":"https://doi.org/10.1109/tcsi.2009.2017133","mag":"1990147374"},"language":"en","primary_location":{"id":"doi:10.1109/tcsi.2009.2017133","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tcsi.2009.2017133","pdf_url":null,"source":{"id":"https://openalex.org/S116977442","display_name":"IEEE Transactions on Circuits and Systems I Regular Papers","issn_l":"1549-8328","issn":["1549-8328","1558-0806"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Circuits and Systems I: Regular Papers","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5061876852","display_name":"Andrea Pugliese","orcid":"https://orcid.org/0000-0003-4385-958X"},"institutions":[{"id":"https://openalex.org/I45204951","display_name":"University of Calabria","ror":"https://ror.org/02rc97e94","country_code":"IT","type":"education","lineage":["https://openalex.org/I45204951"]}],"countries":["IT"],"is_corresponding":false,"raw_author_name":"A. Pugliese","raw_affiliation_strings":["Department of Electronics, Computer Science and Systems, University of Calabria, Rende, Cosenza, Italy","Dept. of Electron., Comput. Sci. & Syst. Univ. of Calabria, Rende, Italy"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Electronics, Computer Science and Systems, University of Calabria, Rende, Cosenza, Italy","institution_ids":["https://openalex.org/I45204951"]},{"raw_affiliation_string":"Dept. of Electron., Comput. Sci. & Syst. Univ. of Calabria, Rende, Italy","institution_ids":["https://openalex.org/I45204951"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5071970376","display_name":"Francesco Amoroso","orcid":"https://orcid.org/0000-0002-8436-9168"},"institutions":[{"id":"https://openalex.org/I45204951","display_name":"University of Calabria","ror":"https://ror.org/02rc97e94","country_code":"IT","type":"education","lineage":["https://openalex.org/I45204951"]}],"countries":["IT"],"is_corresponding":false,"raw_author_name":"F.A. Amoroso","raw_affiliation_strings":["Department of Electronics, Computer Science and Systems, University of Calabria, Rende, Cosenza, Italy","Dept. of Electron., Comput. Sci. & Syst. Univ. of Calabria, Rende, Italy"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Electronics, Computer Science and Systems, University of Calabria, Rende, Cosenza, Italy","institution_ids":["https://openalex.org/I45204951"]},{"raw_affiliation_string":"Dept. of Electron., Comput. Sci. & Syst. Univ. of Calabria, Rende, Italy","institution_ids":["https://openalex.org/I45204951"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5047864758","display_name":"G. Cappuccino","orcid":"https://orcid.org/0000-0001-8838-3525"},"institutions":[{"id":"https://openalex.org/I45204951","display_name":"University of Calabria","ror":"https://ror.org/02rc97e94","country_code":"IT","type":"education","lineage":["https://openalex.org/I45204951"]}],"countries":["IT"],"is_corresponding":false,"raw_author_name":"G. Cappuccino","raw_affiliation_strings":["Department of Electronics, Computer Science and Systems, University of Calabria, Rende, Cosenza, Italy","Dept. of Electron., Comput. Sci. & Syst. Univ. of Calabria, Rende, Italy"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Electronics, Computer Science and Systems, University of Calabria, Rende, Cosenza, Italy","institution_ids":["https://openalex.org/I45204951"]},{"raw_affiliation_string":"Dept. of Electron., Comput. Sci. & Syst. Univ. of Calabria, Rende, Italy","institution_ids":["https://openalex.org/I45204951"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5032249162","display_name":"G. Cocorullo","orcid":"https://orcid.org/0000-0001-9133-0774"},"institutions":[{"id":"https://openalex.org/I45204951","display_name":"University of Calabria","ror":"https://ror.org/02rc97e94","country_code":"IT","type":"education","lineage":["https://openalex.org/I45204951"]}],"countries":["IT"],"is_corresponding":false,"raw_author_name":"G. Cocorullo","raw_affiliation_strings":["Department of Electronics, Computer Science and Systems, University of Calabria, Rende, Cosenza, Italy","Dept. of Electron., Comput. Sci. & Syst. Univ. of Calabria, Rende, Italy"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Electronics, Computer Science and Systems, University of Calabria, Rende, Cosenza, Italy","institution_ids":["https://openalex.org/I45204951"]},{"raw_affiliation_string":"Dept. of Electron., Comput. Sci. & Syst. Univ. of Calabria, Rende, Italy","institution_ids":["https://openalex.org/I45204951"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":4,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":2.5261,"has_fulltext":false,"cited_by_count":37,"citation_normalized_percentile":{"value":0.88216835,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":90,"max":98},"biblio":{"volume":"56","issue":"12","first_page":"2569","last_page":"2582"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10323","display_name":"Analog and Mixed-Signal Circuit Design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2204","display_name":"Biomedical Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10323","display_name":"Analog and Mixed-Signal Circuit Design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2204","display_name":"Biomedical Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10187","display_name":"Radio Frequency Integrated Circuit Design","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/settling-time","display_name":"Settling time","score":0.7112556099891663},{"id":"https://openalex.org/keywords/network-topology","display_name":"Network topology","score":0.6717256903648376},{"id":"https://openalex.org/keywords/sizing","display_name":"Sizing","score":0.6657979488372803},{"id":"https://openalex.org/keywords/settling","display_name":"Settling","score":0.6170187592506409},{"id":"https://openalex.org/keywords/cmos","display_name":"CMOS","score":0.5424216389656067},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.5421943664550781},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.5138381123542786},{"id":"https://openalex.org/keywords/compensation","display_name":"Compensation (psychology)","score":0.46338924765586853},{"id":"https://openalex.org/keywords/figure-of-merit","display_name":"Figure of merit","score":0.4566042721271515},{"id":"https://openalex.org/keywords/operational-amplifier","display_name":"Operational amplifier","score":0.450877845287323},{"id":"https://openalex.org/keywords/topology","display_name":"Topology (electrical circuits)","score":0.4343530535697937},{"id":"https://openalex.org/keywords/amplifier","display_name":"Amplifier","score":0.430732786655426},{"id":"https://openalex.org/keywords/frequency-compensation","display_name":"Frequency compensation","score":0.4293660521507263},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.2833114266395569},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.2464483380317688},{"id":"https://openalex.org/keywords/control-engineering","display_name":"Control engineering","score":0.11460047960281372},{"id":"https://openalex.org/keywords/step-response","display_name":"Step response","score":0.10584118962287903},{"id":"https://openalex.org/keywords/computer-network","display_name":"Computer network","score":0.07279995083808899}],"concepts":[{"id":"https://openalex.org/C14781684","wikidata":"https://www.wikidata.org/wiki/Q3983320","display_name":"Settling time","level":3,"score":0.7112556099891663},{"id":"https://openalex.org/C199845137","wikidata":"https://www.wikidata.org/wiki/Q145490","display_name":"Network topology","level":2,"score":0.6717256903648376},{"id":"https://openalex.org/C2777767291","wikidata":"https://www.wikidata.org/wiki/Q1080291","display_name":"Sizing","level":2,"score":0.6657979488372803},{"id":"https://openalex.org/C173209714","wikidata":"https://www.wikidata.org/wiki/Q923906","display_name":"Settling","level":2,"score":0.6170187592506409},{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.5424216389656067},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.5421943664550781},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.5138381123542786},{"id":"https://openalex.org/C2780023022","wikidata":"https://www.wikidata.org/wiki/Q1338171","display_name":"Compensation (psychology)","level":2,"score":0.46338924765586853},{"id":"https://openalex.org/C130277099","wikidata":"https://www.wikidata.org/wiki/Q3676605","display_name":"Figure of merit","level":2,"score":0.4566042721271515},{"id":"https://openalex.org/C145366948","wikidata":"https://www.wikidata.org/wiki/Q178947","display_name":"Operational amplifier","level":4,"score":0.450877845287323},{"id":"https://openalex.org/C184720557","wikidata":"https://www.wikidata.org/wiki/Q7825049","display_name":"Topology (electrical circuits)","level":2,"score":0.4343530535697937},{"id":"https://openalex.org/C194257627","wikidata":"https://www.wikidata.org/wiki/Q211554","display_name":"Amplifier","level":3,"score":0.430732786655426},{"id":"https://openalex.org/C131782439","wikidata":"https://www.wikidata.org/wiki/Q1455581","display_name":"Frequency compensation","level":4,"score":0.4293660521507263},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.2833114266395569},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.2464483380317688},{"id":"https://openalex.org/C133731056","wikidata":"https://www.wikidata.org/wiki/Q4917288","display_name":"Control engineering","level":1,"score":0.11460047960281372},{"id":"https://openalex.org/C160030872","wikidata":"https://www.wikidata.org/wiki/Q2142864","display_name":"Step response","level":2,"score":0.10584118962287903},{"id":"https://openalex.org/C31258907","wikidata":"https://www.wikidata.org/wiki/Q1301371","display_name":"Computer network","level":1,"score":0.07279995083808899},{"id":"https://openalex.org/C31972630","wikidata":"https://www.wikidata.org/wiki/Q844240","display_name":"Computer vision","level":1,"score":0.0},{"id":"https://openalex.org/C87717796","wikidata":"https://www.wikidata.org/wiki/Q146326","display_name":"Environmental engineering","level":1,"score":0.0},{"id":"https://openalex.org/C11171543","wikidata":"https://www.wikidata.org/wiki/Q41630","display_name":"Psychoanalysis","level":1,"score":0.0},{"id":"https://openalex.org/C15744967","wikidata":"https://www.wikidata.org/wiki/Q9418","display_name":"Psychology","level":0,"score":0.0},{"id":"https://openalex.org/C142362112","wikidata":"https://www.wikidata.org/wiki/Q735","display_name":"Art","level":0,"score":0.0},{"id":"https://openalex.org/C153349607","wikidata":"https://www.wikidata.org/wiki/Q36649","display_name":"Visual arts","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/tcsi.2009.2017133","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tcsi.2009.2017133","pdf_url":null,"source":{"id":"https://openalex.org/S116977442","display_name":"IEEE Transactions on Circuits and Systems I Regular Papers","issn_l":"1549-8328","issn":["1549-8328","1558-0806"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Circuits and Systems I: Regular Papers","raw_type":"journal-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":31,"referenced_works":["https://openalex.org/W1549744172","https://openalex.org/W1583439921","https://openalex.org/W1592506358","https://openalex.org/W1719157710","https://openalex.org/W1827562294","https://openalex.org/W1968300101","https://openalex.org/W1974372886","https://openalex.org/W1974779192","https://openalex.org/W1978678774","https://openalex.org/W2011100675","https://openalex.org/W2014643058","https://openalex.org/W2031649171","https://openalex.org/W2067402917","https://openalex.org/W2072816683","https://openalex.org/W2076027811","https://openalex.org/W2086568432","https://openalex.org/W2092504306","https://openalex.org/W2100186220","https://openalex.org/W2106212725","https://openalex.org/W2107224510","https://openalex.org/W2113851294","https://openalex.org/W2125776391","https://openalex.org/W2127644813","https://openalex.org/W2130500333","https://openalex.org/W2139144515","https://openalex.org/W2147121405","https://openalex.org/W2161583624","https://openalex.org/W2162080503","https://openalex.org/W2162599988","https://openalex.org/W4214744378","https://openalex.org/W6637400765"],"related_works":["https://openalex.org/W2133128399","https://openalex.org/W2068808680","https://openalex.org/W2015106506","https://openalex.org/W2769669497","https://openalex.org/W2056587553","https://openalex.org/W2091536637","https://openalex.org/W2048159162","https://openalex.org/W2029130080","https://openalex.org/W2111225211","https://openalex.org/W2061522778"],"abstract_inverted_index":{"A":[0],"new":[1],"settling-time-oriented":[2],"design":[3,76],"methodology":[4,50],"for":[5,78],"the":[6,16,27,31,38,46,49,52,55,57,74,91,98,107,110,113,117,129],"most":[7],"common":[8],"three-stage":[9,59],"operational":[10],"amplifier":[11],"(op-amp)":[12],"schemes":[13],"reported":[14],"in":[15,20,34,64,97,125,132],"literature":[17],"is":[18,122],"presented":[19],"this":[21],"paper.":[22],"The":[23],"proposed":[24,75,96],"approach":[25],"allows":[26],"systematic":[28],"sizing":[29,94],"of":[30,48,54,103,134],"compensation":[32,92],"network":[33,93],"order":[35,126],"to":[36,90,127],"reach":[37],"best":[39],"closed-loop":[40],"op-amp":[41,60,119,130],"settling":[42,85,111],"behavior.":[43],"To":[44],"demonstrate":[45],"effectiveness":[47],"and":[51,116],"correctness":[53],"analysis,":[56],"examined":[58],"topologies":[61],"are":[62],"designed":[63],"a":[65,83],"commercial":[66],"0.35-\u00bfm":[67],"CMOS":[68],"technology.":[69],"Circuit":[70],"simulations":[71],"show":[72],"that":[73],"approach,":[77],"each":[79],"investigated":[80],"topology,":[81],"guarantees":[82],"significant":[84],"time":[86],"reduction":[87],"with":[88],"respect":[89],"strategies":[95],"past.":[99],"An":[100],"ad-hoc":[101],"figure":[102],"merit,":[104],"which":[105],"evaluates":[106],"trade-off":[108],"between":[109],"time,":[112],"load":[114],"capacitance":[115],"total":[118],"stage":[120],"transconductances,":[121],"also":[123],"defined":[124],"estimate":[128],"efficiency":[131],"terms":[133],"time-domain":[135],"performances.":[136]},"counts_by_year":[{"year":2025,"cited_by_count":3},{"year":2024,"cited_by_count":2},{"year":2022,"cited_by_count":2},{"year":2021,"cited_by_count":5},{"year":2020,"cited_by_count":2},{"year":2019,"cited_by_count":2},{"year":2018,"cited_by_count":1},{"year":2016,"cited_by_count":3},{"year":2015,"cited_by_count":2},{"year":2014,"cited_by_count":2},{"year":2013,"cited_by_count":2},{"year":2012,"cited_by_count":2}],"updated_date":"2026-06-11T09:08:48.828518","created_date":"2025-10-10T00:00:00"}