{"id":"https://openalex.org/W2156727676","doi":"https://doi.org/10.1109/tcsi.2008.2001372","title":"Design of Thermally Robust Clock Trees Using Dynamically Adaptive Clock Buffers","display_name":"Design of Thermally Robust Clock Trees Using Dynamically Adaptive Clock Buffers","publication_year":2009,"publication_date":"2009-02-01","ids":{"openalex":"https://openalex.org/W2156727676","doi":"https://doi.org/10.1109/tcsi.2008.2001372","mag":"2156727676"},"language":"en","primary_location":{"id":"doi:10.1109/tcsi.2008.2001372","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tcsi.2008.2001372","pdf_url":null,"source":{"id":"https://openalex.org/S116977442","display_name":"IEEE Transactions on Circuits and Systems I Regular Papers","issn_l":"1549-8328","issn":["1549-8328","1558-0806"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Circuits and Systems I: Regular Papers","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5109152866","display_name":"Tamer Ragheb","orcid":null},"institutions":[{"id":"https://openalex.org/I74775410","display_name":"Rice University","ror":"https://ror.org/008zs3103","country_code":"US","type":"education","lineage":["https://openalex.org/I74775410"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"T. Ragheb","raw_affiliation_strings":["Rice Automated Nanoscale Design Group, Electrical and Computer Engineering Department, Rice University, Houston, TX, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Rice Automated Nanoscale Design Group, Electrical and Computer Engineering Department, Rice University, Houston, TX, USA","institution_ids":["https://openalex.org/I74775410"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5001075285","display_name":"Andrew J. Ricketts","orcid":null},"institutions":[{"id":"https://openalex.org/I130769515","display_name":"Pennsylvania State University","ror":"https://ror.org/04p491231","country_code":"US","type":"education","lineage":["https://openalex.org/I130769515"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"A. Ricketts","raw_affiliation_strings":["Department of Computer Science and Engineering, Pennsylvania State University, University Park, PA, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Computer Science and Engineering, Pennsylvania State University, University Park, PA, USA","institution_ids":["https://openalex.org/I130769515"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5111789913","display_name":"Mosin Mondal","orcid":null},"institutions":[{"id":"https://openalex.org/I74775410","display_name":"Rice University","ror":"https://ror.org/008zs3103","country_code":"US","type":"education","lineage":["https://openalex.org/I74775410"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"M. Mondal","raw_affiliation_strings":["Rice Automated Nanoscale Design Group, Electrical and Computer Engineering Department, Rice University, Houston, TX, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Rice Automated Nanoscale Design Group, Electrical and Computer Engineering Department, Rice University, Houston, TX, USA","institution_ids":["https://openalex.org/I74775410"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5047509515","display_name":"Sami Kirolos","orcid":null},"institutions":[{"id":"https://openalex.org/I74775410","display_name":"Rice University","ror":"https://ror.org/008zs3103","country_code":"US","type":"education","lineage":["https://openalex.org/I74775410"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"S. Kirolos","raw_affiliation_strings":["Rice Automated Nanoscale Design Group, Electrical and Computer Engineering Department, Rice University, Houston, TX, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Rice Automated Nanoscale Design Group, Electrical and Computer Engineering Department, Rice University, Houston, TX, USA","institution_ids":["https://openalex.org/I74775410"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5066498830","display_name":"G.M. Links","orcid":null},"institutions":[{"id":"https://openalex.org/I130769515","display_name":"Pennsylvania State University","ror":"https://ror.org/04p491231","country_code":"US","type":"education","lineage":["https://openalex.org/I130769515"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"G.M. Links","raw_affiliation_strings":["Department of Computer Science and Engineering, Pennsylvania State University, University Park, PA, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Computer Science and Engineering, Pennsylvania State University, University Park, PA, USA","institution_ids":["https://openalex.org/I130769515"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5101919131","display_name":"Vijaykrishnan Narayanan","orcid":"https://orcid.org/0000-0001-6266-6068"},"institutions":[{"id":"https://openalex.org/I130769515","display_name":"Pennsylvania State University","ror":"https://ror.org/04p491231","country_code":"US","type":"education","lineage":["https://openalex.org/I130769515"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"V. Narayanan","raw_affiliation_strings":["Department of Computer Science and Engineering, Pennsylvania State University, University Park, PA, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Computer Science and Engineering, Pennsylvania State University, University Park, PA, USA","institution_ids":["https://openalex.org/I130769515"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5057380866","display_name":"Yehia Massoud","orcid":"https://orcid.org/0000-0002-6701-0639"},"institutions":[{"id":"https://openalex.org/I130769515","display_name":"Pennsylvania State University","ror":"https://ror.org/04p491231","country_code":"US","type":"education","lineage":["https://openalex.org/I130769515"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Y. Massoud","raw_affiliation_strings":["Department of Computer Science and Engineering, Pennsylvania State University, University Park, PA, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Computer Science and Engineering, Pennsylvania State University, University Park, PA, USA","institution_ids":["https://openalex.org/I130769515"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":2,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":1.8507,"has_fulltext":false,"cited_by_count":18,"citation_normalized_percentile":{"value":0.86256129,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":97},"biblio":{"volume":"56","issue":"2","first_page":"374","last_page":"383"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10472","display_name":"Semiconductor materials and devices","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10558","display_name":"Advancements in Semiconductor Devices and Circuit Design","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/clock-skew","display_name":"Clock skew","score":0.8498175144195557},{"id":"https://openalex.org/keywords/digital-clock-manager","display_name":"Digital clock manager","score":0.7189508676528931},{"id":"https://openalex.org/keywords/skew","display_name":"Skew","score":0.6986136436462402},{"id":"https://openalex.org/keywords/timing-failure","display_name":"Timing failure","score":0.6756822466850281},{"id":"https://openalex.org/keywords/clock-gating","display_name":"Clock gating","score":0.600072979927063},{"id":"https://openalex.org/keywords/synchronous-circuit","display_name":"Synchronous circuit","score":0.5946312546730042},{"id":"https://openalex.org/keywords/clock-network","display_name":"Clock network","score":0.5910791158676147},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.5785314440727234},{"id":"https://openalex.org/keywords/clock-domain-crossing","display_name":"Clock domain crossing","score":0.5653594136238098},{"id":"https://openalex.org/keywords/clock-synchronization","display_name":"Clock synchronization","score":0.47236210107803345},{"id":"https://openalex.org/keywords/clock-drift","display_name":"Clock drift","score":0.44681668281555176},{"id":"https://openalex.org/keywords/synchronization","display_name":"Synchronization (alternating current)","score":0.44282519817352295},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.42996177077293396},{"id":"https://openalex.org/keywords/static-timing-analysis","display_name":"Static timing analysis","score":0.41966331005096436},{"id":"https://openalex.org/keywords/clock-signal","display_name":"Clock signal","score":0.39751487970352173},{"id":"https://openalex.org/keywords/electronic-circuit","display_name":"Electronic circuit","score":0.37560293078422546},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.23567429184913635},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.1885938048362732},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.1676657497882843},{"id":"https://openalex.org/keywords/telecommunications","display_name":"Telecommunications","score":0.07673817873001099}],"concepts":[{"id":"https://openalex.org/C60501442","wikidata":"https://www.wikidata.org/wiki/Q4382014","display_name":"Clock skew","level":4,"score":0.8498175144195557},{"id":"https://openalex.org/C113074038","wikidata":"https://www.wikidata.org/wiki/Q5276052","display_name":"Digital clock manager","level":5,"score":0.7189508676528931},{"id":"https://openalex.org/C43711488","wikidata":"https://www.wikidata.org/wiki/Q7534783","display_name":"Skew","level":2,"score":0.6986136436462402},{"id":"https://openalex.org/C104654189","wikidata":"https://www.wikidata.org/wiki/Q7806740","display_name":"Timing failure","level":5,"score":0.6756822466850281},{"id":"https://openalex.org/C22716491","wikidata":"https://www.wikidata.org/wiki/Q590170","display_name":"Clock gating","level":5,"score":0.600072979927063},{"id":"https://openalex.org/C42196554","wikidata":"https://www.wikidata.org/wiki/Q1186179","display_name":"Synchronous circuit","level":4,"score":0.5946312546730042},{"id":"https://openalex.org/C2778182565","wikidata":"https://www.wikidata.org/wiki/Q1752879","display_name":"Clock network","level":5,"score":0.5910791158676147},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.5785314440727234},{"id":"https://openalex.org/C127204226","wikidata":"https://www.wikidata.org/wiki/Q5134799","display_name":"Clock domain crossing","level":5,"score":0.5653594136238098},{"id":"https://openalex.org/C129891060","wikidata":"https://www.wikidata.org/wiki/Q1513059","display_name":"Clock synchronization","level":4,"score":0.47236210107803345},{"id":"https://openalex.org/C155837451","wikidata":"https://www.wikidata.org/wiki/Q1069144","display_name":"Clock drift","level":5,"score":0.44681668281555176},{"id":"https://openalex.org/C2778562939","wikidata":"https://www.wikidata.org/wiki/Q1298791","display_name":"Synchronization (alternating current)","level":3,"score":0.44282519817352295},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.42996177077293396},{"id":"https://openalex.org/C93682380","wikidata":"https://www.wikidata.org/wiki/Q2025226","display_name":"Static timing analysis","level":2,"score":0.41966331005096436},{"id":"https://openalex.org/C137059387","wikidata":"https://www.wikidata.org/wiki/Q426882","display_name":"Clock signal","level":3,"score":0.39751487970352173},{"id":"https://openalex.org/C134146338","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Electronic circuit","level":2,"score":0.37560293078422546},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.23567429184913635},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.1885938048362732},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.1676657497882843},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.07673817873001099},{"id":"https://openalex.org/C127162648","wikidata":"https://www.wikidata.org/wiki/Q16858953","display_name":"Channel (broadcasting)","level":2,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/tcsi.2008.2001372","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tcsi.2008.2001372","pdf_url":null,"source":{"id":"https://openalex.org/S116977442","display_name":"IEEE Transactions on Circuits and Systems I Regular Papers","issn_l":"1549-8328","issn":["1549-8328","1558-0806"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Circuits and Systems I: Regular Papers","raw_type":"journal-article"}],"best_oa_location":null,"sustainable_development_goals":[{"display_name":"Affordable and clean energy","score":0.5699999928474426,"id":"https://metadata.un.org/sdg/7"}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":25,"referenced_works":["https://openalex.org/W1509583710","https://openalex.org/W1527137186","https://openalex.org/W1906572721","https://openalex.org/W2031538835","https://openalex.org/W2069345435","https://openalex.org/W2075891646","https://openalex.org/W2108880814","https://openalex.org/W2114987195","https://openalex.org/W2117648153","https://openalex.org/W2127664190","https://openalex.org/W2132144911","https://openalex.org/W2132816157","https://openalex.org/W2144302754","https://openalex.org/W2144809715","https://openalex.org/W2154941994","https://openalex.org/W2157024459","https://openalex.org/W2157089032","https://openalex.org/W2157133114","https://openalex.org/W2157763958","https://openalex.org/W3105418640","https://openalex.org/W3159140662","https://openalex.org/W4238535529","https://openalex.org/W4247586331","https://openalex.org/W6679421688","https://openalex.org/W6681300864"],"related_works":["https://openalex.org/W4247180033","https://openalex.org/W2088914741","https://openalex.org/W2617666058","https://openalex.org/W3006003651","https://openalex.org/W60672686","https://openalex.org/W2520965597","https://openalex.org/W3048124756","https://openalex.org/W4247089581","https://openalex.org/W2787237207","https://openalex.org/W2411759562"],"abstract_inverted_index":{"On-chip":[0],"temperature":[1,36,84,94,126],"gradient":[2,85],"has":[3],"emerged":[4],"as":[5],"a":[6,91],"major":[7],"design":[8,174],"concern":[9],"for":[10,14,27,56,90],"high-performance":[11],"integrated":[12],"circuits":[13,30],"the":[15,35,42,58,69,75,80,87,113,125,131,136,140,147,161],"current":[16],"and":[17,105,134,173],"future":[18],"technology":[19],"nodes.":[20],"Clock":[21],"skew":[22,61,89,162],"is":[23,32,51,157],"an":[24,108,119],"undesirable":[25],"phenomenon":[26],"synchronous":[28],"digital":[29],"that":[31,96,123,153],"exacerbated":[33],"by":[34,62,163],"difference":[37],"between":[38],"various":[39],"parts":[40,129],"of":[41,48,74,82,93,111,127,130,139,159],"clock":[43,60,70,76,88,115,132,142,148,171],"tree.":[44],"The":[45],"main":[46],"aim":[47],"this":[49],"paper":[50],"to":[52,102,145,165,168],"provide":[53],"intelligent":[54],"solution":[55],"minimizing":[57],"temperature-dependent":[59],"designing":[63],"dynamically":[64,144],"adaptive":[65,120,155],"circuit":[66,121],"elements,":[67],"particularly":[68],"buffers.":[71],"Using":[72],"anRLCmodel":[73],"tree,":[77],"we":[78,117],"investigate":[79],"effect":[81],"on-chip":[83],"on":[86],"number":[92],"profiles":[95],"can":[97],"arise":[98],"in":[99],"practice":[100],"due":[101],"different":[103,128],"architectures":[104],"applications.":[106],"As":[107],"effective":[109],"way":[110],"mitigating":[112],"variable":[114],"skew,":[116],"present":[118],"technique":[122,156],"senses":[124],"tree":[133],"adjusts":[135],"driving":[137],"strengths":[138],"corresponding":[141],"buffers":[143],"reduce":[146],"skew.":[149],"Simulation":[150],"results":[151],"demonstrate":[152],"our":[154],"capable":[158],"reducing":[160],"up":[164],"92.4%,":[166],"leading":[167],"much":[169],"improved":[170],"synchronization":[172],"performance.":[175]},"counts_by_year":[{"year":2026,"cited_by_count":1},{"year":2022,"cited_by_count":4},{"year":2018,"cited_by_count":1},{"year":2017,"cited_by_count":1},{"year":2015,"cited_by_count":2},{"year":2014,"cited_by_count":1},{"year":2013,"cited_by_count":1},{"year":2012,"cited_by_count":2}],"updated_date":"2026-07-29T09:40:50.615796","created_date":"2025-10-10T00:00:00"}