{"id":"https://openalex.org/W2170411227","doi":"https://doi.org/10.1109/tce.2003.1261231","title":"Design and implementation of a novel sync processing system for composite video signals","display_name":"Design and implementation of a novel sync processing system for composite video signals","publication_year":2003,"publication_date":"2003-11-01","ids":{"openalex":"https://openalex.org/W2170411227","doi":"https://doi.org/10.1109/tce.2003.1261231","mag":"2170411227"},"language":"en","primary_location":{"id":"doi:10.1109/tce.2003.1261231","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tce.2003.1261231","pdf_url":null,"source":{"id":"https://openalex.org/S126824455","display_name":"IEEE Transactions on Consumer Electronics","issn_l":"0098-3063","issn":["0098-3063","1558-4127"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Consumer Electronics","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5103697228","display_name":"Dengpan Mou","orcid":null},"institutions":[{"id":"https://openalex.org/I196349391","display_name":"Universit\u00e4t Ulm","ror":"https://ror.org/032000t02","country_code":"DE","type":"education","lineage":["https://openalex.org/I196349391"]}],"countries":["DE"],"is_corresponding":true,"raw_author_name":"Dengpan Mou","raw_affiliation_strings":["Microelectronics Department, University of Ulm (EBS), Ulm, Germany"],"affiliations":[{"raw_affiliation_string":"Microelectronics Department, University of Ulm (EBS), Ulm, Germany","institution_ids":["https://openalex.org/I196349391"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5040385180","display_name":"R. Lares","orcid":null},"institutions":[{"id":"https://openalex.org/I196349391","display_name":"Universit\u00e4t Ulm","ror":"https://ror.org/032000t02","country_code":"DE","type":"education","lineage":["https://openalex.org/I196349391"]}],"countries":["DE"],"is_corresponding":false,"raw_author_name":"R. Lares","raw_affiliation_strings":["Microelectronics Department, University of Ulm (EBS), Ulm, Germany"],"affiliations":[{"raw_affiliation_string":"Microelectronics Department, University of Ulm (EBS), Ulm, Germany","institution_ids":["https://openalex.org/I196349391"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5103183089","display_name":"W. Y. Yan","orcid":"https://orcid.org/0009-0005-4407-7856"},"institutions":[{"id":"https://openalex.org/I4210093367","display_name":"Deutsche Telekom (Germany)","ror":"https://ror.org/00m8prc86","country_code":"DE","type":"company","lineage":["https://openalex.org/I4210093367"]}],"countries":["DE"],"is_corresponding":false,"raw_author_name":"Wenhao Yan","raw_affiliation_strings":["Deutsche Thomson Brandt GmbH, Villingen-Schwenningen, Germany"],"affiliations":[{"raw_affiliation_string":"Deutsche Thomson Brandt GmbH, Villingen-Schwenningen, Germany","institution_ids":["https://openalex.org/I4210093367"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5017273560","display_name":"F. Rominger","orcid":null},"institutions":[{"id":"https://openalex.org/I4210093367","display_name":"Deutsche Telekom (Germany)","ror":"https://ror.org/00m8prc86","country_code":"DE","type":"company","lineage":["https://openalex.org/I4210093367"]}],"countries":["DE"],"is_corresponding":false,"raw_author_name":"F. Rominger","raw_affiliation_strings":["Deutsche Thomson Brandt GmbH, Villingen-Schwenningen, Germany"],"affiliations":[{"raw_affiliation_string":"Deutsche Thomson Brandt GmbH, Villingen-Schwenningen, Germany","institution_ids":["https://openalex.org/I4210093367"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5112718098","display_name":"Albrecht Rothermel","orcid":null},"institutions":[{"id":"https://openalex.org/I196349391","display_name":"Universit\u00e4t Ulm","ror":"https://ror.org/032000t02","country_code":"DE","type":"education","lineage":["https://openalex.org/I196349391"]}],"countries":["DE"],"is_corresponding":false,"raw_author_name":"A. Rothermel","raw_affiliation_strings":["Microelectronics Department, University of Ulm (EBS), Ulm, Germany"],"affiliations":[{"raw_affiliation_string":"Microelectronics Department, University of Ulm (EBS), Ulm, Germany","institution_ids":["https://openalex.org/I196349391"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":5,"corresponding_author_ids":["https://openalex.org/A5103697228"],"corresponding_institution_ids":["https://openalex.org/I196349391"],"apc_list":null,"apc_paid":null,"fwci":0.2928,"has_fulltext":false,"cited_by_count":2,"citation_normalized_percentile":{"value":0.61021505,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":90,"max":94},"biblio":{"volume":"49","issue":"4","first_page":"1286","last_page":"1291"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11034","display_name":"Digital Filter Design and Implementation","score":0.9994999766349792,"subfield":{"id":"https://openalex.org/subfields/1711","display_name":"Signal Processing"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11034","display_name":"Digital Filter Design and Implementation","score":0.9994999766349792,"subfield":{"id":"https://openalex.org/subfields/1711","display_name":"Signal Processing"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11417","display_name":"Advancements in PLL and VCO Technologies","score":0.9993000030517578,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11447","display_name":"Blind Source Separation Techniques","score":0.9926999807357788,"subfield":{"id":"https://openalex.org/subfields/1711","display_name":"Signal Processing"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/sync","display_name":"sync","score":0.9142133593559265},{"id":"https://openalex.org/keywords/phase-locked-loop","display_name":"Phase-locked loop","score":0.826321005821228},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6563965082168579},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.6388798952102661},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.5869753956794739},{"id":"https://openalex.org/keywords/synchronization","display_name":"Synchronization (alternating current)","score":0.5342295169830322},{"id":"https://openalex.org/keywords/signal-processing","display_name":"Signal processing","score":0.515219509601593},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.48467567563056946},{"id":"https://openalex.org/keywords/cmos","display_name":"CMOS","score":0.44232383370399475},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.4009529948234558},{"id":"https://openalex.org/keywords/digital-signal-processing","display_name":"Digital signal processing","score":0.37915679812431335},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.269718199968338},{"id":"https://openalex.org/keywords/phase-noise","display_name":"Phase noise","score":0.18661677837371826},{"id":"https://openalex.org/keywords/telecommunications","display_name":"Telecommunications","score":0.16166231036186218},{"id":"https://openalex.org/keywords/frame","display_name":"Frame (networking)","score":0.11273053288459778}],"concepts":[{"id":"https://openalex.org/C3913047","wikidata":"https://www.wikidata.org/wiki/Q1956265","display_name":"sync","level":3,"score":0.9142133593559265},{"id":"https://openalex.org/C12707504","wikidata":"https://www.wikidata.org/wiki/Q52637","display_name":"Phase-locked loop","level":3,"score":0.826321005821228},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6563965082168579},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.6388798952102661},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.5869753956794739},{"id":"https://openalex.org/C2778562939","wikidata":"https://www.wikidata.org/wiki/Q1298791","display_name":"Synchronization (alternating current)","level":3,"score":0.5342295169830322},{"id":"https://openalex.org/C104267543","wikidata":"https://www.wikidata.org/wiki/Q208163","display_name":"Signal processing","level":3,"score":0.515219509601593},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.48467567563056946},{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.44232383370399475},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.4009529948234558},{"id":"https://openalex.org/C84462506","wikidata":"https://www.wikidata.org/wiki/Q173142","display_name":"Digital signal processing","level":2,"score":0.37915679812431335},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.269718199968338},{"id":"https://openalex.org/C89631360","wikidata":"https://www.wikidata.org/wiki/Q1428766","display_name":"Phase noise","level":2,"score":0.18661677837371826},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.16166231036186218},{"id":"https://openalex.org/C126042441","wikidata":"https://www.wikidata.org/wiki/Q1324888","display_name":"Frame (networking)","level":2,"score":0.11273053288459778},{"id":"https://openalex.org/C127162648","wikidata":"https://www.wikidata.org/wiki/Q16858953","display_name":"Channel (broadcasting)","level":2,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/tce.2003.1261231","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tce.2003.1261231","pdf_url":null,"source":{"id":"https://openalex.org/S126824455","display_name":"IEEE Transactions on Consumer Electronics","issn_l":"0098-3063","issn":["0098-3063","1558-4127"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Consumer Electronics","raw_type":"journal-article"}],"best_oa_location":null,"sustainable_development_goals":[{"score":0.5299999713897705,"id":"https://metadata.un.org/sdg/9","display_name":"Industry, innovation and infrastructure"}],"awards":[],"funders":[{"id":"https://openalex.org/F4320325530","display_name":"Universit\u00e4t Ulm","ror":"https://ror.org/032000t02"}],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":7,"referenced_works":["https://openalex.org/W1766888123","https://openalex.org/W1970239009","https://openalex.org/W2026122614","https://openalex.org/W2161372694","https://openalex.org/W2270694755","https://openalex.org/W2293599327","https://openalex.org/W2321734724"],"related_works":["https://openalex.org/W1876592433","https://openalex.org/W4210376836","https://openalex.org/W4210925376","https://openalex.org/W2019602065","https://openalex.org/W2111590261","https://openalex.org/W197862639","https://openalex.org/W2360384790","https://openalex.org/W2109284253","https://openalex.org/W4232397253","https://openalex.org/W4235913033"],"abstract_inverted_index":{"Sync":[0],"processing":[1,24,69,85],"will":[2],"continue":[3],"to":[4,15],"be":[5],"a":[6,17,27,32,66,73,90,111,115,119],"mandatory":[7],"block":[8],"for":[9,37,45,49],"future":[10],"fully":[11],"digital":[12],"multimedia":[13],"terminals,":[14],"offer":[16],"compatible":[18],"analog":[19,150],"video":[20],"input.":[21],"Conventional":[22],"sync":[23,28,68],"circuits":[25],"employ":[26],"slicer":[29],"combined":[30],"with":[31,78,126,142,146],"PLL":[33,42,131],"(phase":[34],"locked":[35],"loop)":[36],"line":[38],"frequency":[39],"filtering.":[40],"The":[41],"is":[43,76,87],"used":[44],"historical":[46],"reasons":[47],"and":[48,95,114,148],"ease":[50],"of":[51,65,128],"implementation,":[52],"which":[53,71],"however":[54],"fundamentally":[55],"limits":[56],"the":[57,62,107,129,133,138],"performance.":[58],"This":[59,103],"paper":[60,104],"presents":[61],"prototype":[63,135],"realization":[64],"novel":[67],"system,":[70,94],"offers":[72],"performance":[74],"that":[75],"impossible":[77],"PLL-based":[79],"solutions.":[80],"It":[81],"avoids":[82],"any":[83],"recursive":[84],"blocks,":[86],"based":[88],"on":[89,106,110,118],"free":[91],"running":[92],"clock":[93],"still":[96],"delivers":[97],"an":[98],"orthogonal":[99],"output":[100],"pixel":[101],"pattern.":[102],"concentrates":[105],"prototypical":[108],"implementation":[109],"FPGA":[112],"board":[113],"synthesized":[116],"design":[117],"0.35":[120],"/spl":[121],"mu/m":[122],"CMOS":[123],"technology.":[124],"Compared":[125],"state":[127],"art":[130],"technology,":[132],"FGPA":[134],"demonstrates":[136],"impressively":[137],"improved":[139],"picture":[140],"stability":[141],"all":[143],"sources,":[144],"especially":[145],"noisy":[147],"unstable":[149],"signals.":[151]},"counts_by_year":[{"year":2016,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}