{"id":"https://openalex.org/W4417003560","doi":"https://doi.org/10.1109/tcad.2025.3640515","title":"Crosstalk Analysis and Advancements in RDL Interposer Design for High-Speed Channels","display_name":"Crosstalk Analysis and Advancements in RDL Interposer Design for High-Speed Channels","publication_year":2025,"publication_date":"2025-12-04","ids":{"openalex":"https://openalex.org/W4417003560","doi":"https://doi.org/10.1109/tcad.2025.3640515"},"language":null,"primary_location":{"id":"doi:10.1109/tcad.2025.3640515","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tcad.2025.3640515","pdf_url":null,"source":{"id":"https://openalex.org/S100835903","display_name":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","issn_l":"0278-0070","issn":["0278-0070","1937-4151"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5046648150","display_name":"Yingbo Zhao","orcid":"https://orcid.org/0000-0001-5218-3142"},"institutions":[{"id":"https://openalex.org/I148099405","display_name":"Xi'an University of Architecture and Technology","ror":"https://ror.org/04v2j2k71","country_code":"CN","type":"education","lineage":["https://openalex.org/I148099405"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Yingbo Zhao","raw_affiliation_strings":["Xi\u2019an University of Architecture and Technology","School of Mechanical and Electrical Engineering, Shaanxi Key Laboratory of Nanomaterials and Nanotechnology, Xi’an University of Architecture and Technology, Xi’an, China"],"raw_orcid":"https://orcid.org/0000-0001-5218-3142","affiliations":[{"raw_affiliation_string":"Xi\u2019an University of Architecture and Technology","institution_ids":["https://openalex.org/I148099405"]},{"raw_affiliation_string":"School of Mechanical and Electrical Engineering, Shaanxi Key Laboratory of Nanomaterials and Nanotechnology, Xi’an University of Architecture and Technology, Xi’an, China","institution_ids":["https://openalex.org/I148099405"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5058854125","display_name":"Xueqin Kou","orcid":"https://orcid.org/0000-0003-3850-942X"},"institutions":[{"id":"https://openalex.org/I148099405","display_name":"Xi'an University of Architecture and Technology","ror":"https://ror.org/04v2j2k71","country_code":"CN","type":"education","lineage":["https://openalex.org/I148099405"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Xueqin Kou","raw_affiliation_strings":["Xi\u2019an University of Architecture and Technology","School of Mechanical and Electrical Engineering, Shaanxi Key Laboratory of Nanomaterials and Nanotechnology, Xi’an University of Architecture and Technology, Xi’an, China"],"raw_orcid":"https://orcid.org/0000-0003-3850-942X","affiliations":[{"raw_affiliation_string":"Xi\u2019an University of Architecture and Technology","institution_ids":["https://openalex.org/I148099405"]},{"raw_affiliation_string":"School of Mechanical and Electrical Engineering, Shaanxi Key Laboratory of Nanomaterials and Nanotechnology, Xi’an University of Architecture and Technology, Xi’an, China","institution_ids":["https://openalex.org/I148099405"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":[],"corresponding_institution_ids":["https://openalex.org/I148099405"],"apc_list":{"value":2645,"currency":"USD","value_usd":2645},"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":0,"citation_normalized_percentile":{"value":0.20153092,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":"45","issue":"8","first_page":"3725","last_page":"3735"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11527","display_name":"3D IC and TSV technologies","score":0.9557999968528748,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11527","display_name":"3D IC and TSV technologies","score":0.9557999968528748,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11444","display_name":"Electromagnetic Compatibility and Noise Suppression","score":0.011099999770522118,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11661","display_name":"Copper Interconnects and Reliability","score":0.0066999997943639755,"subfield":{"id":"https://openalex.org/subfields/2504","display_name":"Electronic, Optical and Magnetic Materials"},"field":{"id":"https://openalex.org/fields/25","display_name":"Materials Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/signal-integrity","display_name":"Signal integrity","score":0.8133000135421753},{"id":"https://openalex.org/keywords/interposer","display_name":"Interposer","score":0.7175999879837036},{"id":"https://openalex.org/keywords/capacitance","display_name":"Capacitance","score":0.6794000267982483},{"id":"https://openalex.org/keywords/crosstalk","display_name":"Crosstalk","score":0.6182000041007996},{"id":"https://openalex.org/keywords/interconnection","display_name":"Interconnection","score":0.504800021648407},{"id":"https://openalex.org/keywords/diagonal","display_name":"Diagonal","score":0.3917999863624573},{"id":"https://openalex.org/keywords/insertion-loss","display_name":"Insertion loss","score":0.35749998688697815},{"id":"https://openalex.org/keywords/integrated-circuit","display_name":"Integrated circuit","score":0.34880000352859497},{"id":"https://openalex.org/keywords/electromagnetic-compatibility","display_name":"Electromagnetic compatibility","score":0.32739999890327454}],"concepts":[{"id":"https://openalex.org/C44938667","wikidata":"https://www.wikidata.org/wiki/Q4503810","display_name":"Signal integrity","level":3,"score":0.8133000135421753},{"id":"https://openalex.org/C158802814","wikidata":"https://www.wikidata.org/wiki/Q6056418","display_name":"Interposer","level":4,"score":0.7175999879837036},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.6840999722480774},{"id":"https://openalex.org/C30066665","wikidata":"https://www.wikidata.org/wiki/Q164399","display_name":"Capacitance","level":3,"score":0.6794000267982483},{"id":"https://openalex.org/C169822122","wikidata":"https://www.wikidata.org/wiki/Q230187","display_name":"Crosstalk","level":2,"score":0.6182000041007996},{"id":"https://openalex.org/C123745756","wikidata":"https://www.wikidata.org/wiki/Q1665949","display_name":"Interconnection","level":2,"score":0.504800021648407},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.5005999803543091},{"id":"https://openalex.org/C130367717","wikidata":"https://www.wikidata.org/wiki/Q189791","display_name":"Diagonal","level":2,"score":0.3917999863624573},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.37940001487731934},{"id":"https://openalex.org/C90327742","wikidata":"https://www.wikidata.org/wiki/Q947396","display_name":"Insertion loss","level":2,"score":0.35749998688697815},{"id":"https://openalex.org/C530198007","wikidata":"https://www.wikidata.org/wiki/Q80831","display_name":"Integrated circuit","level":2,"score":0.34880000352859497},{"id":"https://openalex.org/C125470083","wikidata":"https://www.wikidata.org/wiki/Q747288","display_name":"Electromagnetic compatibility","level":2,"score":0.32739999890327454},{"id":"https://openalex.org/C120793396","wikidata":"https://www.wikidata.org/wiki/Q173350","display_name":"Printed circuit board","level":2,"score":0.32170000672340393},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.32100000977516174},{"id":"https://openalex.org/C189714311","wikidata":"https://www.wikidata.org/wiki/Q1530371","display_name":"Common-mode signal","level":4,"score":0.31949999928474426},{"id":"https://openalex.org/C2779843651","wikidata":"https://www.wikidata.org/wiki/Q7390335","display_name":"SIGNAL (programming language)","level":2,"score":0.3165000081062317},{"id":"https://openalex.org/C104267543","wikidata":"https://www.wikidata.org/wiki/Q208163","display_name":"Signal processing","level":3,"score":0.3082999885082245},{"id":"https://openalex.org/C68278764","wikidata":"https://www.wikidata.org/wiki/Q444167","display_name":"Capacitive coupling","level":3,"score":0.3050999939441681},{"id":"https://openalex.org/C557945733","wikidata":"https://www.wikidata.org/wiki/Q389772","display_name":"Data transmission","level":2,"score":0.28859999775886536},{"id":"https://openalex.org/C74172769","wikidata":"https://www.wikidata.org/wiki/Q1446839","display_name":"Routing (electronic design automation)","level":2,"score":0.27480000257492065},{"id":"https://openalex.org/C134146338","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Electronic circuit","level":2,"score":0.2702000141143799},{"id":"https://openalex.org/C17829176","wikidata":"https://www.wikidata.org/wiki/Q179043","display_name":"Electrical impedance","level":2,"score":0.26759999990463257},{"id":"https://openalex.org/C2765594","wikidata":"https://www.wikidata.org/wiki/Q2624187","display_name":"Integrated circuit layout","level":3,"score":0.26739999651908875},{"id":"https://openalex.org/C122890649","wikidata":"https://www.wikidata.org/wiki/Q7834016","display_name":"Transfer matrix","level":2,"score":0.26510000228881836},{"id":"https://openalex.org/C154318817","wikidata":"https://www.wikidata.org/wiki/Q2157249","display_name":"Parasitic capacitance","level":4,"score":0.2565000057220459}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/tcad.2025.3640515","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tcad.2025.3640515","pdf_url":null,"source":{"id":"https://openalex.org/S100835903","display_name":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","issn_l":"0278-0070","issn":["0278-0070","1937-4151"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","raw_type":"journal-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[{"id":"https://openalex.org/G3770855725","display_name":null,"funder_award_id":"61804120","funder_id":"https://openalex.org/F4320321001","funder_display_name":"National Natural Science Foundation of China"}],"funders":[{"id":"https://openalex.org/F4320321001","display_name":"National Natural Science Foundation of China","ror":"https://ror.org/01h0zpd94"}],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":26,"referenced_works":["https://openalex.org/W2514838290","https://openalex.org/W2521823411","https://openalex.org/W2749199255","https://openalex.org/W2783370179","https://openalex.org/W3005038879","https://openalex.org/W3015969454","https://openalex.org/W3132197712","https://openalex.org/W3137288476","https://openalex.org/W3179290750","https://openalex.org/W3191540473","https://openalex.org/W3191777380","https://openalex.org/W4200494344","https://openalex.org/W4294167329","https://openalex.org/W4312460541","https://openalex.org/W4317793565","https://openalex.org/W4385525225","https://openalex.org/W4385525247","https://openalex.org/W4385525440","https://openalex.org/W4388720735","https://openalex.org/W4388721373","https://openalex.org/W4388838018","https://openalex.org/W4392905095","https://openalex.org/W4400033944","https://openalex.org/W4400034687","https://openalex.org/W4403863364","https://openalex.org/W4410295124"],"related_works":[],"abstract_inverted_index":{"In":[0],"this":[1],"paper,":[2],"we":[3,101],"introduce":[4],"an":[5,57],"electromagnetic":[6],"capacitance":[7,30],"matrix":[8,35],"for":[9,54,144,165],"high-speed":[10,166],"channels":[11,167],"to":[12,24,28,40],"analyze":[13,41,102],"crosstalk":[14],"mechanisms":[15],"in":[16,33,44,62,104,127,168],"RDL":[17,55,146],"interposers.":[18],"This":[19,139],"is":[20],"the":[21,26,34,86,94],"first":[22],"study":[23],"use":[25],"off-diagonal":[27],"diagonal":[29],"ratio":[31],"(ODDCR)":[32],"as":[36],"a":[37,67],"quantitative":[38],"metric":[39],"coupling":[42],"effects":[43],"high-frequency":[45],"scenarios.":[46],"We":[47],"then":[48],"propose":[49],"two":[50],"routing":[51],"layout":[52],"schemes":[53,76],"interposers:":[56],"optimized":[58],"Ground-Signal-Ground":[59],"(GSG)":[60],"configuration":[61,70],"full-coverage":[63],"wrap":[64],"mode":[65],"and":[66,80,89,107,117,136,158],"Ground-Signal-Signal":[68],"(GSS)":[69],"with":[71,85,113],"multiple":[72,115],"signal":[73,82,95,155],"units.":[74],"These":[75],"support":[77],"high-density":[78],"packaging":[79],"enhance":[81],"routability,":[83],"aligning":[84],"recent":[87],"HBM3":[88],"HBM4":[90],"protocols.":[91],"To":[92],"validate":[93],"integrity":[96,156],"of":[97],"these":[98],"proposed":[99],"configurations,":[100],"them":[103],"both":[105],"frequency":[106],"time":[108],"domains,":[109],"comparing":[110],"their":[111],"performance":[112],"conventional":[114],"striplines":[116],"reported":[118],"staggered":[119],"GSG":[120],"configurations.":[121],"The":[122],"results":[123],"demonstrate":[124],"significant":[125],"improvements":[126],"insertion":[128],"loss,":[129,131],"return":[130],"near-end":[132],"crosstalk,":[133,135],"far-end":[134],"eye":[137],"diagrams.":[138],"work":[140],"provides":[141],"practical":[142],"guidelines":[143],"designing":[145],"interposers,":[147],"ensuring":[148],"high":[149],"data":[150],"transfer":[151],"rates":[152],"while":[153],"addressing":[154],"issues,":[157],"offers":[159],"insights":[160],"into":[161],"optimizing":[162],"interconnect":[163],"layouts":[164],"2.5-D":[169],"ICs.":[170]},"counts_by_year":[],"updated_date":"2026-08-21T09:56:20.448147","created_date":"2025-12-04T00:00:00"}