{"id":"https://openalex.org/W4416582909","doi":"https://doi.org/10.1109/tcad.2025.3636454","title":"Low-Overhead CNN Acceleration via FFT-Based Circular Convolution and Partially Pipelined Dataflow","display_name":"Low-Overhead CNN Acceleration via FFT-Based Circular Convolution and Partially Pipelined Dataflow","publication_year":2025,"publication_date":"2025-11-24","ids":{"openalex":"https://openalex.org/W4416582909","doi":"https://doi.org/10.1109/tcad.2025.3636454"},"language":null,"primary_location":{"id":"doi:10.1109/tcad.2025.3636454","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tcad.2025.3636454","pdf_url":null,"source":{"id":"https://openalex.org/S100835903","display_name":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","issn_l":"0278-0070","issn":["0278-0070","1937-4151"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5046312537","display_name":"Yishuo Meng","orcid":"https://orcid.org/0000-0002-3402-6386"},"institutions":[{"id":"https://openalex.org/I87445476","display_name":"Xi'an Jiaotong University","ror":"https://ror.org/017zhmm22","country_code":"CN","type":"education","lineage":["https://openalex.org/I87445476"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Yishuo Meng","raw_affiliation_strings":["School of Microelectronics, Xi’an Jiaotong University, Xi’an, Shaanxi, China"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"School of Microelectronics, Xi’an Jiaotong University, Xi’an, Shaanxi, China","institution_ids":["https://openalex.org/I87445476"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5080354346","display_name":"Jianfei Wang","orcid":"https://orcid.org/0009-0004-0132-3319"},"institutions":[{"id":"https://openalex.org/I87445476","display_name":"Xi'an Jiaotong University","ror":"https://ror.org/017zhmm22","country_code":"CN","type":"education","lineage":["https://openalex.org/I87445476"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Jianfei Wang","raw_affiliation_strings":["School of Microelectronics, Xi’an Jiaotong University, Xi’an, Shaanxi, China"],"raw_orcid":"https://orcid.org/0009-0004-0132-3319","affiliations":[{"raw_affiliation_string":"School of Microelectronics, Xi’an Jiaotong University, Xi’an, Shaanxi, China","institution_ids":["https://openalex.org/I87445476"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5101992904","display_name":"Qiang Fu","orcid":"https://orcid.org/0000-0002-0332-636X"},"institutions":[{"id":"https://openalex.org/I87445476","display_name":"Xi'an Jiaotong University","ror":"https://ror.org/017zhmm22","country_code":"CN","type":"education","lineage":["https://openalex.org/I87445476"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Qiang Fu","raw_affiliation_strings":["School of Microelectronics, Xi’an Jiaotong University, Xi’an, Shaanxi, China"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"School of Microelectronics, Xi’an Jiaotong University, Xi’an, Shaanxi, China","institution_ids":["https://openalex.org/I87445476"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5021185664","display_name":"Siwei Xiang","orcid":null},"institutions":[{"id":"https://openalex.org/I87445476","display_name":"Xi'an Jiaotong University","ror":"https://ror.org/017zhmm22","country_code":"CN","type":"education","lineage":["https://openalex.org/I87445476"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Siwei Xiang","raw_affiliation_strings":["School of Microelectronics, Xi’an Jiaotong University, Xi’an, Shaanxi, China"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"School of Microelectronics, Xi’an Jiaotong University, Xi’an, Shaanxi, China","institution_ids":["https://openalex.org/I87445476"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5042282822","display_name":"Jia Hou","orcid":"https://orcid.org/0009-0007-1744-3667"},"institutions":[{"id":"https://openalex.org/I87445476","display_name":"Xi'an Jiaotong University","ror":"https://ror.org/017zhmm22","country_code":"CN","type":"education","lineage":["https://openalex.org/I87445476"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Jia Hou","raw_affiliation_strings":["School of Microelectronics, Xi’an Jiaotong University, Xi’an, Shaanxi, China"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"School of Microelectronics, Xi’an Jiaotong University, Xi’an, Shaanxi, China","institution_ids":["https://openalex.org/I87445476"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5112119294","display_name":"Zhijie Lin","orcid":"https://orcid.org/0009-0005-3334-4381"},"institutions":[{"id":"https://openalex.org/I87445476","display_name":"Xi'an Jiaotong University","ror":"https://ror.org/017zhmm22","country_code":"CN","type":"education","lineage":["https://openalex.org/I87445476"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Zhijie Lin","raw_affiliation_strings":["School of Microelectronics, Xi’an Jiaotong University, Xi’an, Shaanxi, China"],"raw_orcid":"https://orcid.org/0009-0005-3334-4381","affiliations":[{"raw_affiliation_string":"School of Microelectronics, Xi’an Jiaotong University, Xi’an, Shaanxi, China","institution_ids":["https://openalex.org/I87445476"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5032062525","display_name":"Ge Li","orcid":"https://orcid.org/0000-0002-2070-8925"},"institutions":[{"id":"https://openalex.org/I87445476","display_name":"Xi'an Jiaotong University","ror":"https://ror.org/017zhmm22","country_code":"CN","type":"education","lineage":["https://openalex.org/I87445476"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Ge Li","raw_affiliation_strings":["School of Microelectronics, Xi’an Jiaotong University, Xi’an, Shaanxi, China"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"School of Microelectronics, Xi’an Jiaotong University, Xi’an, Shaanxi, China","institution_ids":["https://openalex.org/I87445476"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5100719382","display_name":"Chen Yang","orcid":"https://orcid.org/0000-0002-8221-7670"},"institutions":[{"id":"https://openalex.org/I87445476","display_name":"Xi'an Jiaotong University","ror":"https://ror.org/017zhmm22","country_code":"CN","type":"education","lineage":["https://openalex.org/I87445476"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Chen Yang","raw_affiliation_strings":["School of Microelectronics, Xi’an Jiaotong University, Xi’an, Shaanxi, China"],"raw_orcid":"https://orcid.org/0000-0002-8221-7670","affiliations":[{"raw_affiliation_string":"School of Microelectronics, Xi’an Jiaotong University, Xi’an, Shaanxi, China","institution_ids":["https://openalex.org/I87445476"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":[],"corresponding_institution_ids":["https://openalex.org/I87445476"],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":0,"citation_normalized_percentile":{"value":0.39082509,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":"45","issue":"7","first_page":"3276","last_page":"3290"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11034","display_name":"Digital Filter Design and Implementation","score":0.3188999891281128,"subfield":{"id":"https://openalex.org/subfields/1711","display_name":"Signal Processing"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11034","display_name":"Digital Filter Design and Implementation","score":0.3188999891281128,"subfield":{"id":"https://openalex.org/subfields/1711","display_name":"Signal Processing"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11697","display_name":"Numerical Methods and Algorithms","score":0.16920000314712524,"subfield":{"id":"https://openalex.org/subfields/1703","display_name":"Computational Theory and Mathematics"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11693","display_name":"Cryptography and Residue Arithmetic","score":0.10100000351667404,"subfield":{"id":"https://openalex.org/subfields/1710","display_name":"Information Systems"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/fast-fourier-transform","display_name":"Fast Fourier transform","score":0.7797999978065491},{"id":"https://openalex.org/keywords/dataflow","display_name":"Dataflow","score":0.7469000220298767},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.6352999806404114},{"id":"https://openalex.org/keywords/convolution","display_name":"Convolution (computer science)","score":0.605400025844574},{"id":"https://openalex.org/keywords/throughput","display_name":"Throughput","score":0.5422000288963318},{"id":"https://openalex.org/keywords/overhead","display_name":"Overhead (engineering)","score":0.5281000137329102},{"id":"https://openalex.org/keywords/digital-signal-processing","display_name":"Digital signal processing","score":0.5170999765396118},{"id":"https://openalex.org/keywords/convolutional-neural-network","display_name":"Convolutional neural network","score":0.484499990940094},{"id":"https://openalex.org/keywords/reduction","display_name":"Reduction (mathematics)","score":0.460999995470047}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7908999919891357},{"id":"https://openalex.org/C75172450","wikidata":"https://www.wikidata.org/wiki/Q623950","display_name":"Fast Fourier transform","level":2,"score":0.7797999978065491},{"id":"https://openalex.org/C96324660","wikidata":"https://www.wikidata.org/wiki/Q205446","display_name":"Dataflow","level":2,"score":0.7469000220298767},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.6352999806404114},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.6068999767303467},{"id":"https://openalex.org/C45347329","wikidata":"https://www.wikidata.org/wiki/Q5166604","display_name":"Convolution (computer science)","level":3,"score":0.605400025844574},{"id":"https://openalex.org/C157764524","wikidata":"https://www.wikidata.org/wiki/Q1383412","display_name":"Throughput","level":3,"score":0.5422000288963318},{"id":"https://openalex.org/C2779960059","wikidata":"https://www.wikidata.org/wiki/Q7113681","display_name":"Overhead (engineering)","level":2,"score":0.5281000137329102},{"id":"https://openalex.org/C84462506","wikidata":"https://www.wikidata.org/wiki/Q173142","display_name":"Digital signal processing","level":2,"score":0.5170999765396118},{"id":"https://openalex.org/C81363708","wikidata":"https://www.wikidata.org/wiki/Q17084460","display_name":"Convolutional neural network","level":2,"score":0.484499990940094},{"id":"https://openalex.org/C111335779","wikidata":"https://www.wikidata.org/wiki/Q3454686","display_name":"Reduction (mathematics)","level":2,"score":0.460999995470047},{"id":"https://openalex.org/C2780595030","wikidata":"https://www.wikidata.org/wiki/Q3860309","display_name":"Multiplication (music)","level":2,"score":0.45669999718666077},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.40049999952316284},{"id":"https://openalex.org/C2221639","wikidata":"https://www.wikidata.org/wiki/Q2877","display_name":"Discrete cosine transform","level":3,"score":0.39559999108314514},{"id":"https://openalex.org/C204241405","wikidata":"https://www.wikidata.org/wiki/Q461499","display_name":"Transformation (genetics)","level":3,"score":0.39329999685287476},{"id":"https://openalex.org/C179799912","wikidata":"https://www.wikidata.org/wiki/Q205084","display_name":"Computational complexity theory","level":2,"score":0.37700000405311584},{"id":"https://openalex.org/C117896860","wikidata":"https://www.wikidata.org/wiki/Q11376","display_name":"Acceleration","level":2,"score":0.3767000138759613},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.35429999232292175},{"id":"https://openalex.org/C74193536","wikidata":"https://www.wikidata.org/wiki/Q574844","display_name":"Kernel (algebra)","level":2,"score":0.34950000047683716},{"id":"https://openalex.org/C77390884","wikidata":"https://www.wikidata.org/wiki/Q217302","display_name":"Application-specific integrated circuit","level":2,"score":0.3359000086784363},{"id":"https://openalex.org/C17137986","wikidata":"https://www.wikidata.org/wiki/Q215067","display_name":"Orthogonality","level":2,"score":0.32420000433921814},{"id":"https://openalex.org/C113775141","wikidata":"https://www.wikidata.org/wiki/Q428691","display_name":"Computer engineering","level":1,"score":0.321399986743927},{"id":"https://openalex.org/C134835016","wikidata":"https://www.wikidata.org/wiki/Q690265","display_name":"Lookup table","level":2,"score":0.3133000135421753},{"id":"https://openalex.org/C14580979","wikidata":"https://www.wikidata.org/wiki/Q876049","display_name":"Very-large-scale integration","level":2,"score":0.30630001425743103},{"id":"https://openalex.org/C58013763","wikidata":"https://www.wikidata.org/wiki/Q5754574","display_name":"High-level synthesis","level":3,"score":0.3012000024318695},{"id":"https://openalex.org/C459310","wikidata":"https://www.wikidata.org/wiki/Q117801","display_name":"Computational science","level":1,"score":0.2824999988079071},{"id":"https://openalex.org/C106131492","wikidata":"https://www.wikidata.org/wiki/Q3072260","display_name":"Filter (signal processing)","level":2,"score":0.2816999852657318},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.27880001068115234},{"id":"https://openalex.org/C104267543","wikidata":"https://www.wikidata.org/wiki/Q208163","display_name":"Signal processing","level":3,"score":0.27790001034736633},{"id":"https://openalex.org/C13164978","wikidata":"https://www.wikidata.org/wiki/Q600158","display_name":"Hardware acceleration","level":3,"score":0.2718000113964081},{"id":"https://openalex.org/C106516650","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm design","level":2,"score":0.27079999446868896},{"id":"https://openalex.org/C125411270","wikidata":"https://www.wikidata.org/wiki/Q18653","display_name":"Encoding (memory)","level":2,"score":0.2524000108242035}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/tcad.2025.3636454","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tcad.2025.3636454","pdf_url":null,"source":{"id":"https://openalex.org/S100835903","display_name":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","issn_l":"0278-0070","issn":["0278-0070","1937-4151"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","raw_type":"journal-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[{"id":"https://openalex.org/G963865091","display_name":null,"funder_award_id":"62176206","funder_id":"https://openalex.org/F4320321001","funder_display_name":"National Natural Science Foundation of China"}],"funders":[{"id":"https://openalex.org/F4320321001","display_name":"National Natural Science Foundation of China","ror":"https://ror.org/01h0zpd94"}],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":0,"referenced_works":[],"related_works":[],"abstract_inverted_index":{"Fast":[0],"Fourier":[1],"Transformation":[2],"(FFT)":[3],"has":[4],"been":[5],"widely":[6],"recognized":[7],"as":[8],"an":[9],"effective":[10],"method":[11],"for":[12,154],"reducing":[13],"the":[14,31,53,59,102,111,114,151,164,170,200],"computational":[15],"density":[16],"of":[17,34,55,107,113,163,173],"convolutional":[18],"neural":[19],"networks":[20],"(CNNs).":[21],"However,":[22],"existing":[23],"FFT-based":[24,124],"CNN":[25,125],"accelerators":[26],"fail":[27],"to":[28,46,50,78,100,160,183,192,199],"fully":[29,51],"exploit":[30],"algorithmic":[32],"advantages":[33],"FFT":[35,56,84,108],"while":[36,57,167],"introducing":[37],"significant":[38],"additional":[39],"hardware":[40,105],"overhead.":[41,61],"Consequently,":[42],"this":[43,89],"paper":[44],"tries":[45],"figure":[47],"out":[48],"how":[49],"implement":[52],"benefit":[54],"saving":[58],"transformation":[60],"First,":[62],"we":[63,91],"propose":[64],"a":[65,94,121,130,181,190],"CirConv-based":[66],"multiplication":[67],"reduction":[68],"(CMR)":[69],"algorithm,":[70,90],"which":[71],"leverages":[72],"circular":[73],"convolution":[74],"and":[75,82,104,118,148,189],"Hermitian":[76,146],"Symmetry":[77],"eliminate":[79],"unnecessary":[80],"padding":[81],"optimize":[83],"scale":[85],"selection.":[86],"Building":[87],"upon":[88],"further":[92],"design":[93],"partially":[95],"pipelined":[96],"transformation-computation":[97],"(PPTC)":[98],"dataflow":[99],"reduce":[101],"parallelism":[103],"complexity":[106],"transformation.":[109],"With":[110],"aid":[112],"proposed":[115],"CMR":[116],"algorithm":[117],"PPTC":[119,149],"dataflow,":[120,150],"high":[122],"throughput":[123],"accelerator":[126,176],"is":[127,177],"implemented":[128],"on":[129],"Xilinx":[131],"VCU118":[132],"FPGA":[133],"platform,":[134],"operating":[135],"at":[136],"250":[137],"MHz.":[138],"The":[139],"experimental":[140],"results":[141],"demonstrate":[142],"that,":[143],"by":[144],"combining":[145],"symmetry":[147],"LUT":[152],"overhead":[153],"FFT/IFFT":[155],"operations":[156],"can":[157],"be":[158],"reduced":[159],"only":[161],"12.14%":[162],"original.":[165],"Furthermore,":[166],"deploying":[168],"VGG16,":[169],"inference":[171],"performance":[172,188],"our":[174],"designed":[175],"6213":[178],"GOPS,":[179],"achieving":[180],"2.17\u00d7":[182],"29.31\u00d7":[184],"improvement":[185],"in":[186,195],"actual":[187],"1.11\u00d7":[191],"6.97\u00d7":[193],"enhancement":[194],"DSP":[196],"efficiency":[197],"compared":[198],"current":[201],"works.":[202]},"counts_by_year":[],"updated_date":"2026-06-20T20:08:15.867695","created_date":"2025-11-25T00:00:00"}