{"id":"https://openalex.org/W4415398701","doi":"https://doi.org/10.1109/tcad.2025.3624127","title":"HARD: A Heterogeneous Last-Level Cache Architecture With Readless Hierarchical Tag and Dynamic-LRU Policy","display_name":"HARD: A Heterogeneous Last-Level Cache Architecture With Readless Hierarchical Tag and Dynamic-LRU Policy","publication_year":2025,"publication_date":"2025-10-21","ids":{"openalex":"https://openalex.org/W4415398701","doi":"https://doi.org/10.1109/tcad.2025.3624127"},"language":null,"primary_location":{"id":"doi:10.1109/tcad.2025.3624127","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tcad.2025.3624127","pdf_url":null,"source":{"id":"https://openalex.org/S100835903","display_name":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","issn_l":"0278-0070","issn":["0278-0070","1937-4151"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5100685864","display_name":"Nan Li","orcid":"https://orcid.org/0000-0002-0382-1782"},"institutions":[{"id":"https://openalex.org/I157773358","display_name":"Sun Yat-sen University","ror":"https://ror.org/0064kty71","country_code":"CN","type":"education","lineage":["https://openalex.org/I157773358"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Nan Li","raw_affiliation_strings":["School of Microelectronics Science and Technology, Sun Yat-sen University, Zhuhai, China"],"raw_orcid":"https://orcid.org/0000-0002-0382-1782","affiliations":[{"raw_affiliation_string":"School of Microelectronics Science and Technology, Sun Yat-sen University, Zhuhai, China","institution_ids":["https://openalex.org/I157773358"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5034446826","display_name":"Weichong Chen","orcid":"https://orcid.org/0000-0001-7804-6605"},"institutions":[{"id":"https://openalex.org/I157773358","display_name":"Sun Yat-sen University","ror":"https://ror.org/0064kty71","country_code":"CN","type":"education","lineage":["https://openalex.org/I157773358"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Weichong Chen","raw_affiliation_strings":["School of Microelectronics Science and Technology, Sun Yat-sen University, Zhuhai, China"],"raw_orcid":"https://orcid.org/0000-0001-7804-6605","affiliations":[{"raw_affiliation_string":"School of Microelectronics Science and Technology, Sun Yat-sen University, Zhuhai, China","institution_ids":["https://openalex.org/I157773358"]}]},{"author_position":"middle","author":{"id":null,"display_name":"Xiangyu Li","orcid":"https://orcid.org/0009-0006-5413-4225"},"institutions":[{"id":"https://openalex.org/I157773358","display_name":"Sun Yat-sen University","ror":"https://ror.org/0064kty71","country_code":"CN","type":"education","lineage":["https://openalex.org/I157773358"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Xiangyu Li","raw_affiliation_strings":["School of Microelectronics Science and Technology, Sun Yat-sen University, Zhuhai, China"],"raw_orcid":"https://orcid.org/0009-0006-5413-4225","affiliations":[{"raw_affiliation_string":"School of Microelectronics Science and Technology, Sun Yat-sen University, Zhuhai, China","institution_ids":["https://openalex.org/I157773358"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5017560036","display_name":"Zhiyi Yu","orcid":"https://orcid.org/0000-0002-8802-0457"},"institutions":[{"id":"https://openalex.org/I157773358","display_name":"Sun Yat-sen University","ror":"https://ror.org/0064kty71","country_code":"CN","type":"education","lineage":["https://openalex.org/I157773358"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Zhiyi Yu","raw_affiliation_strings":["School of Microelectronics Science and Technology, Sun Yat-sen University, Zhuhai, China"],"raw_orcid":"https://orcid.org/0000-0002-8802-0457","affiliations":[{"raw_affiliation_string":"School of Microelectronics Science and Technology, Sun Yat-sen University, Zhuhai, China","institution_ids":["https://openalex.org/I157773358"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":[],"corresponding_institution_ids":["https://openalex.org/I157773358"],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":0,"citation_normalized_percentile":{"value":0.31789114,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":"45","issue":"6","first_page":"2962","last_page":"2975"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11478","display_name":"Caching and Content Delivery","score":0.9988999962806702,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11478","display_name":"Caching and Content Delivery","score":0.9988999962806702,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11181","display_name":"Advanced Data Storage Technologies","score":0.9958000183105469,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10715","display_name":"Distributed and Parallel Computing Systems","score":0.9919999837875366,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/cache","display_name":"Cache","score":0.7386000156402588},{"id":"https://openalex.org/keywords/cache-only-memory-architecture","display_name":"Cache-only memory architecture","score":0.5618000030517578},{"id":"https://openalex.org/keywords/cache-pollution","display_name":"Cache pollution","score":0.5187000036239624},{"id":"https://openalex.org/keywords/data-access","display_name":"Data access","score":0.4973999857902527},{"id":"https://openalex.org/keywords/cache-coloring","display_name":"Cache coloring","score":0.4675999879837036},{"id":"https://openalex.org/keywords/scalability","display_name":"Scalability","score":0.44440001249313354},{"id":"https://openalex.org/keywords/cache-algorithms","display_name":"Cache algorithms","score":0.415800005197525},{"id":"https://openalex.org/keywords/smart-cache","display_name":"Smart Cache","score":0.3982999920845032},{"id":"https://openalex.org/keywords/cpu-cache","display_name":"CPU cache","score":0.3885999917984009}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.8429999947547913},{"id":"https://openalex.org/C115537543","wikidata":"https://www.wikidata.org/wiki/Q165596","display_name":"Cache","level":2,"score":0.7386000156402588},{"id":"https://openalex.org/C3720319","wikidata":"https://www.wikidata.org/wiki/Q5015937","display_name":"Cache-only memory architecture","level":5,"score":0.5618000030517578},{"id":"https://openalex.org/C113166858","wikidata":"https://www.wikidata.org/wiki/Q5015981","display_name":"Cache pollution","level":5,"score":0.5187000036239624},{"id":"https://openalex.org/C47487241","wikidata":"https://www.wikidata.org/wiki/Q5227230","display_name":"Data access","level":2,"score":0.4973999857902527},{"id":"https://openalex.org/C201148951","wikidata":"https://www.wikidata.org/wiki/Q5015976","display_name":"Cache coloring","level":4,"score":0.4675999879837036},{"id":"https://openalex.org/C48044578","wikidata":"https://www.wikidata.org/wiki/Q727490","display_name":"Scalability","level":2,"score":0.44440001249313354},{"id":"https://openalex.org/C38556500","wikidata":"https://www.wikidata.org/wiki/Q13404475","display_name":"Cache algorithms","level":4,"score":0.415800005197525},{"id":"https://openalex.org/C167713795","wikidata":"https://www.wikidata.org/wiki/Q352090","display_name":"Smart Cache","level":5,"score":0.3982999920845032},{"id":"https://openalex.org/C189783530","wikidata":"https://www.wikidata.org/wiki/Q352090","display_name":"CPU cache","level":3,"score":0.3885999917984009},{"id":"https://openalex.org/C43214815","wikidata":"https://www.wikidata.org/wiki/Q7310987","display_name":"Reliability (semiconductor)","level":3,"score":0.38350000977516174},{"id":"https://openalex.org/C194080101","wikidata":"https://www.wikidata.org/wiki/Q46306","display_name":"Access time","level":2,"score":0.37880000472068787},{"id":"https://openalex.org/C25536678","wikidata":"https://www.wikidata.org/wiki/Q5015977","display_name":"Cache invalidation","level":5,"score":0.36469998955726624},{"id":"https://openalex.org/C120314980","wikidata":"https://www.wikidata.org/wiki/Q180634","display_name":"Distributed computing","level":1,"score":0.3610000014305115},{"id":"https://openalex.org/C68043766","wikidata":"https://www.wikidata.org/wiki/Q267416","display_name":"Static random-access memory","level":2,"score":0.35899999737739563},{"id":"https://openalex.org/C36340418","wikidata":"https://www.wikidata.org/wiki/Q7124288","display_name":"Page cache","level":5,"score":0.35199999809265137},{"id":"https://openalex.org/C133371097","wikidata":"https://www.wikidata.org/wiki/Q868014","display_name":"Non-uniform memory access","level":5,"score":0.3165999948978424},{"id":"https://openalex.org/C2780165032","wikidata":"https://www.wikidata.org/wiki/Q16869822","display_name":"Energy consumption","level":2,"score":0.31220000982284546},{"id":"https://openalex.org/C41036726","wikidata":"https://www.wikidata.org/wiki/Q844824","display_name":"Physical address","level":3,"score":0.31200000643730164},{"id":"https://openalex.org/C2779602883","wikidata":"https://www.wikidata.org/wiki/Q15544750","display_name":"Memory architecture","level":2,"score":0.3084000051021576},{"id":"https://openalex.org/C2742236","wikidata":"https://www.wikidata.org/wiki/Q924713","display_name":"Efficient energy use","level":2,"score":0.30140000581741333},{"id":"https://openalex.org/C146152329","wikidata":"https://www.wikidata.org/wiki/Q1932543","display_name":"Data migration","level":2,"score":0.2930999994277954},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.289000004529953},{"id":"https://openalex.org/C2777210771","wikidata":"https://www.wikidata.org/wiki/Q4927124","display_name":"Block (permutation group theory)","level":2,"score":0.27000001072883606},{"id":"https://openalex.org/C59687516","wikidata":"https://www.wikidata.org/wiki/Q5015938","display_name":"Cache-oblivious algorithm","level":5,"score":0.2660999894142151},{"id":"https://openalex.org/C123657996","wikidata":"https://www.wikidata.org/wiki/Q12271","display_name":"Architecture","level":2,"score":0.2639999985694885},{"id":"https://openalex.org/C144986985","wikidata":"https://www.wikidata.org/wiki/Q871236","display_name":"Hierarchical database model","level":2,"score":0.26010000705718994},{"id":"https://openalex.org/C111335779","wikidata":"https://www.wikidata.org/wiki/Q3454686","display_name":"Reduction (mathematics)","level":2,"score":0.2515999972820282},{"id":"https://openalex.org/C176649486","wikidata":"https://www.wikidata.org/wiki/Q2308807","display_name":"Memory management","level":3,"score":0.2500999867916107}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/tcad.2025.3624127","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tcad.2025.3624127","pdf_url":null,"source":{"id":"https://openalex.org/S100835903","display_name":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","issn_l":"0278-0070","issn":["0278-0070","1937-4151"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","raw_type":"journal-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[{"id":"https://openalex.org/G691677441","display_name":null,"funder_award_id":"62334014","funder_id":"https://openalex.org/F4320321001","funder_display_name":"National Natural Science Foundation of China"},{"id":"https://openalex.org/G7420601228","display_name":null,"funder_award_id":"2023B0303030004","funder_id":"https://openalex.org/F4320335777","funder_display_name":"National Key Research and Development Program of China"}],"funders":[{"id":"https://openalex.org/F4320321001","display_name":"National Natural Science Foundation of China","ror":"https://ror.org/01h0zpd94"},{"id":"https://openalex.org/F4320335777","display_name":"National Key Research and Development Program of China","ror":null}],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":0,"referenced_works":[],"related_works":[],"abstract_inverted_index":{"This":[0,106,155],"paper":[1],"proposes":[2],"a":[3,75,150,159,201,215],"Heterogeneous":[4],"Last":[5],"Level":[6],"Cache":[7],"Architecture":[8],"with":[9],"Readless":[10],"Hierarchical":[11],"Tag":[12,138,187,212],"and":[13,22,34,128,164,173,181,214,239],"Dynamic-LRU":[14],"Policy":[15],"(HARD),":[16],"designed":[17,70],"to":[18,102,140,222],"enhance":[19],"system":[20],"performance":[21,59,112],"reliability":[23,184],"by":[24,45,62],"leveraging":[25],"the":[26,42,53,69,95,103,111,114,137,142,183,186,211,223,228,233],"complementary":[27],"advantages":[28],"of":[29,113,146,162,185],"Static":[30],"Random-Access":[31,38],"Memory":[32,39],"(SRAM)":[33],"Spin-Orbit":[35],"Torque":[36],"Magnetic":[37],"(SOT-MRAM).":[40],"In":[41],"Data":[43,71,234],"RAM,":[44,72,139,235],"integrating":[46],"SOT-MRAM,":[47,147,165],"HARD":[48,193],"increases":[49],"cache":[50,117,225,241],"capacity":[51,226],"under":[52,227],"same":[54,229],"area":[55,230],"constraints,":[56],"effectively":[57],"alleviating":[58],"bottlenecks":[60],"caused":[61],"memory":[63],"access":[64,89,120,198],"latency.":[65],"To":[66,207],"better":[67],"manage":[68],"we":[73,148],"introduce":[74,149],"Dynamic":[76],"Least":[77],"Recently":[78],"Used":[79],"(Dynamic-LRU)":[80],"policy,":[81],"which":[82],"dynamically":[83],"adjusts":[84],"data":[85,93,101,197],"placement":[86],"based":[87],"on":[88,133],"patterns,":[90],"storing":[91],"access-intensive":[92],"in":[94,118,136,195,204,218],"SRAM":[96,163],"region":[97],"while":[98],"migrating":[99],"access-sparse":[100],"SOT-MRAM":[104],"region.":[105],"approach":[107],"not":[108],"only":[109],"ensures":[110],"last":[115],"level":[116],"high-speed":[119],"scenarios":[121],"but":[122],"also":[123,157],"optimizes":[124],"storage":[125],"resource":[126],"utilization":[127],"significantly":[129],"reduces":[130],"write":[131],"pressure":[132],"SOT-MRAM.":[134],"Furthermore,":[135],"address":[141],"read":[143],"disturbance":[144],"issue":[145],"readless":[151,174],"hierarchical":[152,171],"tag":[153],"structure.":[154],"structure":[156],"employs":[158],"heterogeneous":[160],"design":[161],"reducing":[166],"unnecessary":[167],"matching":[168],"operations":[169],"through":[170],"architecture":[172],"comparison":[175],"schemes,":[176],"thereby":[177],"lowering":[178],"energy":[179],"consumption":[180],"improving":[182],"RAM.":[188],"Experimental":[189],"results":[190],"demonstrate":[191],"that":[192],"excels":[194],"complex":[196],"scenarios,":[199],"achieving":[200],"40.6\u00d7":[202],"improvement":[203],"Mean":[205],"Time":[206],"Failure":[208],"(MTTF)":[209],"for":[210,232,243],"RAM":[213],"6.3%":[216],"reduction":[217],"miss":[219],"rate":[220],"attributed":[221],"increased":[224],"budget":[231],"offering":[236],"an":[237],"efficient":[238],"scalable":[240],"solution":[242],"high-performance":[244],"computer":[245],"architectures.":[246]},"counts_by_year":[],"updated_date":"2026-05-21T06:26:12.895304","created_date":"2025-10-22T00:00:00"}