{"id":"https://openalex.org/W4414693511","doi":"https://doi.org/10.1109/tcad.2025.3616073","title":"Vendor-Independent Design Space Exploration and Resource Optimization Framework for 3-D Networks-on-Chip Using Hypergraph-Genetic Algorithm Integration","display_name":"Vendor-Independent Design Space Exploration and Resource Optimization Framework for 3-D Networks-on-Chip Using Hypergraph-Genetic Algorithm Integration","publication_year":2025,"publication_date":"2025-10-01","ids":{"openalex":"https://openalex.org/W4414693511","doi":"https://doi.org/10.1109/tcad.2025.3616073"},"language":"en","primary_location":{"id":"doi:10.1109/tcad.2025.3616073","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tcad.2025.3616073","pdf_url":null,"source":{"id":"https://openalex.org/S100835903","display_name":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","issn_l":"0278-0070","issn":["0278-0070","1937-4151"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":true,"oa_status":"green","oa_url":"https://orcid.org/0000-0002-0820-5487","any_repository_has_fulltext":true},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5114690036","display_name":"Ahmed Al-Alousi","orcid":"https://orcid.org/0000-0002-3601-3642"},"institutions":[{"id":"https://openalex.org/I59433898","display_name":"Brunel University of London","ror":"https://ror.org/00dn4t376","country_code":"GB","type":"education","lineage":["https://openalex.org/I124357947","https://openalex.org/I59433898"]}],"countries":["GB"],"is_corresponding":false,"raw_author_name":"Ahmed Al-Alousi","raw_affiliation_strings":["Department of Electronic and Electrical Engineering, College of Engineering, Design and Physical Sciences, Brunel University of London, Uxbridge, U.K","Department of Electronic and Electrical Engineering, College of Engineering, Design and Physical Sciences, Brunel University of London, Uxbridge, United Kingdom"],"raw_orcid":"https://orcid.org/0000-0002-3601-3642","affiliations":[{"raw_affiliation_string":"Department of Electronic and Electrical Engineering, College of Engineering, Design and Physical Sciences, Brunel University of London, Uxbridge, U.K","institution_ids":["https://openalex.org/I59433898"]},{"raw_affiliation_string":"Department of Electronic and Electrical Engineering, College of Engineering, Design and Physical Sciences, Brunel University of London, Uxbridge, United Kingdom","institution_ids":["https://openalex.org/I59433898"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5026237130","display_name":"Maozhen Li","orcid":"https://orcid.org/0000-0002-0820-5487"},"institutions":[{"id":"https://openalex.org/I59433898","display_name":"Brunel University of London","ror":"https://ror.org/00dn4t376","country_code":"GB","type":"education","lineage":["https://openalex.org/I124357947","https://openalex.org/I59433898"]}],"countries":["GB"],"is_corresponding":false,"raw_author_name":"Maozhen Li","raw_affiliation_strings":["Department of Electronic and Electrical Engineering, College of Engineering, Design and Physical Sciences, Brunel University of London, Uxbridge, U.K","Department of Electronic and Electrical Engineering, College of Engineering, Design and Physical Sciences, Brunel University of London, Uxbridge, United Kingdom"],"raw_orcid":"https://orcid.org/0000-0002-0820-5487","affiliations":[{"raw_affiliation_string":"Department of Electronic and Electrical Engineering, College of Engineering, Design and Physical Sciences, Brunel University of London, Uxbridge, U.K","institution_ids":["https://openalex.org/I59433898"]},{"raw_affiliation_string":"Department of Electronic and Electrical Engineering, College of Engineering, Design and Physical Sciences, Brunel University of London, Uxbridge, United Kingdom","institution_ids":["https://openalex.org/I59433898"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5108055798","display_name":"Hongying Meng","orcid":"https://orcid.org/0000-0002-8836-1382"},"institutions":[{"id":"https://openalex.org/I59433898","display_name":"Brunel University of London","ror":"https://ror.org/00dn4t376","country_code":"GB","type":"education","lineage":["https://openalex.org/I124357947","https://openalex.org/I59433898"]}],"countries":["GB"],"is_corresponding":false,"raw_author_name":"Hongying Meng","raw_affiliation_strings":["Department of Electronic and Electrical Engineering, College of Engineering, Design and Physical Sciences, Brunel University of London, Uxbridge, U.K","Department of Electronic and Electrical Engineering, College of Engineering, Design and Physical Sciences, Brunel University of London, Uxbridge, United Kingdom"],"raw_orcid":"https://orcid.org/0000-0002-8836-1382","affiliations":[{"raw_affiliation_string":"Department of Electronic and Electrical Engineering, College of Engineering, Design and Physical Sciences, Brunel University of London, Uxbridge, U.K","institution_ids":["https://openalex.org/I59433898"]},{"raw_affiliation_string":"Department of Electronic and Electrical Engineering, College of Engineering, Design and Physical Sciences, Brunel University of London, Uxbridge, United Kingdom","institution_ids":["https://openalex.org/I59433898"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":[],"corresponding_institution_ids":["https://openalex.org/I59433898"],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":0,"citation_normalized_percentile":{"value":0.28415174,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":"45","issue":"5","first_page":"2236","last_page":"2248"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.996999979019165,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.996999979019165,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9850000143051147,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9746000170707703,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/design-space-exploration","display_name":"Design space exploration","score":0.7502999901771545},{"id":"https://openalex.org/keywords/scalability","display_name":"Scalability","score":0.6541000008583069},{"id":"https://openalex.org/keywords/resource","display_name":"Resource (disambiguation)","score":0.47380000352859497},{"id":"https://openalex.org/keywords/key","display_name":"Key (lock)","score":0.4650999903678894},{"id":"https://openalex.org/keywords/network-topology","display_name":"Network topology","score":0.4499000012874603},{"id":"https://openalex.org/keywords/routing","display_name":"Routing (electronic design automation)","score":0.41999998688697815},{"id":"https://openalex.org/keywords/space-exploration","display_name":"Space exploration","score":0.4146000146865845},{"id":"https://openalex.org/keywords/reduction","display_name":"Reduction (mathematics)","score":0.39640000462532043},{"id":"https://openalex.org/keywords/genetic-algorithm","display_name":"Genetic algorithm","score":0.37529999017715454}],"concepts":[{"id":"https://openalex.org/C2776221188","wikidata":"https://www.wikidata.org/wiki/Q21072556","display_name":"Design space exploration","level":2,"score":0.7502999901771545},{"id":"https://openalex.org/C48044578","wikidata":"https://www.wikidata.org/wiki/Q727490","display_name":"Scalability","level":2,"score":0.6541000008583069},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6093999743461609},{"id":"https://openalex.org/C206345919","wikidata":"https://www.wikidata.org/wiki/Q20380951","display_name":"Resource (disambiguation)","level":2,"score":0.47380000352859497},{"id":"https://openalex.org/C26517878","wikidata":"https://www.wikidata.org/wiki/Q228039","display_name":"Key (lock)","level":2,"score":0.4650999903678894},{"id":"https://openalex.org/C199845137","wikidata":"https://www.wikidata.org/wiki/Q145490","display_name":"Network topology","level":2,"score":0.4499000012874603},{"id":"https://openalex.org/C74172769","wikidata":"https://www.wikidata.org/wiki/Q1446839","display_name":"Routing (electronic design automation)","level":2,"score":0.41999998688697815},{"id":"https://openalex.org/C120314980","wikidata":"https://www.wikidata.org/wiki/Q180634","display_name":"Distributed computing","level":1,"score":0.4163999855518341},{"id":"https://openalex.org/C104060986","wikidata":"https://www.wikidata.org/wiki/Q180046","display_name":"Space exploration","level":2,"score":0.4146000146865845},{"id":"https://openalex.org/C111335779","wikidata":"https://www.wikidata.org/wiki/Q3454686","display_name":"Reduction (mathematics)","level":2,"score":0.39640000462532043},{"id":"https://openalex.org/C8880873","wikidata":"https://www.wikidata.org/wiki/Q187787","display_name":"Genetic algorithm","level":2,"score":0.37529999017715454},{"id":"https://openalex.org/C26713055","wikidata":"https://www.wikidata.org/wiki/Q245962","display_name":"Implementation","level":2,"score":0.36899998784065247},{"id":"https://openalex.org/C100776233","wikidata":"https://www.wikidata.org/wiki/Q2532492","display_name":"Bridge (graph theory)","level":2,"score":0.3483000099658966},{"id":"https://openalex.org/C139807058","wikidata":"https://www.wikidata.org/wiki/Q352374","display_name":"Adaptation (eye)","level":2,"score":0.34779998660087585},{"id":"https://openalex.org/C43214815","wikidata":"https://www.wikidata.org/wiki/Q7310987","display_name":"Reliability (semiconductor)","level":3,"score":0.34310001134872437},{"id":"https://openalex.org/C106516650","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm design","level":2,"score":0.328000009059906},{"id":"https://openalex.org/C113775141","wikidata":"https://www.wikidata.org/wiki/Q428691","display_name":"Computer engineering","level":1,"score":0.30730000138282776},{"id":"https://openalex.org/C128519102","wikidata":"https://www.wikidata.org/wiki/Q339554","display_name":"Network on a chip","level":2,"score":0.29910001158714294},{"id":"https://openalex.org/C159149176","wikidata":"https://www.wikidata.org/wiki/Q14489129","display_name":"Evolutionary algorithm","level":2,"score":0.29899999499320984},{"id":"https://openalex.org/C163258240","wikidata":"https://www.wikidata.org/wiki/Q25342","display_name":"Power (physics)","level":2,"score":0.29269999265670776},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.2809000015258789},{"id":"https://openalex.org/C127705205","wikidata":"https://www.wikidata.org/wiki/Q5748245","display_name":"Heuristics","level":2,"score":0.27390000224113464},{"id":"https://openalex.org/C2778820799","wikidata":"https://www.wikidata.org/wiki/Q3454688","display_name":"Cost reduction","level":2,"score":0.26759999990463257},{"id":"https://openalex.org/C2778572836","wikidata":"https://www.wikidata.org/wiki/Q380933","display_name":"Space (punctuation)","level":2,"score":0.2590000033378601},{"id":"https://openalex.org/C125583679","wikidata":"https://www.wikidata.org/wiki/Q755673","display_name":"Search algorithm","level":2,"score":0.2551000118255615},{"id":"https://openalex.org/C201995342","wikidata":"https://www.wikidata.org/wiki/Q682496","display_name":"Systems engineering","level":1,"score":0.2533999979496002}],"mesh":[],"locations_count":2,"locations":[{"id":"doi:10.1109/tcad.2025.3616073","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tcad.2025.3616073","pdf_url":null,"source":{"id":"https://openalex.org/S100835903","display_name":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","issn_l":"0278-0070","issn":["0278-0070","1937-4151"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","raw_type":"journal-article"},{"id":"pmh:oai:bura.brunel.ac.uk:2438/32055","is_oa":true,"landing_page_url":"https://orcid.org/0000-0002-0820-5487","pdf_url":null,"source":{"id":"https://openalex.org/S4306401473","display_name":"Brunel University Research Archive (BURA) (Brunel University London)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I59433898","host_organization_name":"Brunel University of London","host_organization_lineage":["https://openalex.org/I59433898"],"host_organization_lineage_names":[],"type":"repository"},"license":"cc-by","license_id":"https://openalex.org/licenses/cc-by","version":"acceptedVersion","is_accepted":true,"is_published":false,"raw_source_name":null,"raw_type":"Article"}],"best_oa_location":{"id":"pmh:oai:bura.brunel.ac.uk:2438/32055","is_oa":true,"landing_page_url":"https://orcid.org/0000-0002-0820-5487","pdf_url":null,"source":{"id":"https://openalex.org/S4306401473","display_name":"Brunel University Research Archive (BURA) (Brunel University London)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I59433898","host_organization_name":"Brunel University of London","host_organization_lineage":["https://openalex.org/I59433898"],"host_organization_lineage_names":[],"type":"repository"},"license":"cc-by","license_id":"https://openalex.org/licenses/cc-by","version":"acceptedVersion","is_accepted":true,"is_published":false,"raw_source_name":null,"raw_type":"Article"},"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":0,"referenced_works":[],"related_works":[],"abstract_inverted_index":{"This":[0],"paper":[1],"presents":[2],"a":[3,47],"novel":[4],"methodology":[5],"for":[6,50,84,135],"design":[7,40],"space":[8,41],"exploration":[9],"and":[10,22,70,77,111,138,149],"resource":[11],"optimisation":[12],"of":[13,42,59,67],"three-dimensional":[14],"Networks-on-Chip":[15],"(3D":[16],"NoC)":[17],"architectures":[18,99],"using":[19],"hypergraph":[20],"modelling":[21],"genetic":[23],"algorithms.":[24],"The":[25,53],"proposed":[26],"approach":[27],"combines":[28],"mathematical":[29],"rigour":[30],"with":[31,80,97],"evolutionary":[32],"search":[33],"capabilities":[34],"to":[35,74,102,118],"efficiently":[36],"explore":[37],"the":[38,57,131],"vast":[39],"3D":[43],"NoC":[44,51,140],"configurations,":[45],"providing":[46],"vendor-independent":[48],"solution":[49],"architects.":[52],"key":[54],"contribution":[55],"is":[56],"development":[58],"Performance-Cost-Ratio":[60],"(PCR)":[61],"functions":[62],"that":[63],"enable":[64],"quantitative":[65],"evaluation":[66],"different":[68],"topologies":[69],"routing":[71],"algorithms,":[72],"extended":[73],"include":[75],"power":[76,115],"thermal":[78],"considerations":[79],"dynamic":[81],"adaptation":[82],"mechanisms":[83],"runtime":[85],"traffic":[86],"variations.":[87],"Validation":[88,121],"through":[89],"four":[90],"compute-intensive":[91],"use":[92],"cases":[93],"demonstrates":[94],"significant":[95],"improvements,":[96],"optimised":[98],"achieving":[100],"up":[101],"33%":[103],"reduction":[104,113],"in":[105,109,114],"latency,":[106],"40%":[107],"increase":[108],"throughput,":[110],"30%":[112],"consumption":[116],"compared":[117],"baseline":[119],"implementations.":[120],"against":[122],"published":[123],"silicon":[124],"implementations":[125],"shows":[126],"92-96%":[127],"correlation":[128],"accuracy,":[129],"confirming":[130],"framework\u2019s":[132],"practical":[133],"applicability":[134],"developing":[136],"efficient":[137],"scalable":[139],"solutions":[141],"as":[142],"processor":[143],"designs":[144],"advance":[145],"towards":[146],"kilo-core":[147],"scales":[148],"beyond.":[150]},"counts_by_year":[],"updated_date":"2026-04-23T06:14:38.165362","created_date":"2025-10-10T00:00:00"}
