{"id":"https://openalex.org/W4414221768","doi":"https://doi.org/10.1109/tcad.2025.3608647","title":"Modeling Techniques for the Formal Verification of Integrated Circuits at Transistor-Level: Performance Versus Precision Tradeoffs","display_name":"Modeling Techniques for the Formal Verification of Integrated Circuits at Transistor-Level: Performance Versus Precision Tradeoffs","publication_year":2025,"publication_date":"2025-09-10","ids":{"openalex":"https://openalex.org/W4414221768","doi":"https://doi.org/10.1109/tcad.2025.3608647"},"language":"en","primary_location":{"id":"doi:10.1109/tcad.2025.3608647","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tcad.2025.3608647","pdf_url":null,"source":{"id":"https://openalex.org/S100835903","display_name":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","issn_l":"0278-0070","issn":["0278-0070","1937-4151"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":true,"oa_status":"green","oa_url":"https://hal.science/hal-05290989","any_repository_has_fulltext":true},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5000892488","display_name":"Oussama Oulkaid","orcid":"https://orcid.org/0000-0002-0838-3355"},"institutions":[{"id":"https://openalex.org/I100532134","display_name":"Universit\u00e9 Claude Bernard Lyon 1","ror":"https://ror.org/029brtt94","country_code":"FR","type":"education","lineage":["https://openalex.org/I100532134","https://openalex.org/I203339264"]},{"id":"https://openalex.org/I113428412","display_name":"\u00c9cole Normale Sup\u00e9rieure de Lyon","ror":"https://ror.org/04zmssz18","country_code":"FR","type":"education","lineage":["https://openalex.org/I113428412","https://openalex.org/I203339264"]},{"id":"https://openalex.org/I1294671590","display_name":"Centre National de la Recherche Scientifique","ror":"https://ror.org/02feahw73","country_code":"FR","type":"government","lineage":["https://openalex.org/I1294671590"]}],"countries":["FR"],"is_corresponding":false,"raw_author_name":"Oussama Oulkaid","raw_affiliation_strings":["Universit&#x00E9; Claude Bernard Lyon 1, CNRS, ENS de Lyon, Inria, LIP, UMR 5668, Lyon cedex 07, France","Univ. Lyon, EnsL, UCBL, CNRS, Inria, LIP, LYON Cedex 07, France"],"raw_orcid":"https://orcid.org/0000-0002-0838-3355","affiliations":[{"raw_affiliation_string":"Universit&#x00E9; Claude Bernard Lyon 1, CNRS, ENS de Lyon, Inria, LIP, UMR 5668, Lyon cedex 07, France","institution_ids":["https://openalex.org/I100532134","https://openalex.org/I113428412","https://openalex.org/I1294671590"]},{"raw_affiliation_string":"Univ. Lyon, EnsL, UCBL, CNRS, Inria, LIP, LYON Cedex 07, France","institution_ids":["https://openalex.org/I113428412","https://openalex.org/I100532134","https://openalex.org/I1294671590"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5037620785","display_name":"Bruno Ferres","orcid":"https://orcid.org/0000-0001-8426-6516"},"institutions":[{"id":"https://openalex.org/I106785703","display_name":"Institut polytechnique de Grenoble","ror":"https://ror.org/05sbt2524","country_code":"FR","type":"education","lineage":["https://openalex.org/I106785703","https://openalex.org/I899635006"]},{"id":"https://openalex.org/I1294671590","display_name":"Centre National de la Recherche Scientifique","ror":"https://ror.org/02feahw73","country_code":"FR","type":"government","lineage":["https://openalex.org/I1294671590"]},{"id":"https://openalex.org/I899635006","display_name":"Universit\u00e9 Grenoble Alpes","ror":"https://ror.org/02rx3b187","country_code":"FR","type":"education","lineage":["https://openalex.org/I899635006"]}],"countries":["FR"],"is_corresponding":false,"raw_author_name":"Bruno Ferres","raw_affiliation_strings":["Univ. Grenoble Alpes, CNRS, Grenoble INP-Institute of Engineering, VERIMAG, Grenoble, France","Univ. Grenoble Alpes, CNRS, Grenoble INP&#x002A;, VERIMAG, Grenoble, France"],"raw_orcid":"https://orcid.org/0000-0001-8426-6516","affiliations":[{"raw_affiliation_string":"Univ. Grenoble Alpes, CNRS, Grenoble INP-Institute of Engineering, VERIMAG, Grenoble, France","institution_ids":["https://openalex.org/I1294671590","https://openalex.org/I899635006","https://openalex.org/I106785703"]},{"raw_affiliation_string":"Univ. Grenoble Alpes, CNRS, Grenoble INP&#x002A;, VERIMAG, Grenoble, France","institution_ids":["https://openalex.org/I1294671590","https://openalex.org/I899635006","https://openalex.org/I106785703"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5061125211","display_name":"Matthieu Moy","orcid":"https://orcid.org/0000-0002-6054-8882"},"institutions":[{"id":"https://openalex.org/I100532134","display_name":"Universit\u00e9 Claude Bernard Lyon 1","ror":"https://ror.org/029brtt94","country_code":"FR","type":"education","lineage":["https://openalex.org/I100532134","https://openalex.org/I203339264"]},{"id":"https://openalex.org/I113428412","display_name":"\u00c9cole Normale Sup\u00e9rieure de Lyon","ror":"https://ror.org/04zmssz18","country_code":"FR","type":"education","lineage":["https://openalex.org/I113428412","https://openalex.org/I203339264"]},{"id":"https://openalex.org/I1294671590","display_name":"Centre National de la Recherche Scientifique","ror":"https://ror.org/02feahw73","country_code":"FR","type":"government","lineage":["https://openalex.org/I1294671590"]}],"countries":["FR"],"is_corresponding":false,"raw_author_name":"Matthieu Moy","raw_affiliation_strings":["Universit&#x00E9; Claude Bernard Lyon 1, CNRS, ENS de Lyon, Inria, LIP, UMR 5668, Lyon cedex 07, France","Univ. Lyon, EnsL, UCBL, CNRS, Inria, LIP, LYON Cedex 07, France"],"raw_orcid":"https://orcid.org/0000-0002-6054-8882","affiliations":[{"raw_affiliation_string":"Universit&#x00E9; Claude Bernard Lyon 1, CNRS, ENS de Lyon, Inria, LIP, UMR 5668, Lyon cedex 07, France","institution_ids":["https://openalex.org/I100532134","https://openalex.org/I113428412","https://openalex.org/I1294671590"]},{"raw_affiliation_string":"Univ. Lyon, EnsL, UCBL, CNRS, Inria, LIP, LYON Cedex 07, France","institution_ids":["https://openalex.org/I113428412","https://openalex.org/I100532134","https://openalex.org/I1294671590"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5002817720","display_name":"Pascal Raymond","orcid":"https://orcid.org/0000-0003-3876-9125"},"institutions":[{"id":"https://openalex.org/I106785703","display_name":"Institut polytechnique de Grenoble","ror":"https://ror.org/05sbt2524","country_code":"FR","type":"education","lineage":["https://openalex.org/I106785703","https://openalex.org/I899635006"]},{"id":"https://openalex.org/I1294671590","display_name":"Centre National de la Recherche Scientifique","ror":"https://ror.org/02feahw73","country_code":"FR","type":"government","lineage":["https://openalex.org/I1294671590"]},{"id":"https://openalex.org/I899635006","display_name":"Universit\u00e9 Grenoble Alpes","ror":"https://ror.org/02rx3b187","country_code":"FR","type":"education","lineage":["https://openalex.org/I899635006"]}],"countries":["FR"],"is_corresponding":false,"raw_author_name":"Pascal Raymond","raw_affiliation_strings":["Univ. Grenoble Alpes, CNRS, Grenoble INP-Institute of Engineering, VERIMAG, Grenoble, France","Univ. Grenoble Alpes, CNRS, Grenoble INP&#x002A;, VERIMAG, Grenoble, France"],"raw_orcid":"https://orcid.org/0000-0003-3876-9125","affiliations":[{"raw_affiliation_string":"Univ. Grenoble Alpes, CNRS, Grenoble INP-Institute of Engineering, VERIMAG, Grenoble, France","institution_ids":["https://openalex.org/I1294671590","https://openalex.org/I899635006","https://openalex.org/I106785703"]},{"raw_affiliation_string":"Univ. Grenoble Alpes, CNRS, Grenoble INP&#x002A;, VERIMAG, Grenoble, France","institution_ids":["https://openalex.org/I1294671590","https://openalex.org/I899635006","https://openalex.org/I106785703"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5005392690","display_name":"Mehdi Khosravian Ghadikolaei","orcid":"https://orcid.org/0000-0002-8482-1521"},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Mehdi Khosravian Ghadikolaei","raw_affiliation_strings":["Aniah, Grenoble, France"],"raw_orcid":"https://orcid.org/0000-0002-8482-1521","affiliations":[{"raw_affiliation_string":"Aniah, Grenoble, France","institution_ids":[]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":5,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":0,"citation_normalized_percentile":{"value":0.23457041,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":"45","issue":"4","first_page":"1852","last_page":"1866"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9980000257492065,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9980000257492065,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T14117","display_name":"Integrated Circuits and Semiconductor Failure Analysis","score":0.9901000261306763,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11338","display_name":"Advancements in Photolithography Techniques","score":0.9858999848365784,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/satisfiability-modulo-theories","display_name":"Satisfiability modulo theories","score":0.570900022983551},{"id":"https://openalex.org/keywords/formal-equivalence-checking","display_name":"Formal equivalence checking","score":0.5044000148773193},{"id":"https://openalex.org/keywords/integrated-circuit","display_name":"Integrated circuit","score":0.49219998717308044},{"id":"https://openalex.org/keywords/formal-verification","display_name":"Formal verification","score":0.46560001373291016},{"id":"https://openalex.org/keywords/semantics","display_name":"Semantics (computer science)","score":0.4366999864578247},{"id":"https://openalex.org/keywords/state","display_name":"State (computer science)","score":0.4196999967098236},{"id":"https://openalex.org/keywords/electronic-circuit","display_name":"Electronic circuit","score":0.39590001106262207},{"id":"https://openalex.org/keywords/modulo","display_name":"Modulo","score":0.3912999927997589},{"id":"https://openalex.org/keywords/circuit-design","display_name":"Circuit design","score":0.3797999918460846}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7314000129699707},{"id":"https://openalex.org/C164155591","wikidata":"https://www.wikidata.org/wiki/Q2067766","display_name":"Satisfiability modulo theories","level":2,"score":0.570900022983551},{"id":"https://openalex.org/C96654402","wikidata":"https://www.wikidata.org/wiki/Q5469962","display_name":"Formal equivalence checking","level":3,"score":0.5044000148773193},{"id":"https://openalex.org/C530198007","wikidata":"https://www.wikidata.org/wiki/Q80831","display_name":"Integrated circuit","level":2,"score":0.49219998717308044},{"id":"https://openalex.org/C111498074","wikidata":"https://www.wikidata.org/wiki/Q173326","display_name":"Formal verification","level":2,"score":0.46560001373291016},{"id":"https://openalex.org/C113775141","wikidata":"https://www.wikidata.org/wiki/Q428691","display_name":"Computer engineering","level":1,"score":0.45159998536109924},{"id":"https://openalex.org/C184337299","wikidata":"https://www.wikidata.org/wiki/Q1437428","display_name":"Semantics (computer science)","level":2,"score":0.4366999864578247},{"id":"https://openalex.org/C48103436","wikidata":"https://www.wikidata.org/wiki/Q599031","display_name":"State (computer science)","level":2,"score":0.4196999967098236},{"id":"https://openalex.org/C134146338","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Electronic circuit","level":2,"score":0.39590001106262207},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.39570000767707825},{"id":"https://openalex.org/C54732982","wikidata":"https://www.wikidata.org/wiki/Q1415345","display_name":"Modulo","level":2,"score":0.3912999927997589},{"id":"https://openalex.org/C190560348","wikidata":"https://www.wikidata.org/wiki/Q3245116","display_name":"Circuit design","level":2,"score":0.3797999918460846},{"id":"https://openalex.org/C172385210","wikidata":"https://www.wikidata.org/wiki/Q5339","display_name":"Transistor","level":3,"score":0.34060001373291016},{"id":"https://openalex.org/C62907940","wikidata":"https://www.wikidata.org/wiki/Q1541329","display_name":"Mixed-signal integrated circuit","level":3,"score":0.33160001039505005},{"id":"https://openalex.org/C26490066","wikidata":"https://www.wikidata.org/wiki/Q17006835","display_name":"Circuit extraction","level":4,"score":0.3296000063419342},{"id":"https://openalex.org/C6943359","wikidata":"https://www.wikidata.org/wiki/Q875276","display_name":"Boolean satisfiability problem","level":2,"score":0.3255999982357025},{"id":"https://openalex.org/C80444323","wikidata":"https://www.wikidata.org/wiki/Q2878974","display_name":"Theoretical computer science","level":1,"score":0.321399986743927},{"id":"https://openalex.org/C110251889","wikidata":"https://www.wikidata.org/wiki/Q1569697","display_name":"Model checking","level":2,"score":0.3125},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.3059000074863434},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.3034000098705292},{"id":"https://openalex.org/C187455244","wikidata":"https://www.wikidata.org/wiki/Q942353","display_name":"Boolean function","level":2,"score":0.30309998989105225},{"id":"https://openalex.org/C75606506","wikidata":"https://www.wikidata.org/wiki/Q1049183","display_name":"Formal methods","level":2,"score":0.30250000953674316},{"id":"https://openalex.org/C72434380","wikidata":"https://www.wikidata.org/wiki/Q230930","display_name":"State space","level":2,"score":0.2939999997615814},{"id":"https://openalex.org/C81843906","wikidata":"https://www.wikidata.org/wiki/Q173156","display_name":"Digital electronics","level":3,"score":0.2883000075817108},{"id":"https://openalex.org/C188817802","wikidata":"https://www.wikidata.org/wiki/Q13426855","display_name":"Physical design","level":3,"score":0.27570000290870667},{"id":"https://openalex.org/C146499914","wikidata":"https://www.wikidata.org/wiki/Q5469969","display_name":"Formal semantics (linguistics)","level":2,"score":0.26269999146461487},{"id":"https://openalex.org/C138331895","wikidata":"https://www.wikidata.org/wiki/Q11650","display_name":"Electronics","level":2,"score":0.2612000107765198},{"id":"https://openalex.org/C23572009","wikidata":"https://www.wikidata.org/wiki/Q964981","display_name":"Equivalent circuit","level":3,"score":0.26030001044273376},{"id":"https://openalex.org/C62460635","wikidata":"https://www.wikidata.org/wiki/Q5508853","display_name":"Functional verification","level":3,"score":0.2567000091075897}],"mesh":[],"locations_count":2,"locations":[{"id":"doi:10.1109/tcad.2025.3608647","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tcad.2025.3608647","pdf_url":null,"source":{"id":"https://openalex.org/S100835903","display_name":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","issn_l":"0278-0070","issn":["0278-0070","1937-4151"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","raw_type":"journal-article"},{"id":"pmh:oai:HAL:hal-05290989v1","is_oa":true,"landing_page_url":"https://hal.science/hal-05290989","pdf_url":null,"source":{"id":"https://openalex.org/S4306402512","display_name":"HAL (Le Centre pour la Communication Scientifique Directe)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I1294671590","host_organization_name":"Centre National de la Recherche Scientifique","host_organization_lineage":["https://openalex.org/I1294671590"],"host_organization_lineage_names":[],"type":"repository"},"license":"other-oa","license_id":"https://openalex.org/licenses/other-oa","version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2025, &#x27E8;10.1109/TCAD.2025.3608647&#x27E9;","raw_type":"Journal articles"}],"best_oa_location":{"id":"pmh:oai:HAL:hal-05290989v1","is_oa":true,"landing_page_url":"https://hal.science/hal-05290989","pdf_url":null,"source":{"id":"https://openalex.org/S4306402512","display_name":"HAL (Le Centre pour la Communication Scientifique Directe)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I1294671590","host_organization_name":"Centre National de la Recherche Scientifique","host_organization_lineage":["https://openalex.org/I1294671590"],"host_organization_lineage_names":[],"type":"repository"},"license":"other-oa","license_id":"https://openalex.org/licenses/other-oa","version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2025, &#x27E8;10.1109/TCAD.2025.3608647&#x27E9;","raw_type":"Journal articles"},"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":0,"referenced_works":[],"related_works":[],"abstract_inverted_index":{"The":[0],"behavior":[1],"of":[2,27,54,90,110,158,169,176],"any":[3],"electronic":[4],"system":[5],"can":[6,37,50,62,72],"be":[7,38,73,96],"traced":[8],"back":[9],"to":[10,57,85,123,185],"how":[11,24],"its":[12],"constituting":[13],"components":[14],"physically":[15,32],"interact":[16],"with":[17],"each":[18],"other.":[19],"Such":[20],"low-level":[21],"interactions":[22],"explain":[23],"specific":[25,166],"states":[26,36],"a":[28,42,65,83,116,159],"given":[29,66],"circuit":[30,35,79,92,129,180,197],"are":[31,183],"possible.":[33],"Some":[34],"erroneous,":[39],"e.g.,":[40],"applying":[41],"voltage":[43],"stress":[44],"greater":[45],"than":[46],"what":[47],"some":[48,78],"device":[49],"tolerate.":[51],"It":[52],"is":[53],"particular":[55],"importance":[56],"know":[58],"whether":[59],"such":[60],"errors":[61,76],"happen":[63],"on":[64,120],"circuit,":[67],"so":[68],"that":[69,182],"required":[70],"corrections":[71],"made.":[74],"Identifying":[75],"requires":[77],"modeling":[80],"technique,":[81],"and":[82,114,137,141,201],"way":[84],"explore":[86],"the":[87,91,108,174,177,195],"state":[88],"space":[89],"model":[93],"(which":[94],"may":[95],"very":[97],"large":[98],"if":[99],"at":[100],"all":[101],"finite).":[102],"In":[103],"this":[104],"work,":[105],"we":[106,172],"show":[107],"limitations":[109],"classical":[111],"verification":[112,154],"techniques,":[113],"propose":[115,127],"new":[117,128],"approach":[118],"based":[119],"formal":[121],"methods":[122],"overcome":[124],"them.":[125],"We":[126,147,189],"semantics":[130],"for":[131,179],"transistor-level":[132],"descriptions":[133],"from":[134],"(1)":[135],"recalling":[136],"improving":[138],"existing":[139],"semantics,":[140,198],"(2)":[142],"introducing":[143],"novel":[144],"alternate":[145],"ones.":[146],"then":[148],"demonstrate":[149],"their":[150],"usage":[151],"in":[152],"our":[153],"framework\u2014which":[155],"makes":[156],"use":[157],"satisfiability":[160],"modulo":[161],"theories":[162],"(SMT)":[163],"solver\u2014to":[164],"verify":[165],"electric":[167],"properties":[168],"circuits.":[170],"Specifically,":[171],"address":[173],"problem":[175],"search":[178],"transistors":[181],"subject":[184],"electrical":[186],"overstress":[187],"(EOS).":[188],"draw":[190],"interesting":[191],"conclusions":[192],"by":[193],"comparing":[194],"presented":[196],"both":[199],"formally":[200],"via":[202],"experimental":[203],"benchmarks.":[204]},"counts_by_year":[],"updated_date":"2026-06-11T09:08:48.828518","created_date":"2025-10-10T00:00:00"}
