{"id":"https://openalex.org/W7080318058","doi":"https://doi.org/10.1109/tcad.2025.3607152","title":"A Reliable ESD 3D-Integrated Design and Simulation (3D-IDS) Methodology for Wafer-on-Wafer Stacked DRAM","display_name":"A Reliable ESD 3D-Integrated Design and Simulation (3D-IDS) Methodology for Wafer-on-Wafer Stacked DRAM","publication_year":2025,"publication_date":"2025-09-08","ids":{"openalex":"https://openalex.org/W7080318058","doi":"https://doi.org/10.1109/tcad.2025.3607152"},"language":"en","primary_location":{"id":"doi:10.1109/tcad.2025.3607152","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tcad.2025.3607152","pdf_url":null,"source":{"id":"https://openalex.org/S100835903","display_name":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","issn_l":"0278-0070","issn":["0278-0070","1937-4151"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":null,"display_name":"Xuerong Jia","orcid":"https://orcid.org/0009-0001-6652-1859"},"institutions":[{"id":"https://openalex.org/I87445476","display_name":"Xi'an Jiaotong University","ror":"https://ror.org/017zhmm22","country_code":"CN","type":"education","lineage":["https://openalex.org/I87445476"]}],"countries":["CN"],"is_corresponding":true,"raw_author_name":"Xuerong Jia","raw_affiliation_strings":["School of Microelectronics and Faculty of Electronic and Information Engineering, Xi&#x2019;an Jiaotong University, Xi&#x2019;an, Shannxi, China"],"affiliations":[{"raw_affiliation_string":"School of Microelectronics and Faculty of Electronic and Information Engineering, Xi&#x2019;an Jiaotong University, Xi&#x2019;an, Shannxi, China","institution_ids":["https://openalex.org/I87445476"]}]},{"author_position":"middle","author":{"id":null,"display_name":"Song Wang","orcid":"https://orcid.org/0000-0002-7682-5987"},"institutions":[{"id":"https://openalex.org/I4210148388","display_name":"Xi'an UniIC Semiconductors (China)","ror":"https://ror.org/04c99ac72","country_code":"CN","type":"company","lineage":["https://openalex.org/I4210148388"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Song Wang","raw_affiliation_strings":["Xi&#x2019;an UniIC Semiconductors Company Ltd., Xi&#x2019;an, China"],"affiliations":[{"raw_affiliation_string":"Xi&#x2019;an UniIC Semiconductors Company Ltd., Xi&#x2019;an, China","institution_ids":["https://openalex.org/I4210148388"]}]},{"author_position":"middle","author":{"id":null,"display_name":"Yixin Guo","orcid":"https://orcid.org/0000-0001-8887-595X"},"institutions":[{"id":"https://openalex.org/I4210148388","display_name":"Xi'an UniIC Semiconductors (China)","ror":"https://ror.org/04c99ac72","country_code":"CN","type":"company","lineage":["https://openalex.org/I4210148388"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Yixin Guo","raw_affiliation_strings":["Xi&#x2019;an UniIC Semiconductors Company Ltd., Xi&#x2019;an, China"],"affiliations":[{"raw_affiliation_string":"Xi&#x2019;an UniIC Semiconductors Company Ltd., Xi&#x2019;an, China","institution_ids":["https://openalex.org/I4210148388"]}]},{"author_position":"middle","author":{"id":null,"display_name":"Fujun Bai","orcid":"https://orcid.org/0000-0002-7971-5986"},"institutions":[{"id":"https://openalex.org/I87445476","display_name":"Xi'an Jiaotong University","ror":"https://ror.org/017zhmm22","country_code":"CN","type":"education","lineage":["https://openalex.org/I87445476"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Fujun Bai","raw_affiliation_strings":["School of Microelectronics and Faculty of Electronic and Information Engineering, Xi&#x2019;an Jiaotong University, Xi&#x2019;an, Shannxi, China"],"affiliations":[{"raw_affiliation_string":"School of Microelectronics and Faculty of Electronic and Information Engineering, Xi&#x2019;an Jiaotong University, Xi&#x2019;an, Shannxi, China","institution_ids":["https://openalex.org/I87445476"]}]},{"author_position":"middle","author":{"id":null,"display_name":"Bing Yu","orcid":null},"institutions":[{"id":"https://openalex.org/I4210148388","display_name":"Xi'an UniIC Semiconductors (China)","ror":"https://ror.org/04c99ac72","country_code":"CN","type":"company","lineage":["https://openalex.org/I4210148388"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Bing Yu","raw_affiliation_strings":["Xi&#x2019;an UniIC Semiconductors Company Ltd., Xi&#x2019;an, China"],"affiliations":[{"raw_affiliation_string":"Xi&#x2019;an UniIC Semiconductors Company Ltd., Xi&#x2019;an, China","institution_ids":["https://openalex.org/I4210148388"]}]},{"author_position":"middle","author":{"id":null,"display_name":"Xiyuan Feng","orcid":null},"institutions":[{"id":"https://openalex.org/I4210148388","display_name":"Xi'an UniIC Semiconductors (China)","ror":"https://ror.org/04c99ac72","country_code":"CN","type":"company","lineage":["https://openalex.org/I4210148388"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Xiyuan Feng","raw_affiliation_strings":["Xi&#x2019;an UniIC Semiconductors Company Ltd., Xi&#x2019;an, China"],"affiliations":[{"raw_affiliation_string":"Xi&#x2019;an UniIC Semiconductors Company Ltd., Xi&#x2019;an, China","institution_ids":["https://openalex.org/I4210148388"]}]},{"author_position":"middle","author":{"id":null,"display_name":"Yi Liu","orcid":"https://orcid.org/0009-0001-0351-5259"},"institutions":[{"id":"https://openalex.org/I150229711","display_name":"University of Electronic Science and Technology of China","ror":"https://ror.org/04qr3zq92","country_code":"CN","type":"education","lineage":["https://openalex.org/I150229711"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Yi Liu","raw_affiliation_strings":["Center for Advanced Semiconductor and Integrated Micro-System, University of Electronic Science and Technology of China, Chengdu, China"],"affiliations":[{"raw_affiliation_string":"Center for Advanced Semiconductor and Integrated Micro-System, University of Electronic Science and Technology of China, Chengdu, China","institution_ids":["https://openalex.org/I150229711"]}]},{"author_position":"middle","author":{"id":null,"display_name":"Zhiwei Liu","orcid":"https://orcid.org/0000-0003-0805-5930"},"institutions":[{"id":"https://openalex.org/I150229711","display_name":"University of Electronic Science and Technology of China","ror":"https://ror.org/04qr3zq92","country_code":"CN","type":"education","lineage":["https://openalex.org/I150229711"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Zhiwei Liu","raw_affiliation_strings":["Center for Advanced Semiconductor and Integrated Micro-System, University of Electronic Science and Technology of China, Chengdu, China"],"affiliations":[{"raw_affiliation_string":"Center for Advanced Semiconductor and Integrated Micro-System, University of Electronic Science and Technology of China, Chengdu, China","institution_ids":["https://openalex.org/I150229711"]}]},{"author_position":"last","author":{"id":null,"display_name":"Li Geng","orcid":"https://orcid.org/0000-0003-4002-9281"},"institutions":[{"id":"https://openalex.org/I87445476","display_name":"Xi'an Jiaotong University","ror":"https://ror.org/017zhmm22","country_code":"CN","type":"education","lineage":["https://openalex.org/I87445476"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Li Geng","raw_affiliation_strings":["School of Microelectronics and Faculty of Electronic and Information Engineering, Xi&#x2019;an Jiaotong University, Xi&#x2019;an, Shannxi, China"],"affiliations":[{"raw_affiliation_string":"School of Microelectronics and Faculty of Electronic and Information Engineering, Xi&#x2019;an Jiaotong University, Xi&#x2019;an, Shannxi, China","institution_ids":["https://openalex.org/I87445476"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":9,"corresponding_author_ids":[],"corresponding_institution_ids":["https://openalex.org/I87445476"],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":0,"citation_normalized_percentile":{"value":0.50492602,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":"45","issue":"4","first_page":"1625","last_page":"1634"},"is_retracted":false,"is_paratext":false,"is_xpac":true,"primary_topic":{"id":"https://openalex.org/T12157","display_name":"Geochemistry and Geologic Mapping","score":0.7091000080108643,"subfield":{"id":"https://openalex.org/subfields/1702","display_name":"Artificial Intelligence"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T12157","display_name":"Geochemistry and Geologic Mapping","score":0.7091000080108643,"subfield":{"id":"https://openalex.org/subfields/1702","display_name":"Artificial Intelligence"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T13067","display_name":"Geological Modeling and Analysis","score":0.027400000020861626,"subfield":{"id":"https://openalex.org/subfields/1906","display_name":"Geochemistry and Petrology"},"field":{"id":"https://openalex.org/fields/19","display_name":"Earth and Planetary Sciences"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10271","display_name":"Seismic Imaging and Inversion Techniques","score":0.014999999664723873,"subfield":{"id":"https://openalex.org/subfields/1908","display_name":"Geophysics"},"field":{"id":"https://openalex.org/fields/19","display_name":"Earth and Planetary Sciences"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/electrostatic-discharge","display_name":"Electrostatic discharge","score":0.8252999782562256},{"id":"https://openalex.org/keywords/dram","display_name":"Dram","score":0.6757000088691711},{"id":"https://openalex.org/keywords/wafer","display_name":"Wafer","score":0.5907999873161316},{"id":"https://openalex.org/keywords/miniaturization","display_name":"Miniaturization","score":0.5769000053405762},{"id":"https://openalex.org/keywords/human-body-model","display_name":"Human-body model","score":0.5573999881744385},{"id":"https://openalex.org/keywords/interconnection","display_name":"Interconnection","score":0.5200999975204468},{"id":"https://openalex.org/keywords/reliability","display_name":"Reliability (semiconductor)","score":0.5097000002861023},{"id":"https://openalex.org/keywords/three-dimensional-integrated-circuit","display_name":"Three-dimensional integrated circuit","score":0.3684000074863434}],"concepts":[{"id":"https://openalex.org/C205483674","wikidata":"https://www.wikidata.org/wiki/Q3574961","display_name":"Electrostatic discharge","level":3,"score":0.8252999782562256},{"id":"https://openalex.org/C7366592","wikidata":"https://www.wikidata.org/wiki/Q1255620","display_name":"Dram","level":2,"score":0.6757000088691711},{"id":"https://openalex.org/C160671074","wikidata":"https://www.wikidata.org/wiki/Q267131","display_name":"Wafer","level":2,"score":0.5907999873161316},{"id":"https://openalex.org/C57528182","wikidata":"https://www.wikidata.org/wiki/Q1271842","display_name":"Miniaturization","level":2,"score":0.5769000053405762},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.5576000213623047},{"id":"https://openalex.org/C2781089380","wikidata":"https://www.wikidata.org/wiki/Q5936753","display_name":"Human-body model","level":2,"score":0.5573999881744385},{"id":"https://openalex.org/C123745756","wikidata":"https://www.wikidata.org/wiki/Q1665949","display_name":"Interconnection","level":2,"score":0.5200999975204468},{"id":"https://openalex.org/C43214815","wikidata":"https://www.wikidata.org/wiki/Q7310987","display_name":"Reliability (semiconductor)","level":3,"score":0.5097000002861023},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.4580000042915344},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.38589999079704285},{"id":"https://openalex.org/C59088047","wikidata":"https://www.wikidata.org/wiki/Q229370","display_name":"Three-dimensional integrated circuit","level":3,"score":0.3684000074863434},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.34049999713897705},{"id":"https://openalex.org/C44445679","wikidata":"https://www.wikidata.org/wiki/Q2538844","display_name":"Wafer testing","level":3,"score":0.33550000190734863},{"id":"https://openalex.org/C2779888857","wikidata":"https://www.wikidata.org/wiki/Q18378810","display_name":"Snapback","level":4,"score":0.3221000134944916},{"id":"https://openalex.org/C2984061966","wikidata":"https://www.wikidata.org/wiki/Q5157313","display_name":"Electromagnetic simulation","level":2,"score":0.3077999949455261},{"id":"https://openalex.org/C2983771295","wikidata":"https://www.wikidata.org/wiki/Q170519","display_name":"3d simulation","level":2,"score":0.29809999465942383},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.29440000653266907},{"id":"https://openalex.org/C555008776","wikidata":"https://www.wikidata.org/wiki/Q267298","display_name":"Battery (electricity)","level":3,"score":0.28940001130104065},{"id":"https://openalex.org/C530198007","wikidata":"https://www.wikidata.org/wiki/Q80831","display_name":"Integrated circuit","level":2,"score":0.28850001096725464},{"id":"https://openalex.org/C34929307","wikidata":"https://www.wikidata.org/wiki/Q845636","display_name":"Technology CAD","level":3,"score":0.2831000089645386},{"id":"https://openalex.org/C163258240","wikidata":"https://www.wikidata.org/wiki/Q25342","display_name":"Power (physics)","level":2,"score":0.2816999852657318},{"id":"https://openalex.org/C108882727","wikidata":"https://www.wikidata.org/wiki/Q2991685","display_name":"Solid modeling","level":2,"score":0.2809999883174896},{"id":"https://openalex.org/C129014197","wikidata":"https://www.wikidata.org/wiki/Q906544","display_name":"Power semiconductor device","level":3,"score":0.2596000134944916},{"id":"https://openalex.org/C45632049","wikidata":"https://www.wikidata.org/wiki/Q1578120","display_name":"Through-silicon via","level":3,"score":0.2547000050544739},{"id":"https://openalex.org/C74524168","wikidata":"https://www.wikidata.org/wiki/Q1074539","display_name":"Integrated circuit design","level":2,"score":0.250900000333786}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/tcad.2025.3607152","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tcad.2025.3607152","pdf_url":null,"source":{"id":"https://openalex.org/S100835903","display_name":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","issn_l":"0278-0070","issn":["0278-0070","1937-4151"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","raw_type":"journal-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":25,"referenced_works":["https://openalex.org/W616493952","https://openalex.org/W1966026370","https://openalex.org/W2031892903","https://openalex.org/W2091980860","https://openalex.org/W2100286024","https://openalex.org/W2136056669","https://openalex.org/W2142339929","https://openalex.org/W2155707315","https://openalex.org/W2186439979","https://openalex.org/W2328705515","https://openalex.org/W2538830844","https://openalex.org/W2764249358","https://openalex.org/W2790182603","https://openalex.org/W2805362231","https://openalex.org/W3013080934","https://openalex.org/W4280626531","https://openalex.org/W4285010435","https://openalex.org/W4285217154","https://openalex.org/W4285298545","https://openalex.org/W4311045766","https://openalex.org/W4366771711","https://openalex.org/W4385192563","https://openalex.org/W4386416005","https://openalex.org/W4395034968","https://openalex.org/W4403136431"],"related_works":[],"abstract_inverted_index":{"The":[0],"Electro-Static":[1,116],"Discharge":[2,117],"(ESD)":[3],"protection":[4,60,101,149],"design":[5,150],"and":[6,33,47,62,103,122,144,151],"verification":[7],"methodology":[8,140],"are":[9],"particularly":[10],"important":[11],"for":[12,51,147],"the":[13,22,28,34,74,115,129,136],"Wafer":[14,16],"on":[15],"(WoW)":[17],"stacked":[18,54,155],"system":[19],"due":[20],"to":[21],"miniaturization":[23],"of":[24,30,36,93],"vertical":[25,31,63,79],"interconnect":[26,64],"cells,":[27],"simplification":[29],"drivers,":[32],"complexity":[35],"3D":[37,53,69,83,86,94,106],"power":[38],"network.":[39,109],"This":[40,85,132],"paper":[41],"introduces":[42],"an":[43],"ESD":[44,59,70,87,95,100,138,148],"3D-Integrated":[45],"Design":[46],"Simulation":[48],"(3D-IDS)":[49],"Methodology":[50],"WoW":[52,82,154],"DRAM,":[55],"which":[56],"incorporates":[57],"customized":[58],"devices":[61,102],"models,":[65],"creating":[66],"a":[67,104,142],"comprehensive":[68,105],"discharging":[71,96],"network,":[72],"addressing":[73],"challenges":[75],"posed":[76],"by":[77],"high-density":[78],"connections":[80],"in":[81,153],"stacks.":[84],"network":[88],"encompasses":[89],"all":[90],"crucial":[91],"elements":[92],"paths,":[97],"including":[98],"on-chip":[99],"power/ground":[107],"discharge":[108],"Silicon":[110],"measurement":[111],"results":[112],"confirm":[113],"that":[114,135],"human":[118],"body":[119],"model":[120,125],"(HBM)":[121],"charged":[123],"device":[124],"(CDM)":[126],"limitations":[127],"corroborate":[128],"simulation":[130],"forecasts.":[131],"validation":[133],"confirms":[134],"proposed":[137],"3D-IDS":[139],"is":[141],"reliable":[143],"effective":[145],"approach":[146],"optimization":[152],"DRAM.":[156]},"counts_by_year":[],"updated_date":"2026-03-27T05:58:40.876381","created_date":"2025-10-10T00:00:00"}
