{"id":"https://openalex.org/W4409917223","doi":"https://doi.org/10.1109/tcad.2025.3565488","title":"A Novel HDL Code Generator for Effectively Testing FPGA Logic Synthesis Compilers","display_name":"A Novel HDL Code Generator for Effectively Testing FPGA Logic Synthesis Compilers","publication_year":2025,"publication_date":"2025-04-29","ids":{"openalex":"https://openalex.org/W4409917223","doi":"https://doi.org/10.1109/tcad.2025.3565488"},"language":"en","primary_location":{"id":"doi:10.1109/tcad.2025.3565488","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tcad.2025.3565488","pdf_url":null,"source":{"id":"https://openalex.org/S100835903","display_name":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","issn_l":"0278-0070","issn":["0278-0070","1937-4151"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5024881981","display_name":"Zhihao Xu","orcid":"https://orcid.org/0009-0008-2188-207X"},"institutions":[{"id":"https://openalex.org/I43313876","display_name":"Dalian Maritime University","ror":"https://ror.org/002b7nr53","country_code":"CN","type":"education","lineage":["https://openalex.org/I43313876"]},{"id":"https://openalex.org/I76569877","display_name":"Southeast University","ror":"https://ror.org/04ct4d772","country_code":"CN","type":"education","lineage":["https://openalex.org/I76569877"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Zhihao Xu","raw_affiliation_strings":["School of Information Science and Technology, Dalian Maritime University, Dalian, China","Dalian, China and the School of Computer Science and Engineering, School of Information Science and Technology, Dalian Maritime University, Southeast University, Nanjing, China"],"raw_orcid":"https://orcid.org/0009-0008-2188-207X","affiliations":[{"raw_affiliation_string":"School of Information Science and Technology, Dalian Maritime University, Dalian, China","institution_ids":["https://openalex.org/I43313876"]},{"raw_affiliation_string":"Dalian, China and the School of Computer Science and Engineering, School of Information Science and Technology, Dalian Maritime University, Southeast University, Nanjing, China","institution_ids":["https://openalex.org/I43313876","https://openalex.org/I76569877"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5018071549","display_name":"Shikai Guo","orcid":"https://orcid.org/0000-0002-8554-6365"},"institutions":[{"id":"https://openalex.org/I43313876","display_name":"Dalian Maritime University","ror":"https://ror.org/002b7nr53","country_code":"CN","type":"education","lineage":["https://openalex.org/I43313876"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Shikai Guo","raw_affiliation_strings":["School of Information Science and Technology, Dalian Maritime University, Dalian, China","School of Information Science and Technology, Dalian Maritime University, Dalian, China and the Key Laboratory of Artificial Intelligence of Dalian, Dalian, China"],"raw_orcid":"https://orcid.org/0000-0002-8554-6365","affiliations":[{"raw_affiliation_string":"School of Information Science and Technology, Dalian Maritime University, Dalian, China","institution_ids":["https://openalex.org/I43313876"]},{"raw_affiliation_string":"School of Information Science and Technology, Dalian Maritime University, Dalian, China and the Key Laboratory of Artificial Intelligence of Dalian, Dalian, China","institution_ids":["https://openalex.org/I43313876"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5008684196","display_name":"Guilin Zhao","orcid":"https://orcid.org/0000-0001-9907-9406"},"institutions":[{"id":"https://openalex.org/I43313876","display_name":"Dalian Maritime University","ror":"https://ror.org/002b7nr53","country_code":"CN","type":"education","lineage":["https://openalex.org/I43313876"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Guilin Zhao","raw_affiliation_strings":["School of Information Science and Technology, Dalian Maritime University, Dalian, China","School of Information Science and Technology, Dalian Maritime University, Dalian, China and the Key Laboratory of Artificial Intelligence of Dalian, Dalian, China"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"School of Information Science and Technology, Dalian Maritime University, Dalian, China","institution_ids":["https://openalex.org/I43313876"]},{"raw_affiliation_string":"School of Information Science and Technology, Dalian Maritime University, Dalian, China and the Key Laboratory of Artificial Intelligence of Dalian, Dalian, China","institution_ids":["https://openalex.org/I43313876"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5034954395","display_name":"Peiyu Zou","orcid":"https://orcid.org/0000-0003-2786-1807"},"institutions":[{"id":"https://openalex.org/I27357992","display_name":"Dalian University of Technology","ror":"https://ror.org/023hj5876","country_code":"CN","type":"education","lineage":["https://openalex.org/I27357992"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Peiyu Zou","raw_affiliation_strings":["School of Software, Dalian University of Technology, Dalian, China"],"raw_orcid":"https://orcid.org/0000-0003-2786-1807","affiliations":[{"raw_affiliation_string":"School of Software, Dalian University of Technology, Dalian, China","institution_ids":["https://openalex.org/I27357992"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5100328758","display_name":"Xiaochen Li","orcid":"https://orcid.org/0000-0002-5068-1938"},"institutions":[{"id":"https://openalex.org/I27357992","display_name":"Dalian University of Technology","ror":"https://ror.org/023hj5876","country_code":"CN","type":"education","lineage":["https://openalex.org/I27357992"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Xiaochen Li","raw_affiliation_strings":["School of Software, Dalian University of Technology, Dalian, China"],"raw_orcid":"https://orcid.org/0000-0002-5068-1938","affiliations":[{"raw_affiliation_string":"School of Software, Dalian University of Technology, Dalian, China","institution_ids":["https://openalex.org/I27357992"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5002119636","display_name":"He Jiang","orcid":"https://orcid.org/0000-0001-8674-4948"},"institutions":[{"id":"https://openalex.org/I27357992","display_name":"Dalian University of Technology","ror":"https://ror.org/023hj5876","country_code":"CN","type":"education","lineage":["https://openalex.org/I27357992"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"He Jiang","raw_affiliation_strings":["School of Software, Dalian University of Technology, Dalian, China"],"raw_orcid":"https://orcid.org/0000-0001-8674-4948","affiliations":[{"raw_affiliation_string":"School of Software, Dalian University of Technology, Dalian, China","institution_ids":["https://openalex.org/I27357992"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":3,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":4.131,"has_fulltext":false,"cited_by_count":3,"citation_normalized_percentile":{"value":0.93014827,"is_in_top_1_percent":false,"is_in_top_10_percent":true},"cited_by_percentile_year":{"min":91,"max":98},"biblio":{"volume":"44","issue":"11","first_page":"4405","last_page":"4418"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9977999925613403,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9977999925613403,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9955999851226807,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T12810","display_name":"Real-time simulation and control systems","score":0.9905999898910522,"subfield":{"id":"https://openalex.org/subfields/2207","display_name":"Control and Systems Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/compiler","display_name":"Compiler","score":0.7217989563941956},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6535554528236389},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.6438925266265869},{"id":"https://openalex.org/keywords/generator","display_name":"Generator (circuit theory)","score":0.6079471111297607},{"id":"https://openalex.org/keywords/code-generation","display_name":"Code generation","score":0.5478435158729553},{"id":"https://openalex.org/keywords/code","display_name":"Code (set theory)","score":0.4944331645965576},{"id":"https://openalex.org/keywords/programming-language","display_name":"Programming language","score":0.473073810338974},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.39072486758232117},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.38992375135421753},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.1506083607673645},{"id":"https://openalex.org/keywords/physics","display_name":"Physics","score":0.06108278036117554},{"id":"https://openalex.org/keywords/power","display_name":"Power (physics)","score":0.050113141536712646}],"concepts":[{"id":"https://openalex.org/C169590947","wikidata":"https://www.wikidata.org/wiki/Q47506","display_name":"Compiler","level":2,"score":0.7217989563941956},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6535554528236389},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.6438925266265869},{"id":"https://openalex.org/C2780992000","wikidata":"https://www.wikidata.org/wiki/Q17016113","display_name":"Generator (circuit theory)","level":3,"score":0.6079471111297607},{"id":"https://openalex.org/C133162039","wikidata":"https://www.wikidata.org/wiki/Q1061077","display_name":"Code generation","level":3,"score":0.5478435158729553},{"id":"https://openalex.org/C2776760102","wikidata":"https://www.wikidata.org/wiki/Q5139990","display_name":"Code (set theory)","level":3,"score":0.4944331645965576},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.473073810338974},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.39072486758232117},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.38992375135421753},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.1506083607673645},{"id":"https://openalex.org/C121332964","wikidata":"https://www.wikidata.org/wiki/Q413","display_name":"Physics","level":0,"score":0.06108278036117554},{"id":"https://openalex.org/C163258240","wikidata":"https://www.wikidata.org/wiki/Q25342","display_name":"Power (physics)","level":2,"score":0.050113141536712646},{"id":"https://openalex.org/C62520636","wikidata":"https://www.wikidata.org/wiki/Q944","display_name":"Quantum mechanics","level":1,"score":0.0},{"id":"https://openalex.org/C26517878","wikidata":"https://www.wikidata.org/wiki/Q228039","display_name":"Key (lock)","level":2,"score":0.0},{"id":"https://openalex.org/C177264268","wikidata":"https://www.wikidata.org/wiki/Q1514741","display_name":"Set (abstract data type)","level":2,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/tcad.2025.3565488","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tcad.2025.3565488","pdf_url":null,"source":{"id":"https://openalex.org/S100835903","display_name":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","issn_l":"0278-0070","issn":["0278-0070","1937-4151"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","raw_type":"journal-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[{"id":"https://openalex.org/G1847967853","display_name":null,"funder_award_id":"2024JJ12GX022","funder_id":"https://openalex.org/F4320336584","funder_display_name":"Dalian Science and Technology Innovation Fund"},{"id":"https://openalex.org/G3427093674","display_name":null,"funder_award_id":"62032004","funder_id":"https://openalex.org/F4320321001","funder_display_name":"National Natural Science Foundation of China"},{"id":"https://openalex.org/G5057948433","display_name":null,"funder_award_id":"62472062","funder_id":"https://openalex.org/F4320321001","funder_display_name":"National Natural Science Foundation of China"},{"id":"https://openalex.org/G6007899901","display_name":null,"funder_award_id":"62202079","funder_id":"https://openalex.org/F4320321001","funder_display_name":"National Natural Science Foundation of China"},{"id":"https://openalex.org/G7380868649","display_name":null,"funder_award_id":"2024JH2/102400059","funder_id":"https://openalex.org/F4320336742","funder_display_name":"Key Research and Development Program of Liaoning Province"}],"funders":[{"id":"https://openalex.org/F4320321001","display_name":"National Natural Science Foundation of China","ror":"https://ror.org/01h0zpd94"},{"id":"https://openalex.org/F4320336584","display_name":"Dalian Science and Technology Innovation Fund","ror":null},{"id":"https://openalex.org/F4320336742","display_name":"Key Research and Development Program of Liaoning Province","ror":null}],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":19,"referenced_works":["https://openalex.org/W2095445208","https://openalex.org/W2137978379","https://openalex.org/W2165436148","https://openalex.org/W2170737051","https://openalex.org/W2370472429","https://openalex.org/W2532737545","https://openalex.org/W2895425194","https://openalex.org/W2955578429","https://openalex.org/W2979357014","https://openalex.org/W3000636126","https://openalex.org/W3007855180","https://openalex.org/W3008410827","https://openalex.org/W3121710465","https://openalex.org/W3130011944","https://openalex.org/W3172669705","https://openalex.org/W3205281171","https://openalex.org/W4244688039","https://openalex.org/W4281994867","https://openalex.org/W4391681217"],"related_works":["https://openalex.org/W650988184","https://openalex.org/W2162410319","https://openalex.org/W2137356287","https://openalex.org/W4321184925","https://openalex.org/W2255990315","https://openalex.org/W60915090","https://openalex.org/W2025840053","https://openalex.org/W2161692994","https://openalex.org/W3122369893","https://openalex.org/W2387634031"],"abstract_inverted_index":{"Field":[0],"Programmable":[1],"Gate":[2],"Array":[3],"(FPGA)":[4],"logic":[5,35,56,80,121],"synthesis":[6,36,57,81,122],"compilers":[7,37,58],"(e.g.,":[8,71,134],"Vivado,":[9],"Iverilog,":[10],"Yosys,":[11],"and":[12,97,129,137,147,162,193],"Quartus)":[13],"are":[14,171,191],"widely":[15],"applied":[16],"in":[17,34,43,79],"Electronic":[18],"Design":[19,66],"Automation":[20],"(EDA),":[21],"such":[22,61],"as":[23],"the":[24,83,92,98,101,141,148,160,175],"development":[25],"of":[26,85,100,143,153,165,189,196],"FPGA":[27,120],"programs.":[28],"However,":[29],"defects":[30,78],"(e.g.":[31],"incorrect":[32],"synthesis)":[33],"may":[38],"lead":[39],"to":[40,53,59,76,112],"unexpected":[41],"behaviors":[42],"target":[44],"applications,":[45],"posing":[46],"security":[47],"risks.":[48],"Therefore,":[49],"it":[50],"is":[51,88],"crucial":[52],"thoroughly":[54],"test":[55],"eliminate":[60],"defects.":[62],"Despite":[63],"several":[64],"Hardware":[65],"Language":[67],"(HDL)":[68],"code":[69,94,116,133,167],"generators":[70,87],"Verismith)":[72],"having":[73],"been":[74,199],"proposed":[75],"find":[77],"compilers,":[82],"effectiveness":[84],"these":[86],"still":[89],"limited":[90],"by":[91,139,169],"simple":[93],"generation":[95],"strategy":[96],"monogeneity":[99],"generated":[102,168],"HDL":[103,115,132,166],"code.":[104],"This":[105],"paper":[106],"proposes":[107],"EvoHDL,":[108],"a":[109],"novel":[110],"method":[111,177],"generate":[113,126],"syntax-valid":[114],"for":[117],"comprehensively":[118],"testing":[119],"compilers.":[123],"EvoHDL":[124,170,183],"can":[125],"more":[127],"complex":[128],"diverse":[130],"defect-triggering":[131,163],"Verilog,":[135],"VHDL,":[136],"SystemVerilog)":[138],"leveraging":[140],"guidance":[142],"abstract":[144],"syntax":[145],"tree":[146],"extensive":[149],"function":[150],"block":[151],"libraries":[152],"cyber-physical":[154],"systems.":[155],"Extensive":[156],"experiments":[157],"show":[158],"that":[159],"diversity":[161],"capability":[164],"significantly":[172],"better":[173],"than":[174],"state-of-the-art":[176],"(i.e.,":[178],"Verismith).":[179],"In":[180],"three":[181],"months,":[182],"has":[184],"reported":[185],"20":[186],"new":[187],"defects\u2013many":[188],"which":[190],"deep":[192],"important;":[194],"16":[195],"them":[197],"have":[198],"confirmed.":[200]},"counts_by_year":[{"year":2026,"cited_by_count":2},{"year":2025,"cited_by_count":1}],"updated_date":"2026-03-27T05:58:40.876381","created_date":"2025-10-10T00:00:00"}