{"id":"https://openalex.org/W4401163769","doi":"https://doi.org/10.1109/tcad.2024.3436013","title":"LSTM-Characterized Approach for Chip Floorplanning: Leveraging HyperGCN and DRQN","display_name":"LSTM-Characterized Approach for Chip Floorplanning: Leveraging HyperGCN and DRQN","publication_year":2024,"publication_date":"2024-07-31","ids":{"openalex":"https://openalex.org/W4401163769","doi":"https://doi.org/10.1109/tcad.2024.3436013"},"language":"en","primary_location":{"id":"doi:10.1109/tcad.2024.3436013","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tcad.2024.3436013","pdf_url":null,"source":{"id":"https://openalex.org/S100835903","display_name":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","issn_l":"0278-0070","issn":["0278-0070","1937-4151"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5084608952","display_name":"Wenbo Guan","orcid":"https://orcid.org/0000-0002-2220-9847"},"institutions":[{"id":"https://openalex.org/I149594827","display_name":"Xidian University","ror":"https://ror.org/05s92vm98","country_code":"CN","type":"education","lineage":["https://openalex.org/I149594827"]}],"countries":["CN"],"is_corresponding":true,"raw_author_name":"Wenbo Guan","raw_affiliation_strings":["Faculty of Integrated Circuits, Xidian University, Xi’an, China"],"affiliations":[{"raw_affiliation_string":"Faculty of Integrated Circuits, Xidian University, Xi’an, China","institution_ids":["https://openalex.org/I149594827"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5085339970","display_name":"Xiao-Yan Tang","orcid":"https://orcid.org/0000-0002-8222-2808"},"institutions":[{"id":"https://openalex.org/I149594827","display_name":"Xidian University","ror":"https://ror.org/05s92vm98","country_code":"CN","type":"education","lineage":["https://openalex.org/I149594827"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Xiaoyan Tang","raw_affiliation_strings":["Faculty of Integrated Circuits, Xidian University, Xi’an, China"],"affiliations":[{"raw_affiliation_string":"Faculty of Integrated Circuits, Xidian University, Xi’an, China","institution_ids":["https://openalex.org/I149594827"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5055887546","display_name":"Hongliang L\u00fc","orcid":"https://orcid.org/0000-0003-2726-4316"},"institutions":[{"id":"https://openalex.org/I149594827","display_name":"Xidian University","ror":"https://ror.org/05s92vm98","country_code":"CN","type":"education","lineage":["https://openalex.org/I149594827"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Hongliang Lu","raw_affiliation_strings":["Faculty of Integrated Circuits, Xidian University, Xi’an, China"],"affiliations":[{"raw_affiliation_string":"Faculty of Integrated Circuits, Xidian University, Xi’an, China","institution_ids":["https://openalex.org/I149594827"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5097341792","display_name":"Jingru Tan","orcid":null},"institutions":[{"id":"https://openalex.org/I149594827","display_name":"Xidian University","ror":"https://ror.org/05s92vm98","country_code":"CN","type":"education","lineage":["https://openalex.org/I149594827"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Jingru Tan","raw_affiliation_strings":["School of Cyber Engineering, Xidian University, Xi’an, China"],"affiliations":[{"raw_affiliation_string":"School of Cyber Engineering, Xidian University, Xi’an, China","institution_ids":["https://openalex.org/I149594827"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5100340097","display_name":"Jinlong Wang","orcid":"https://orcid.org/0000-0001-9240-5600"},"institutions":[{"id":"https://openalex.org/I2801787653","display_name":"Beijing Dance Academy","ror":"https://ror.org/02g3wgj66","country_code":"CN","type":"education","lineage":["https://openalex.org/I2801787653"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Jinlong Wang","raw_affiliation_strings":["Department of TikTok Research and Development, Beijing Bytedance Technology Company Ltd., Beijing, China","Department of TikTok Research and Development, Beijing Bytedance Technology Co, Beijing, China"],"affiliations":[{"raw_affiliation_string":"Department of TikTok Research and Development, Beijing Bytedance Technology Company Ltd., Beijing, China","institution_ids":["https://openalex.org/I2801787653"]},{"raw_affiliation_string":"Department of TikTok Research and Development, Beijing Bytedance Technology Co, Beijing, China","institution_ids":[]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5100421237","display_name":"Yuming Zhang","orcid":"https://orcid.org/0000-0002-8587-0747"},"institutions":[{"id":"https://openalex.org/I149594827","display_name":"Xidian University","ror":"https://ror.org/05s92vm98","country_code":"CN","type":"education","lineage":["https://openalex.org/I149594827"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Yuming Zhang","raw_affiliation_strings":["Faculty of Integrated Circuits, Xidian University, Xi’an, China"],"affiliations":[{"raw_affiliation_string":"Faculty of Integrated Circuits, Xidian University, Xi’an, China","institution_ids":["https://openalex.org/I149594827"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5045888183","display_name":"Yimen Zhang","orcid":"https://orcid.org/0000-0002-4887-735X"},"institutions":[{"id":"https://openalex.org/I149594827","display_name":"Xidian University","ror":"https://ror.org/05s92vm98","country_code":"CN","type":"education","lineage":["https://openalex.org/I149594827"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Yimen Zhang","raw_affiliation_strings":["Faculty of Integrated Circuits, Xidian University, Xi’an, China"],"affiliations":[{"raw_affiliation_string":"Faculty of Integrated Circuits, Xidian University, Xi’an, China","institution_ids":["https://openalex.org/I149594827"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":7,"corresponding_author_ids":["https://openalex.org/A5084608952"],"corresponding_institution_ids":["https://openalex.org/I149594827"],"apc_list":null,"apc_paid":null,"fwci":0.2088,"has_fulltext":false,"cited_by_count":1,"citation_normalized_percentile":{"value":0.50112488,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":91,"max":95},"biblio":{"volume":"44","issue":"2","first_page":"709","last_page":"722"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9966999888420105,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9966999888420105,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11159","display_name":"Manufacturing Process and Optimization","score":0.9915000200271606,"subfield":{"id":"https://openalex.org/subfields/2209","display_name":"Industrial and Manufacturing Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11527","display_name":"3D IC and TSV technologies","score":0.9912999868392944,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/floorplan","display_name":"Floorplan","score":0.920043408870697},{"id":"https://openalex.org/keywords/chip","display_name":"Chip","score":0.604224443435669},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.5947997570037842},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.4448115825653076},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.4401230812072754},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.3833022117614746},{"id":"https://openalex.org/keywords/telecommunications","display_name":"Telecommunications","score":0.08292832970619202}],"concepts":[{"id":"https://openalex.org/C130145326","wikidata":"https://www.wikidata.org/wiki/Q1553985","display_name":"Floorplan","level":2,"score":0.920043408870697},{"id":"https://openalex.org/C165005293","wikidata":"https://www.wikidata.org/wiki/Q1074500","display_name":"Chip","level":2,"score":0.604224443435669},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.5947997570037842},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.4448115825653076},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.4401230812072754},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.3833022117614746},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.08292832970619202}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/tcad.2024.3436013","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tcad.2024.3436013","pdf_url":null,"source":{"id":"https://openalex.org/S100835903","display_name":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","issn_l":"0278-0070","issn":["0278-0070","1937-4151"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","raw_type":"journal-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":42,"referenced_works":["https://openalex.org/W1944814515","https://openalex.org/W1967402431","https://openalex.org/W1990789187","https://openalex.org/W2024060531","https://openalex.org/W2085374061","https://openalex.org/W2105616993","https://openalex.org/W2109826730","https://openalex.org/W2135685510","https://openalex.org/W2147899388","https://openalex.org/W2149544985","https://openalex.org/W2154462472","https://openalex.org/W2178215049","https://openalex.org/W2798405286","https://openalex.org/W2842511635","https://openalex.org/W2899620233","https://openalex.org/W3085990079","https://openalex.org/W3092027164","https://openalex.org/W3115480774","https://openalex.org/W3127834963","https://openalex.org/W3127876976","https://openalex.org/W3141265860","https://openalex.org/W3169517138","https://openalex.org/W3171752851","https://openalex.org/W3211934115","https://openalex.org/W3216969643","https://openalex.org/W4200341486","https://openalex.org/W4231171283","https://openalex.org/W4252279978","https://openalex.org/W4290876433","https://openalex.org/W4293023278","https://openalex.org/W4312121071","https://openalex.org/W4387490112","https://openalex.org/W4387546238","https://openalex.org/W6631190155","https://openalex.org/W6637967152","https://openalex.org/W6677939520","https://openalex.org/W6726873649","https://openalex.org/W6747769025","https://openalex.org/W6755691001","https://openalex.org/W6782858274","https://openalex.org/W6791250250","https://openalex.org/W6796367035"],"related_works":["https://openalex.org/W2055008360","https://openalex.org/W1500063550","https://openalex.org/W2135118255","https://openalex.org/W215057456","https://openalex.org/W2106366463","https://openalex.org/W1535718467","https://openalex.org/W2165891825","https://openalex.org/W4239364405","https://openalex.org/W2261987718","https://openalex.org/W2983230882"],"abstract_inverted_index":{"In":[0],"the":[1,59,70,107,120,161,168,173,190,200,207,230,257,279,286,301],"field":[2],"of":[3,62,113,202,215,233,260,281,289],"very":[4],"large-scale":[5],"integration":[6,102],"(VLSI)":[7],"chip":[8,10,46,114,162],"design,":[9,295],"floorplanning":[11,47,276],"plays":[12],"a":[13,129,179,212,297],"crucial":[14],"role":[15],"as":[16,24,163],"it":[17],"directly":[18],"influences":[19],"key":[20],"optimization":[21,194],"objectives":[22],"such":[23],"placement":[25],"wirelength.":[26],"This,":[27],"in":[28,241,293,300],"turn,":[29],"affects":[30],"signal":[31],"delay,":[32],"power":[33],"efficiency,":[34],"routability,":[35],"and":[36,52,65,110,166,251,273],"overall":[37],"cost.":[38],"However,":[39],"traditional":[40,121,271],"reinforcement":[41],"learning":[42],"(RL)":[43],"methods":[44],"for":[45,76],"often":[48],"oversimplify":[49],"this":[50,284],"complex":[51,147],"dynamic":[53],"task.":[54],"They":[55],"tend":[56],"to":[57,67,105,171,183,198,223],"overlook":[58],"cascading":[60],"effects":[61],"module":[63,174,217,234],"placements":[64],"fail":[66],"fully":[68],"comprehend":[69],"intricate":[71],"interdependencies":[72],"that":[73,89,226,267],"are":[74],"vital":[75],"making":[77],"informed":[78],"decisions.":[79],"To":[80,278],"address":[81],"these":[82],"challenges,":[83],"we":[84,159],"introduce":[85],"an":[86,164],"innovative":[87],"approach":[88,205],"combines":[90],"hypergraph":[91],"graph":[92,148],"convolutional":[93],"networks":[94],"(HyperGCNs)":[95],"with":[96,189,291],"deep":[97,191],"recurrent":[98,180],"Q-networks":[99],"(DRQNs).":[100],"This":[101,219,243],"allows":[103,220],"us":[104,197],"capture":[106],"nuanced":[108],"dynamics":[109],"interconnected":[111,216],"aspects":[112],"design":[115],"more":[116],"effectively.":[117],"We":[118],"enhance":[119],"Markov":[122],"decision":[123],"process":[124],"(MDP)":[125],"model":[126],"by":[127,210],"incorporating":[128],"state":[130,208,245],"characterization":[131],"layer":[132,181],"based":[133],"on":[134],"long":[135],"short-term":[136],"memory":[137],"(LSTM)":[138],"technology.":[139],"Initially,":[140],"HyperGCN":[141],"efficiently":[142],"encodes":[143],"netlist":[144],"information,":[145],"simplifying":[146],"structures":[149],"into":[150,228],"lower":[151],"dimensional":[152],"vectors,":[153],"thereby":[154],"enhancing":[155],"knowledge":[156],"processing.":[157],"Subsequently,":[158],"treat":[160],"agent":[165],"apply":[167],"DRQN":[169],"algorithm":[170],"optimize":[172],"layout.":[175],"DRQN\u2019s":[176],"LSTM":[177,290],"utilizes":[178],"structure":[182],"grasp":[184],"dependencies":[185],"between":[186],"modules,":[187],"combined":[188],"Q-network":[192],"(DQN)\u2019s":[193],"capabilities,":[195],"enabling":[196],"navigate":[199],"complexities":[201],"floorplanning.":[203],"Our":[204,263],"improves":[206],"representation":[209],"encompassing":[211],"broader":[213],"understanding":[214],"characteristics.":[218],"our":[221,261,268,282],"agents":[222],"make":[224],"decisions":[225],"take":[227],"account":[229],"collective":[231],"impact":[232],"adjustments,":[235],"rather":[236],"than":[237],"viewing":[238],"each":[239],"change":[240],"isolation.":[242],"comprehensive":[244],"representation,":[246],"which":[247],"includes":[248],"diverse":[249],"features":[250],"their":[252],"evolving":[253],"relationships,":[254],"significantly":[255],"enhances":[256],"decision-making":[258],"capabilities":[259],"agents.":[262],"extensive":[264],"experiments":[265],"demonstrate":[266],"method":[269],"outperforms":[270],"heuristic-based":[272],"other":[274],"learning-based":[275],"techniques.":[277],"best":[280],"knowledge,":[283],"is":[285],"first":[287],"application":[288],"DQN":[292],"circuit":[294],"representing":[296],"significant":[298],"advancement":[299],"field.":[302]},"counts_by_year":[{"year":2025,"cited_by_count":1}],"updated_date":"2026-03-27T05:58:40.876381","created_date":"2025-10-10T00:00:00"}