{"id":"https://openalex.org/W4388430394","doi":"https://doi.org/10.1109/tcad.2023.3329774","title":"High-Performance Placement Engine for Modern Large-Scale FPGAs With Heterogeneity and Clock Constraints","display_name":"High-Performance Placement Engine for Modern Large-Scale FPGAs With Heterogeneity and Clock Constraints","publication_year":2023,"publication_date":"2023-11-06","ids":{"openalex":"https://openalex.org/W4388430394","doi":"https://doi.org/10.1109/tcad.2023.3329774"},"language":"en","primary_location":{"id":"doi:10.1109/tcad.2023.3329774","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tcad.2023.3329774","pdf_url":null,"source":{"id":"https://openalex.org/S100835903","display_name":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","issn_l":"0278-0070","issn":["0278-0070","1937-4151"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5065790763","display_name":"Ziran Zhu","orcid":"https://orcid.org/0000-0002-9475-6364"},"institutions":[{"id":"https://openalex.org/I76569877","display_name":"Southeast University","ror":"https://ror.org/04ct4d772","country_code":"CN","type":"education","lineage":["https://openalex.org/I76569877"]}],"countries":["CN"],"is_corresponding":true,"raw_author_name":"Ziran Zhu","raw_affiliation_strings":["National ASIC System Engineering Research Center, School of Integrated Circuits, Southeast University, Nanjing, China"],"raw_orcid":"https://orcid.org/0000-0002-9475-6364","affiliations":[{"raw_affiliation_string":"National ASIC System Engineering Research Center, School of Integrated Circuits, Southeast University, Nanjing, China","institution_ids":["https://openalex.org/I76569877"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5082518778","display_name":"Yangjie Mei","orcid":null},"institutions":[{"id":"https://openalex.org/I76569877","display_name":"Southeast University","ror":"https://ror.org/04ct4d772","country_code":"CN","type":"education","lineage":["https://openalex.org/I76569877"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Yangjie Mei","raw_affiliation_strings":["National ASIC System Engineering Research Center, School of Integrated Circuits, Southeast University, Nanjing, China"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"National ASIC System Engineering Research Center, School of Integrated Circuits, Southeast University, Nanjing, China","institution_ids":["https://openalex.org/I76569877"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5082505512","display_name":"Kangkang Deng","orcid":"https://orcid.org/0000-0003-0938-0233"},"institutions":[{"id":"https://openalex.org/I20231570","display_name":"Peking University","ror":"https://ror.org/02v51f717","country_code":"CN","type":"education","lineage":["https://openalex.org/I20231570"]},{"id":"https://openalex.org/I4210133846","display_name":"Peking University International Hospital","ror":"https://ror.org/03jxhcr96","country_code":"CN","type":"healthcare","lineage":["https://openalex.org/I4210133846"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Kangkang Deng","raw_affiliation_strings":["Beijing International Center for Mathematical Research, Peking University, Beijing, China"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Beijing International Center for Mathematical Research, Peking University, Beijing, China","institution_ids":["https://openalex.org/I20231570","https://openalex.org/I4210133846"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5000710953","display_name":"Huan He","orcid":"https://orcid.org/0000-0002-7416-3254"},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Huan He","raw_affiliation_strings":["Central Hardware Planning & Architecture Design Department, Hangzhou Huawei Enterprises Telecommunication Technologies Company Ltd., Hangzhou, China"],"raw_orcid":"https://orcid.org/0000-0002-7416-3254","affiliations":[{"raw_affiliation_string":"Central Hardware Planning & Architecture Design Department, Hangzhou Huawei Enterprises Telecommunication Technologies Company Ltd., Hangzhou, China","institution_ids":[]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5101854580","display_name":"Jianli Chen","orcid":"https://orcid.org/0000-0002-1391-2696"},"institutions":[{"id":"https://openalex.org/I24943067","display_name":"Fudan University","ror":"https://ror.org/013q1eq08","country_code":"CN","type":"education","lineage":["https://openalex.org/I24943067"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Jianli Chen","raw_affiliation_strings":["State Key Laboratory of ASIC and System, Fudan University, Shanghai, China"],"raw_orcid":"https://orcid.org/0000-0002-1391-2696","affiliations":[{"raw_affiliation_string":"State Key Laboratory of ASIC and System, Fudan University, Shanghai, China","institution_ids":["https://openalex.org/I24943067"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5030384645","display_name":"Jun Yang","orcid":"https://orcid.org/0000-0002-8379-0321"},"institutions":[{"id":"https://openalex.org/I76569877","display_name":"Southeast University","ror":"https://ror.org/04ct4d772","country_code":"CN","type":"education","lineage":["https://openalex.org/I76569877"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Jun Yang","raw_affiliation_strings":["National ASIC System Engineering Research Center, School of Integrated Circuits, Southeast University, Nanjing, China"],"raw_orcid":"https://orcid.org/0000-0002-8379-0321","affiliations":[{"raw_affiliation_string":"National ASIC System Engineering Research Center, School of Integrated Circuits, Southeast University, Nanjing, China","institution_ids":["https://openalex.org/I76569877"]}]},{"author_position":"last","author":{"id":null,"display_name":"Yao-Wen Chang","orcid":"https://orcid.org/0000-0001-8838-2653"},"institutions":[{"id":"https://openalex.org/I16733864","display_name":"National Taiwan University","ror":"https://ror.org/05bqach95","country_code":"TW","type":"education","lineage":["https://openalex.org/I16733864"]}],"countries":["TW"],"is_corresponding":false,"raw_author_name":"Yao-Wen Chang","raw_affiliation_strings":["Graduate Institute of Electronics Engineering and the Department of Electrical Engineering, National Taiwan University, Taipei, Taiwan"],"raw_orcid":"https://orcid.org/0000-0001-8838-2653","affiliations":[{"raw_affiliation_string":"Graduate Institute of Electronics Engineering and the Department of Electrical Engineering, National Taiwan University, Taipei, Taiwan","institution_ids":["https://openalex.org/I16733864"]}]}],"institutions":[],"countries_distinct_count":2,"institutions_distinct_count":7,"corresponding_author_ids":["https://openalex.org/A5065790763"],"corresponding_institution_ids":["https://openalex.org/I76569877"],"apc_list":null,"apc_paid":null,"fwci":0.2555,"has_fulltext":false,"cited_by_count":2,"citation_normalized_percentile":{"value":0.54851652,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":90,"max":94},"biblio":{"volume":"43","issue":"3","first_page":"956","last_page":"969"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9993000030517578,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11527","display_name":"3D IC and TSV technologies","score":0.9968000054359436,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.809622049331665},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7101340293884277},{"id":"https://openalex.org/keywords/scalability","display_name":"Scalability","score":0.6790903806686401},{"id":"https://openalex.org/keywords/simulated-annealing","display_name":"Simulated annealing","score":0.5316351652145386},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.4776631295681},{"id":"https://openalex.org/keywords/block","display_name":"Block (permutation group theory)","score":0.47632867097854614},{"id":"https://openalex.org/keywords/legalization","display_name":"Legalization","score":0.42915600538253784},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.37206441164016724},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.17395305633544922},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.11344429850578308}],"concepts":[{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.809622049331665},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7101340293884277},{"id":"https://openalex.org/C48044578","wikidata":"https://www.wikidata.org/wiki/Q727490","display_name":"Scalability","level":2,"score":0.6790903806686401},{"id":"https://openalex.org/C126980161","wikidata":"https://www.wikidata.org/wiki/Q863783","display_name":"Simulated annealing","level":2,"score":0.5316351652145386},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.4776631295681},{"id":"https://openalex.org/C2777210771","wikidata":"https://www.wikidata.org/wiki/Q4927124","display_name":"Block (permutation group theory)","level":2,"score":0.47632867097854614},{"id":"https://openalex.org/C2778506969","wikidata":"https://www.wikidata.org/wiki/Q940525","display_name":"Legalization","level":2,"score":0.42915600538253784},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.37206441164016724},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.17395305633544922},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.11344429850578308},{"id":"https://openalex.org/C15744967","wikidata":"https://www.wikidata.org/wiki/Q9418","display_name":"Psychology","level":0,"score":0.0},{"id":"https://openalex.org/C118552586","wikidata":"https://www.wikidata.org/wiki/Q7867","display_name":"Psychiatry","level":1,"score":0.0},{"id":"https://openalex.org/C77088390","wikidata":"https://www.wikidata.org/wiki/Q8513","display_name":"Database","level":1,"score":0.0},{"id":"https://openalex.org/C2524010","wikidata":"https://www.wikidata.org/wiki/Q8087","display_name":"Geometry","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/tcad.2023.3329774","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tcad.2023.3329774","pdf_url":null,"source":{"id":"https://openalex.org/S100835903","display_name":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","issn_l":"0278-0070","issn":["0278-0070","1937-4151"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","raw_type":"journal-article"}],"best_oa_location":null,"sustainable_development_goals":[{"score":0.47999998927116394,"display_name":"Peace, Justice and strong institutions","id":"https://metadata.un.org/sdg/16"}],"awards":[{"id":"https://openalex.org/G5200715922","display_name":null,"funder_award_id":"2022YFB4400500","funder_id":"https://openalex.org/F4320335777","funder_display_name":"National Key Research and Development Program of China"},{"id":"https://openalex.org/G6443967404","display_name":null,"funder_award_id":"MOST 110-2221-E-002-177-MY3","funder_id":"https://openalex.org/F4320322795","funder_display_name":"Ministry of Science and Technology, Taiwan"},{"id":"https://openalex.org/G7997439749","display_name":null,"funder_award_id":"62104037","funder_id":"https://openalex.org/F4320321001","funder_display_name":"National Natural Science Foundation of China"},{"id":"https://openalex.org/G970242193","display_name":null,"funder_award_id":"BK20210219","funder_id":"https://openalex.org/F4320322769","funder_display_name":"Natural Science Foundation of Jiangsu Province"}],"funders":[{"id":"https://openalex.org/F4320321001","display_name":"National Natural Science Foundation of China","ror":"https://ror.org/01h0zpd94"},{"id":"https://openalex.org/F4320322769","display_name":"Natural Science Foundation of Jiangsu Province","ror":"https://ror.org/01h0zpd94"},{"id":"https://openalex.org/F4320322795","display_name":"Ministry of Science and Technology, Taiwan","ror":"https://ror.org/02kv4zf79"},{"id":"https://openalex.org/F4320335777","display_name":"National Key Research and Development Program of China","ror":null}],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":32,"referenced_works":["https://openalex.org/W1522301498","https://openalex.org/W1996746141","https://openalex.org/W2029031086","https://openalex.org/W2057624533","https://openalex.org/W2124537194","https://openalex.org/W2131920591","https://openalex.org/W2139637699","https://openalex.org/W2150281391","https://openalex.org/W2165419774","https://openalex.org/W2167190617","https://openalex.org/W2595334824","https://openalex.org/W2626482350","https://openalex.org/W2738078952","https://openalex.org/W2770762651","https://openalex.org/W2771551340","https://openalex.org/W2774510317","https://openalex.org/W2801898382","https://openalex.org/W2897282114","https://openalex.org/W2915733502","https://openalex.org/W2997112717","https://openalex.org/W2997871849","https://openalex.org/W3143454515","https://openalex.org/W3185597847","https://openalex.org/W4200068975","https://openalex.org/W4212918377","https://openalex.org/W4234143391","https://openalex.org/W4253397218","https://openalex.org/W4255959021","https://openalex.org/W4293023445","https://openalex.org/W4293024106","https://openalex.org/W4293775970","https://openalex.org/W6631190155"],"related_works":["https://openalex.org/W181044676","https://openalex.org/W2376987616","https://openalex.org/W2054026560","https://openalex.org/W4389994644","https://openalex.org/W2390844778","https://openalex.org/W2323493410","https://openalex.org/W3086867668","https://openalex.org/W4225935048","https://openalex.org/W2366627955","https://openalex.org/W2138311189"],"abstract_inverted_index":{"As":[0],"field-programmable":[1],"gate":[2],"array":[3],"(FPGA)":[4],"architectures":[5],"continue":[6],"to":[7,26,65,83,106,131,143,156,169],"evolve":[8],"and":[9,15,42,48,59,78,91,135,137,146,162],"become":[10],"more":[11],"complex,":[12],"the":[13,60,67,85,103,115,133,171,178,185,192,197],"heterogeneity":[14,41,90],"clock":[16,43,92],"constraints":[17,93],"imposed":[18],"by":[19],"modern":[20,37],"FPGAs":[21,39],"have":[22],"posed":[23],"significant":[24],"challenges":[25],"FPGA":[27,86],"placement.":[28,122],"This":[29],"article":[30],"proposes":[31],"a":[32,52,75,95,124,138,153,163,202],"high-performance":[33],"placement":[34,88,166],"engine":[35],"for":[36,120],"large-scale":[38],"with":[40,89,177],"constraints.":[44],"To":[45],"improve":[46],"efficiency":[47],"scalability,":[49],"we":[50,73,112,151],"develop":[51],"clustering":[53],"method":[54,81,105],"considering":[55],"both":[56],"internal/external":[57],"connectivity":[58],"balance":[61],"of":[62,97],"block":[63,127],"types":[64],"build":[66],"hierarchy.":[68],"In":[69,110],"each":[70,108],"hierarchy":[71],"level,":[72],"propose":[74,152],"hybrid":[76],"penalty":[77],"augmented":[79],"Lagrangian":[80],"(HPALM)":[82],"convert":[84],"global":[87,121],"into":[94,148],"series":[96],"unconstrained":[98],"optimization":[99],"subproblems,":[100],"then":[101],"use":[102],"Adam":[104],"solve":[107],"subproblem.":[109],"particular,":[111],"prove":[113],"that":[114,191],"HPALM":[116],"is":[117,129,141,167],"globally":[118],"convergent":[119],"Besides,":[123],"matching-based":[125],"IP":[126],"legalization":[128,155],"developed":[130],"legalize":[132,157],"DSPs":[134],"RAMs,":[136],"multistage":[139],"packing":[140],"presented":[142,168],"cluster":[144],"LUTs":[145],"FFs":[147],"HCLBs.":[149],"Finally,":[150],"history-based":[154],"CLBs":[158],"in":[159,201],"an":[160],"FPGA,":[161],"simulated-annealing-based":[164],"detailed":[165],"reduce":[170],"wirelength":[172,200],"while":[173],"maintaining":[174],"legality.":[175],"Compared":[176],"state-of-the-art":[179],"works,":[180],"experimental":[181],"results":[182],"based":[183],"on":[184],"ISPD":[186],"2017":[187],"contest":[188],"benchmarks":[189],"show":[190],"proposed":[193],"algorithm":[194],"can":[195],"achieve":[196],"shortest":[198],"routed":[199],"reasonable":[203],"runtime.":[204]},"counts_by_year":[{"year":2024,"cited_by_count":1},{"year":2023,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}