{"id":"https://openalex.org/W4386523879","doi":"https://doi.org/10.1109/tcad.2023.3313101","title":"Multielectrostatic FPGA Placement Considering SLICEL\u2013SLICEM Heterogeneity, Clock Feasibility, and Timing Optimization","display_name":"Multielectrostatic FPGA Placement Considering SLICEL\u2013SLICEM Heterogeneity, Clock Feasibility, and Timing Optimization","publication_year":2023,"publication_date":"2023-09-07","ids":{"openalex":"https://openalex.org/W4386523879","doi":"https://doi.org/10.1109/tcad.2023.3313101"},"language":"en","primary_location":{"id":"doi:10.1109/tcad.2023.3313101","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tcad.2023.3313101","pdf_url":null,"source":{"id":"https://openalex.org/S100835903","display_name":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","issn_l":"0278-0070","issn":["0278-0070","1937-4151"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5042195167","display_name":"Jing Mai","orcid":"https://orcid.org/0000-0002-3787-1534"},"institutions":[{"id":"https://openalex.org/I20231570","display_name":"Peking University","ror":"https://ror.org/02v51f717","country_code":"CN","type":"education","lineage":["https://openalex.org/I20231570"]}],"countries":["CN"],"is_corresponding":true,"raw_author_name":"Jing Mai","raw_affiliation_strings":["School of Computer Science, Peking University, Beijing, China"],"affiliations":[{"raw_affiliation_string":"School of Computer Science, Peking University, Beijing, China","institution_ids":["https://openalex.org/I20231570"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5100639356","display_name":"Jiarui Wang","orcid":"https://orcid.org/0000-0002-7054-384X"},"institutions":[{"id":"https://openalex.org/I20231570","display_name":"Peking University","ror":"https://ror.org/02v51f717","country_code":"CN","type":"education","lineage":["https://openalex.org/I20231570"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Jiarui Wang","raw_affiliation_strings":["School of Computer Science, Peking University, Beijing, China"],"affiliations":[{"raw_affiliation_string":"School of Computer Science, Peking University, Beijing, China","institution_ids":["https://openalex.org/I20231570"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5000972803","display_name":"Zhixiong Di","orcid":"https://orcid.org/0000-0001-7323-5052"},"institutions":[{"id":"https://openalex.org/I4800084","display_name":"Southwest Jiaotong University","ror":"https://ror.org/00hn7w693","country_code":"CN","type":"education","lineage":["https://openalex.org/I4800084"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Zhixiong Di","raw_affiliation_strings":["School of Information Science and Technology, Southwest Jiaotong University, Chengdu, China"],"affiliations":[{"raw_affiliation_string":"School of Information Science and Technology, Southwest Jiaotong University, Chengdu, China","institution_ids":["https://openalex.org/I4800084"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5000933188","display_name":"Yibo Lin","orcid":"https://orcid.org/0000-0002-0977-2774"},"institutions":[{"id":"https://openalex.org/I20231570","display_name":"Peking University","ror":"https://ror.org/02v51f717","country_code":"CN","type":"education","lineage":["https://openalex.org/I20231570"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Yibo Lin","raw_affiliation_strings":["School of Integrated Circuits, Peking University, Beijing, China"],"affiliations":[{"raw_affiliation_string":"School of Integrated Circuits, Peking University, Beijing, China","institution_ids":["https://openalex.org/I20231570"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":4,"corresponding_author_ids":["https://openalex.org/A5042195167"],"corresponding_institution_ids":["https://openalex.org/I20231570"],"apc_list":null,"apc_paid":null,"fwci":0.9124,"has_fulltext":false,"cited_by_count":7,"citation_normalized_percentile":{"value":0.74303355,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":95,"max":99},"biblio":{"volume":"43","issue":"2","first_page":"641","last_page":"653"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9988999962806702,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9987999796867371,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.8055990934371948},{"id":"https://openalex.org/keywords/placement","display_name":"Placement","score":0.7795108556747437},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7172306776046753},{"id":"https://openalex.org/keywords/static-timing-analysis","display_name":"Static timing analysis","score":0.6368953585624695},{"id":"https://openalex.org/keywords/routing","display_name":"Routing (electronic design automation)","score":0.6343871355056763},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.49727538228034973},{"id":"https://openalex.org/keywords/weighting","display_name":"Weighting","score":0.4194210469722748},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.33498257398605347},{"id":"https://openalex.org/keywords/physical-design","display_name":"Physical design","score":0.20302817225456238},{"id":"https://openalex.org/keywords/circuit-design","display_name":"Circuit design","score":0.12010228633880615}],"concepts":[{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.8055990934371948},{"id":"https://openalex.org/C117690923","wikidata":"https://www.wikidata.org/wiki/Q1484784","display_name":"Placement","level":4,"score":0.7795108556747437},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7172306776046753},{"id":"https://openalex.org/C93682380","wikidata":"https://www.wikidata.org/wiki/Q2025226","display_name":"Static timing analysis","level":2,"score":0.6368953585624695},{"id":"https://openalex.org/C74172769","wikidata":"https://www.wikidata.org/wiki/Q1446839","display_name":"Routing (electronic design automation)","level":2,"score":0.6343871355056763},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.49727538228034973},{"id":"https://openalex.org/C183115368","wikidata":"https://www.wikidata.org/wiki/Q856577","display_name":"Weighting","level":2,"score":0.4194210469722748},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.33498257398605347},{"id":"https://openalex.org/C188817802","wikidata":"https://www.wikidata.org/wiki/Q13426855","display_name":"Physical design","level":3,"score":0.20302817225456238},{"id":"https://openalex.org/C190560348","wikidata":"https://www.wikidata.org/wiki/Q3245116","display_name":"Circuit design","level":2,"score":0.12010228633880615},{"id":"https://openalex.org/C126838900","wikidata":"https://www.wikidata.org/wiki/Q77604","display_name":"Radiology","level":1,"score":0.0},{"id":"https://openalex.org/C71924100","wikidata":"https://www.wikidata.org/wiki/Q11190","display_name":"Medicine","level":0,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/tcad.2023.3313101","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tcad.2023.3313101","pdf_url":null,"source":{"id":"https://openalex.org/S100835903","display_name":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","issn_l":"0278-0070","issn":["0278-0070","1937-4151"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","raw_type":"journal-article"}],"best_oa_location":null,"sustainable_development_goals":[{"id":"https://metadata.un.org/sdg/7","display_name":"Affordable and clean energy","score":0.4000000059604645}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":37,"referenced_works":["https://openalex.org/W1922167881","https://openalex.org/W1981519894","https://openalex.org/W1985292881","https://openalex.org/W1987995897","https://openalex.org/W2003764518","https://openalex.org/W2007049691","https://openalex.org/W2024392966","https://openalex.org/W2067856828","https://openalex.org/W2094806828","https://openalex.org/W2132693178","https://openalex.org/W2151758817","https://openalex.org/W2154014710","https://openalex.org/W2158578385","https://openalex.org/W2328615082","https://openalex.org/W2533722497","https://openalex.org/W2535860792","https://openalex.org/W2595334824","https://openalex.org/W2738078952","https://openalex.org/W2770762651","https://openalex.org/W2771551340","https://openalex.org/W2774510317","https://openalex.org/W2801898382","https://openalex.org/W2884307971","https://openalex.org/W2897282114","https://openalex.org/W2897505503","https://openalex.org/W2915733502","https://openalex.org/W2945592068","https://openalex.org/W2945806107","https://openalex.org/W3036696276","https://openalex.org/W3125127664","https://openalex.org/W3185597847","https://openalex.org/W4200068975","https://openalex.org/W4205914307","https://openalex.org/W4251366091","https://openalex.org/W4252769808","https://openalex.org/W4293023445","https://openalex.org/W4318684489"],"related_works":["https://openalex.org/W2110265185","https://openalex.org/W3146360095","https://openalex.org/W1571681534","https://openalex.org/W2184011203","https://openalex.org/W2042759115","https://openalex.org/W113636695","https://openalex.org/W1980984060","https://openalex.org/W3183044703","https://openalex.org/W2153380648","https://openalex.org/W1974474301"],"abstract_inverted_index":{"When":[0],"modern":[1,7],"FPGA":[2,8,27,57,80,90],"architecture":[3],"becomes":[4],"increasingly":[5],"complicated,":[6],"placement":[9,81,157],"is":[10],"a":[11,41,88,115,123,140,153],"mixed":[12],"optimization":[13,135,162],"problem":[14],"with":[15,114],"multiple":[16],"objectives,":[17],"including":[18],"wirelength,":[19,165],"routability,":[20,166],"timing":[21,147],"closure,":[22],"and":[23,36,74,101,127,168,176,189],"clock":[24,65,99,169],"feasibility.":[25,170],"Typical":[26],"devices":[28],"nowadays":[29],"consist":[30],"of":[31,40,164],"heterogeneous":[32],"SLICEs":[33],"like":[34,63],"SLICEL":[35],"SLICEM.":[37],"The":[38,71],"resources":[39],"SLICE":[42],"can":[43],"be":[44],"configured":[45],"to":[46,79,132,145,159],"{LUT,":[47],"FF,":[48],"distributed":[49],"RAM,":[50],"SHIFT,":[51],"CARRY}.":[52],"Besides":[53],"such":[54],"heterogeneity,":[55],"advanced":[56],"architectures":[58],"also":[59,121],"bring":[60],"complicated":[61],"constraints":[62,75],"timing,":[64,98,167],"routing,":[66],"carry":[67,102,128],"chain":[68,103,129],"alignment,":[69],"etc.":[70],"above":[72],"heterogeneity":[73,96,112],"impose":[76],"increasing":[77],"challenges":[78],"algorithms.":[82],"In":[83],"this":[84],"work,":[85],"we":[86,150],"propose":[87,108,139],"multielectrostatic":[89],"placer":[91,182],"considering":[92],"the":[93,134,161,184],"aforementioned":[94],"SLICEL\u2013SLICEM":[95,111],"under":[97],"routing":[100],"alignment":[104,130],"constraints.":[105],"We":[106,120,137],"first":[107],"an":[109],"effective":[110],"model":[113],"novel":[116],"electrostatic-based":[117],"density":[118],"formulation.":[119],"design":[122],"dynamically":[124],"adjusted":[125],"preconditioning":[126],"technique":[131],"stabilize":[133],"convergence.":[136],"then":[138],"timing-driven":[141],"net":[142],"weighting":[143],"scheme":[144],"incorporate":[146,160],"optimization.":[148],"Finally,":[149],"put":[151],"forward":[152],"nested":[154],"Lagrangian":[155],"relaxation-based":[156],"framework":[158],"objectives":[163],"Experimental":[171],"results":[172],"on":[173],"both":[174],"academic":[175],"industrial":[177],"benchmarks":[178],"demonstrate":[179],"that":[180],"our":[181],"outperforms":[183],"state-of-the-art":[185],"placers":[186],"in":[187],"quality":[188],"efficiency.":[190]},"counts_by_year":[{"year":2026,"cited_by_count":1},{"year":2025,"cited_by_count":2},{"year":2024,"cited_by_count":4}],"updated_date":"2026-03-27T05:58:40.876381","created_date":"2025-10-10T00:00:00"}