{"id":"https://openalex.org/W4320713034","doi":"https://doi.org/10.1109/tcad.2023.3244879","title":"A Security-Aware and LUT-Based CAD Flow for the Physical Synthesis of hASICs","display_name":"A Security-Aware and LUT-Based CAD Flow for the Physical Synthesis of hASICs","publication_year":2023,"publication_date":"2023-02-14","ids":{"openalex":"https://openalex.org/W4320713034","doi":"https://doi.org/10.1109/tcad.2023.3244879"},"language":"en","primary_location":{"id":"doi:10.1109/tcad.2023.3244879","is_oa":true,"landing_page_url":"https://doi.org/10.1109/tcad.2023.3244879","pdf_url":"https://ieeexplore.ieee.org/ielx7/43/6917053/10044229.pdf","source":{"id":"https://openalex.org/S100835903","display_name":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","issn_l":"0278-0070","issn":["0278-0070","1937-4151"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":"cc-by","license_id":"https://openalex.org/licenses/cc-by","version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":true,"oa_status":"hybrid","oa_url":"https://ieeexplore.ieee.org/ielx7/43/6917053/10044229.pdf","any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5050135442","display_name":"Zain Ul Abideen","orcid":"https://orcid.org/0000-0002-8865-9402"},"institutions":[{"id":"https://openalex.org/I111112146","display_name":"Tallinn University of Technology","ror":"https://ror.org/0443cwa12","country_code":"EE","type":"education","lineage":["https://openalex.org/I111112146"]}],"countries":["EE"],"is_corresponding":true,"raw_author_name":"Zain Ul Abideen","raw_affiliation_strings":["Department of Computer Systems, Centre for Hardware Security, Tallinn University of Technology, Tallinn, Estonia","Department of Computer Systems, Centre for Hardware Security, Tallinn University of Technology (TalTech), Tallinn, Estonia"],"raw_orcid":"https://orcid.org/0000-0002-8865-9402","affiliations":[{"raw_affiliation_string":"Department of Computer Systems, Centre for Hardware Security, Tallinn University of Technology, Tallinn, Estonia","institution_ids":["https://openalex.org/I111112146"]},{"raw_affiliation_string":"Department of Computer Systems, Centre for Hardware Security, Tallinn University of Technology (TalTech), Tallinn, Estonia","institution_ids":["https://openalex.org/I111112146"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5016003223","display_name":"Tiago Perez","orcid":"https://orcid.org/0000-0001-6006-1938"},"institutions":[{"id":"https://openalex.org/I111112146","display_name":"Tallinn University of Technology","ror":"https://ror.org/0443cwa12","country_code":"EE","type":"education","lineage":["https://openalex.org/I111112146"]}],"countries":["EE"],"is_corresponding":false,"raw_author_name":"Tiago Diadami Perez","raw_affiliation_strings":["Department of Computer Systems, Centre for Hardware Security, Tallinn University of Technology, Tallinn, Estonia","Department of Computer Systems, Centre for Hardware Security, Tallinn University of Technology (TalTech), Tallinn, Estonia"],"raw_orcid":"https://orcid.org/0000-0001-6006-1938","affiliations":[{"raw_affiliation_string":"Department of Computer Systems, Centre for Hardware Security, Tallinn University of Technology, Tallinn, Estonia","institution_ids":["https://openalex.org/I111112146"]},{"raw_affiliation_string":"Department of Computer Systems, Centre for Hardware Security, Tallinn University of Technology (TalTech), Tallinn, Estonia","institution_ids":["https://openalex.org/I111112146"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5076835601","display_name":"Mayler G. A. Martins","orcid":"https://orcid.org/0000-0002-2848-2190"},"institutions":[{"id":"https://openalex.org/I4210088951","display_name":"Synopsys (United States)","ror":"https://ror.org/013by2m91","country_code":"US","type":"company","lineage":["https://openalex.org/I4210088951"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Mayler Martins","raw_affiliation_strings":["SRG, Synopsys Inc., Mountain View, CA, USA"],"raw_orcid":"https://orcid.org/0000-0002-2848-2190","affiliations":[{"raw_affiliation_string":"SRG, Synopsys Inc., Mountain View, CA, USA","institution_ids":["https://openalex.org/I4210088951"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5060594809","display_name":"Samuel Pagliarini","orcid":"https://orcid.org/0000-0002-5294-0606"},"institutions":[{"id":"https://openalex.org/I111112146","display_name":"Tallinn University of Technology","ror":"https://ror.org/0443cwa12","country_code":"EE","type":"education","lineage":["https://openalex.org/I111112146"]}],"countries":["EE"],"is_corresponding":false,"raw_author_name":"Samuel Pagliarini","raw_affiliation_strings":["Department of Computer Systems, Centre for Hardware Security, Tallinn University of Technology, Tallinn, Estonia","Department of Computer Systems, Centre for Hardware Security, Tallinn University of Technology (TalTech), Tallinn, Estonia"],"raw_orcid":"https://orcid.org/0000-0002-5294-0606","affiliations":[{"raw_affiliation_string":"Department of Computer Systems, Centre for Hardware Security, Tallinn University of Technology, Tallinn, Estonia","institution_ids":["https://openalex.org/I111112146"]},{"raw_affiliation_string":"Department of Computer Systems, Centre for Hardware Security, Tallinn University of Technology (TalTech), Tallinn, Estonia","institution_ids":["https://openalex.org/I111112146"]}]}],"institutions":[],"countries_distinct_count":2,"institutions_distinct_count":4,"corresponding_author_ids":["https://openalex.org/A5050135442"],"corresponding_institution_ids":["https://openalex.org/I111112146"],"apc_list":null,"apc_paid":null,"fwci":4.4886,"has_fulltext":true,"cited_by_count":15,"citation_normalized_percentile":{"value":0.95275831,"is_in_top_1_percent":false,"is_in_top_10_percent":true},"cited_by_percentile_year":{"min":94,"max":99},"biblio":{"volume":"42","issue":"10","first_page":"3157","last_page":"3170"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T12122","display_name":"Physical Unclonable Functions (PUFs) and Hardware Security","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T12122","display_name":"Physical Unclonable Functions (PUFs) and Hardware Security","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T14117","display_name":"Integrated Circuits and Semiconductor Failure Analysis","score":0.9810000061988831,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11601","display_name":"Neuroscience and Neural Engineering","score":0.9570000171661377,"subfield":{"id":"https://openalex.org/subfields/2804","display_name":"Cellular and Molecular Neuroscience"},"field":{"id":"https://openalex.org/fields/28","display_name":"Neuroscience"},"domain":{"id":"https://openalex.org/domains/1","display_name":"Life Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/obfuscation","display_name":"Obfuscation","score":0.7500101327896118},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7260183095932007},{"id":"https://openalex.org/keywords/application-specific-integrated-circuit","display_name":"Application-specific integrated circuit","score":0.7010771036148071},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.6181676387786865},{"id":"https://openalex.org/keywords/lookup-table","display_name":"Lookup table","score":0.5549394488334656},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.5038830637931824},{"id":"https://openalex.org/keywords/hardware-security-module","display_name":"Hardware security module","score":0.4734898507595062},{"id":"https://openalex.org/keywords/block","display_name":"Block (permutation group theory)","score":0.47213155031204224},{"id":"https://openalex.org/keywords/oracle","display_name":"Oracle","score":0.4709171950817108},{"id":"https://openalex.org/keywords/design-flow","display_name":"Design flow","score":0.4688265025615692},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.3792777955532074},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.3317951560020447},{"id":"https://openalex.org/keywords/cryptography","display_name":"Cryptography","score":0.27843764424324036},{"id":"https://openalex.org/keywords/computer-security","display_name":"Computer security","score":0.1861266791820526},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.11649823188781738},{"id":"https://openalex.org/keywords/software-engineering","display_name":"Software engineering","score":0.0826188325881958}],"concepts":[{"id":"https://openalex.org/C40305131","wikidata":"https://www.wikidata.org/wiki/Q2616305","display_name":"Obfuscation","level":2,"score":0.7500101327896118},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7260183095932007},{"id":"https://openalex.org/C77390884","wikidata":"https://www.wikidata.org/wiki/Q217302","display_name":"Application-specific integrated circuit","level":2,"score":0.7010771036148071},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.6181676387786865},{"id":"https://openalex.org/C134835016","wikidata":"https://www.wikidata.org/wiki/Q690265","display_name":"Lookup table","level":2,"score":0.5549394488334656},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.5038830637931824},{"id":"https://openalex.org/C39217717","wikidata":"https://www.wikidata.org/wiki/Q1432354","display_name":"Hardware security module","level":3,"score":0.4734898507595062},{"id":"https://openalex.org/C2777210771","wikidata":"https://www.wikidata.org/wiki/Q4927124","display_name":"Block (permutation group theory)","level":2,"score":0.47213155031204224},{"id":"https://openalex.org/C55166926","wikidata":"https://www.wikidata.org/wiki/Q2892946","display_name":"Oracle","level":2,"score":0.4709171950817108},{"id":"https://openalex.org/C37135326","wikidata":"https://www.wikidata.org/wiki/Q931942","display_name":"Design flow","level":2,"score":0.4688265025615692},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.3792777955532074},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.3317951560020447},{"id":"https://openalex.org/C178489894","wikidata":"https://www.wikidata.org/wiki/Q8789","display_name":"Cryptography","level":2,"score":0.27843764424324036},{"id":"https://openalex.org/C38652104","wikidata":"https://www.wikidata.org/wiki/Q3510521","display_name":"Computer security","level":1,"score":0.1861266791820526},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.11649823188781738},{"id":"https://openalex.org/C115903868","wikidata":"https://www.wikidata.org/wiki/Q80993","display_name":"Software engineering","level":1,"score":0.0826188325881958},{"id":"https://openalex.org/C2524010","wikidata":"https://www.wikidata.org/wiki/Q8087","display_name":"Geometry","level":1,"score":0.0},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/tcad.2023.3244879","is_oa":true,"landing_page_url":"https://doi.org/10.1109/tcad.2023.3244879","pdf_url":"https://ieeexplore.ieee.org/ielx7/43/6917053/10044229.pdf","source":{"id":"https://openalex.org/S100835903","display_name":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","issn_l":"0278-0070","issn":["0278-0070","1937-4151"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":"cc-by","license_id":"https://openalex.org/licenses/cc-by","version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","raw_type":"journal-article"}],"best_oa_location":{"id":"doi:10.1109/tcad.2023.3244879","is_oa":true,"landing_page_url":"https://doi.org/10.1109/tcad.2023.3244879","pdf_url":"https://ieeexplore.ieee.org/ielx7/43/6917053/10044229.pdf","source":{"id":"https://openalex.org/S100835903","display_name":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","issn_l":"0278-0070","issn":["0278-0070","1937-4151"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":"cc-by","license_id":"https://openalex.org/licenses/cc-by","version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","raw_type":"journal-article"},"sustainable_development_goals":[{"display_name":"Industry, innovation and infrastructure","id":"https://metadata.un.org/sdg/9","score":0.41999998688697815}],"awards":[],"funders":[{"id":"https://openalex.org/F4320320300","display_name":"European Commission","ror":"https://ror.org/00k4n6c32"},{"id":"https://openalex.org/F4320338080","display_name":"European Social Fund","ror":"https://ror.org/00k4n6c32"}],"has_content":{"pdf":true,"grobid_xml":true},"content_urls":{"pdf":"https://content.openalex.org/works/W4320713034.pdf","grobid_xml":"https://content.openalex.org/works/W4320713034.grobid-xml"},"referenced_works_count":37,"referenced_works":["https://openalex.org/W1524250393","https://openalex.org/W1546325545","https://openalex.org/W2012725064","https://openalex.org/W2015987974","https://openalex.org/W2028017029","https://openalex.org/W2067276029","https://openalex.org/W2095410905","https://openalex.org/W2112965713","https://openalex.org/W2626492933","https://openalex.org/W2708742051","https://openalex.org/W2747980214","https://openalex.org/W2752013983","https://openalex.org/W2766393343","https://openalex.org/W2771999643","https://openalex.org/W2946336531","https://openalex.org/W2946576051","https://openalex.org/W2949793111","https://openalex.org/W2963001922","https://openalex.org/W2972274212","https://openalex.org/W2998465829","https://openalex.org/W3032908353","https://openalex.org/W3033033241","https://openalex.org/W3092254747","https://openalex.org/W3114561146","https://openalex.org/W3117845485","https://openalex.org/W3132470343","https://openalex.org/W3157690307","https://openalex.org/W3158968530","https://openalex.org/W3176852059","https://openalex.org/W3207940480","https://openalex.org/W4205241157","https://openalex.org/W4212893557","https://openalex.org/W4234937017","https://openalex.org/W4248383989","https://openalex.org/W6669490149","https://openalex.org/W6683245250","https://openalex.org/W6764036932"],"related_works":["https://openalex.org/W3186150091","https://openalex.org/W2759901721","https://openalex.org/W4321192641","https://openalex.org/W2566543615","https://openalex.org/W2911286527","https://openalex.org/W2070693700","https://openalex.org/W4311080747","https://openalex.org/W4378501452","https://openalex.org/W2097839191","https://openalex.org/W3088996813"],"abstract_inverted_index":{"Numerous":[0],"threats":[1,31],"are":[2],"associated":[3],"with":[4,90],"the":[5,39,91,104,118,161,184,210],"globalized":[6],"integrated":[7],"circuit":[8],"(IC)":[9],"supply":[10],"chain,":[11],"such":[12],"as":[13,59,68],"piracy,":[14],"reverse":[15],"engineering,":[16],"overproduction,":[17],"and":[18,108,142,170,177,201],"malicious":[19],"logic":[20,119],"insertion.":[21],"Many":[22],"obfuscation":[23,56,185],"approaches":[24],"have":[25,165],"been":[26],"proposed":[27,140],"to":[28],"mitigate":[29],"these":[30],"by":[32],"preventing":[33],"an":[34,51,121,188],"adversary":[35],"from":[36],"fully":[37],"understanding":[38],"IC":[40,52],"(or":[41],"parts":[42],"of":[43,47,117,223],"it).":[44],"The":[45],"use":[46],"reconfigurable":[48,63],"elements":[49],"inside":[50],"is":[53,85,215],"a":[54,60,69,80,129,220,226,235],"known":[55],"technique,":[57],"either":[58],"coarse":[61],"grain":[62,71],"block":[64],"(i.e.,":[65,73],"eFPGA)":[66],"or":[67],"fine":[70],"element":[72],"FPGA-like":[74],"look-up":[75],"tables).":[76],"This":[77],"paper":[78],"presents":[79],"security-aware":[81],"CAD":[82,101],"flow":[83,102],"that":[84,150,154,183],"LUT-based":[86],"yet":[87],"still":[88],"compatible":[89],"standard":[92],"cell":[93],"based":[94],"physical":[95],"synthesis":[96],"flow.":[97],"More":[98],"precisely,":[99],"our":[100,139],"explores":[103],"FPGA-ASIC":[105],"design":[106,214],"space":[107],"produces":[109],"heavily":[110,136],"obfuscated":[111,212],"designs":[112],"where":[113],"only":[114,155,239],"small":[115],"portions":[116],"resemble":[120],"ASIC.":[122],"Therefore,":[123],"we":[124,164],"term":[125],"this":[126],"specialized":[127],"solution":[128],"\u201chybrid":[130],"ASIC\u201d":[131],"(hASIC).":[132],"Nevertheless,":[133],"even":[134],"for":[135,147,187,197,205],"LUT-dominated":[137],"designs,":[138],"decomposition":[141],"pin":[143],"swapping":[144],"algorithms":[145],"allow":[146],"performance":[148,152],"gains":[149],"enable":[151],"levels":[153],"ASICs":[156],"would":[157],"otherwise":[158],"achieve.":[159],"On":[160],"security":[162,180],"side,":[163],"developed":[166],"novel":[167],"template-based":[168,207],"attacks":[169,200],"also":[171],"applied":[172],"existing":[173],"attacks,":[174],"both":[175],"oracle-free":[176],"oracle-based.":[178],"Our":[179],"analysis":[181],"revealed":[182],"rate":[186],"SHA-256":[189,213],"study":[190],"case":[191],"should":[192],"be":[193],"at":[194,202],"least":[195,203],"45%":[196],"withstanding":[198,206],"traditional":[199],"80%":[204,211],"attacks.":[208],"When":[209],"physically":[216],"implemented,":[217],"it":[218],"achieves":[219,238],"remarkable":[221],"frequency":[222],"368MHz":[224],"in":[225],"65nm":[227],"commercial":[228],"technology,":[229],"whereas":[230],"its":[231],"FPGA":[232],"implementation":[233],"(in":[234],"superior":[236],"technology)":[237],"77MHz.":[240]},"counts_by_year":[{"year":2025,"cited_by_count":10},{"year":2024,"cited_by_count":3},{"year":2023,"cited_by_count":2}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}