{"id":"https://openalex.org/W4312761315","doi":"https://doi.org/10.1109/tcad.2022.3213617","title":"Adaptive Multidimensional Parallel Fault Simulation Framework on Heterogeneous System","display_name":"Adaptive Multidimensional Parallel Fault Simulation Framework on Heterogeneous System","publication_year":2022,"publication_date":"2022-10-11","ids":{"openalex":"https://openalex.org/W4312761315","doi":"https://doi.org/10.1109/tcad.2022.3213617"},"language":"en","primary_location":{"id":"doi:10.1109/tcad.2022.3213617","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tcad.2022.3213617","pdf_url":null,"source":{"id":"https://openalex.org/S100835903","display_name":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","issn_l":"0278-0070","issn":["0278-0070","1937-4151"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5101671748","display_name":"Jingbo Hu","orcid":"https://orcid.org/0000-0003-2720-5594"},"institutions":[{"id":"https://openalex.org/I99065089","display_name":"Tsinghua University","ror":"https://ror.org/03cve4549","country_code":"CN","type":"education","lineage":["https://openalex.org/I99065089"]}],"countries":["CN"],"is_corresponding":true,"raw_author_name":"Jingbo Hu","raw_affiliation_strings":["Department of Electrical Engineering, Tsinghua University, Beijing, China"],"affiliations":[{"raw_affiliation_string":"Department of Electrical Engineering, Tsinghua University, Beijing, China","institution_ids":["https://openalex.org/I99065089"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5102805465","display_name":"Guohao Dai","orcid":"https://orcid.org/0000-0002-8464-0130"},"institutions":[{"id":"https://openalex.org/I183067930","display_name":"Shanghai Jiao Tong University","ror":"https://ror.org/0220qvk04","country_code":"CN","type":"education","lineage":["https://openalex.org/I183067930"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Guohao Dai","raw_affiliation_strings":["Qing Yuan Research Institute, Shanghai Jiao Tong University, Shanghai, China"],"affiliations":[{"raw_affiliation_string":"Qing Yuan Research Institute, Shanghai Jiao Tong University, Shanghai, China","institution_ids":["https://openalex.org/I183067930"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5082611743","display_name":"Liuzheng Wang","orcid":null},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Liuzheng Wang","raw_affiliation_strings":["Architecture and Design Department, HiSilicon Technologies Company Ltd., Shenzhen, China"],"affiliations":[{"raw_affiliation_string":"Architecture and Design Department, HiSilicon Technologies Company Ltd., Shenzhen, China","institution_ids":[]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5080887026","display_name":"Liyang Lai","orcid":"https://orcid.org/0000-0003-1041-8980"},"institutions":[{"id":"https://openalex.org/I32574673","display_name":"Shantou University","ror":"https://ror.org/01a099706","country_code":"CN","type":"education","lineage":["https://openalex.org/I32574673"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Liyang Lai","raw_affiliation_strings":["Department of Electrical Engineering and Guangdong Provincial Key Laboratory of Digital Signal and Image Processing, Shantou University, Shantou, China"],"affiliations":[{"raw_affiliation_string":"Department of Electrical Engineering and Guangdong Provincial Key Laboratory of Digital Signal and Image Processing, Shantou University, Shantou, China","institution_ids":["https://openalex.org/I32574673"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5055069752","display_name":"Yu Huang","orcid":"https://orcid.org/0000-0003-2730-5077"},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Yu Huang","raw_affiliation_strings":["Architecture and Design Department, HiSilicon Technologies Company Ltd., Shenzhen, China"],"affiliations":[{"raw_affiliation_string":"Architecture and Design Department, HiSilicon Technologies Company Ltd., Shenzhen, China","institution_ids":[]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5103867707","display_name":"Huazhong Yang","orcid":null},"institutions":[{"id":"https://openalex.org/I99065089","display_name":"Tsinghua University","ror":"https://ror.org/03cve4549","country_code":"CN","type":"education","lineage":["https://openalex.org/I99065089"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Huazhong Yang","raw_affiliation_strings":["Department of Electrical Engineering, Tsinghua University, Beijing, China"],"affiliations":[{"raw_affiliation_string":"Department of Electrical Engineering, Tsinghua University, Beijing, China","institution_ids":["https://openalex.org/I99065089"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5100445061","display_name":"Yu Wang","orcid":"https://orcid.org/0000-0001-6108-5157"},"institutions":[{"id":"https://openalex.org/I99065089","display_name":"Tsinghua University","ror":"https://ror.org/03cve4549","country_code":"CN","type":"education","lineage":["https://openalex.org/I99065089"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Yu Wang","raw_affiliation_strings":["Department of Electrical Engineering, Tsinghua University, Beijing, China"],"affiliations":[{"raw_affiliation_string":"Department of Electrical Engineering, Tsinghua University, Beijing, China","institution_ids":["https://openalex.org/I99065089"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":7,"corresponding_author_ids":["https://openalex.org/A5101671748"],"corresponding_institution_ids":["https://openalex.org/I99065089"],"apc_list":null,"apc_paid":null,"fwci":1.5894,"has_fulltext":false,"cited_by_count":7,"citation_normalized_percentile":{"value":0.82691234,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":94,"max":97},"biblio":{"volume":"42","issue":"6","first_page":"1951","last_page":"1964"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10743","display_name":"Software Testing and Debugging Techniques","score":0.9933000206947327,"subfield":{"id":"https://openalex.org/subfields/1712","display_name":"Software"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9911999702453613,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.803514301776886},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.7300412654876709},{"id":"https://openalex.org/keywords/scalability","display_name":"Scalability","score":0.7216805815696716},{"id":"https://openalex.org/keywords/supercomputer","display_name":"Supercomputer","score":0.47048142552375793},{"id":"https://openalex.org/keywords/divergence","display_name":"Divergence (linguistics)","score":0.44420474767684937},{"id":"https://openalex.org/keywords/queue","display_name":"Queue","score":0.4388396739959717},{"id":"https://openalex.org/keywords/cuda","display_name":"CUDA","score":0.42882847785949707},{"id":"https://openalex.org/keywords/multi-core-processor","display_name":"Multi-core processor","score":0.4107225835323334}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.803514301776886},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.7300412654876709},{"id":"https://openalex.org/C48044578","wikidata":"https://www.wikidata.org/wiki/Q727490","display_name":"Scalability","level":2,"score":0.7216805815696716},{"id":"https://openalex.org/C83283714","wikidata":"https://www.wikidata.org/wiki/Q121117","display_name":"Supercomputer","level":2,"score":0.47048142552375793},{"id":"https://openalex.org/C207390915","wikidata":"https://www.wikidata.org/wiki/Q1230525","display_name":"Divergence (linguistics)","level":2,"score":0.44420474767684937},{"id":"https://openalex.org/C160403385","wikidata":"https://www.wikidata.org/wiki/Q220543","display_name":"Queue","level":2,"score":0.4388396739959717},{"id":"https://openalex.org/C2778119891","wikidata":"https://www.wikidata.org/wiki/Q477690","display_name":"CUDA","level":2,"score":0.42882847785949707},{"id":"https://openalex.org/C78766204","wikidata":"https://www.wikidata.org/wiki/Q555032","display_name":"Multi-core processor","level":2,"score":0.4107225835323334},{"id":"https://openalex.org/C41895202","wikidata":"https://www.wikidata.org/wiki/Q8162","display_name":"Linguistics","level":1,"score":0.0},{"id":"https://openalex.org/C77088390","wikidata":"https://www.wikidata.org/wiki/Q8513","display_name":"Database","level":1,"score":0.0},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.0},{"id":"https://openalex.org/C138885662","wikidata":"https://www.wikidata.org/wiki/Q5891","display_name":"Philosophy","level":0,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/tcad.2022.3213617","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tcad.2022.3213617","pdf_url":null,"source":{"id":"https://openalex.org/S100835903","display_name":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","issn_l":"0278-0070","issn":["0278-0070","1937-4151"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","raw_type":"journal-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[{"id":"https://openalex.org/G1799421016","display_name":null,"funder_award_id":"61832007","funder_id":"https://openalex.org/F4320321001","funder_display_name":"National Natural Science Foundation of China"},{"id":"https://openalex.org/G6803541034","display_name":null,"funder_award_id":"U21B2031","funder_id":"https://openalex.org/F4320321001","funder_display_name":"National Natural Science Foundation of China"},{"id":"https://openalex.org/G6839492696","display_name":null,"funder_award_id":"U19B2019","funder_id":"https://openalex.org/F4320321001","funder_display_name":"National Natural Science Foundation of China"},{"id":"https://openalex.org/G8262591375","display_name":null,"funder_award_id":"62104128","funder_id":"https://openalex.org/F4320321001","funder_display_name":"National Natural Science Foundation of China"}],"funders":[{"id":"https://openalex.org/F4320314786","display_name":"Xilinx","ror":"https://ror.org/01rb7bk56"},{"id":"https://openalex.org/F4320321001","display_name":"National Natural Science Foundation of China","ror":"https://ror.org/01h0zpd94"},{"id":"https://openalex.org/F4320329777","display_name":"Beijing National Research Center For Information Science And Technology","ror":null}],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":33,"referenced_works":["https://openalex.org/W151183725","https://openalex.org/W1502544429","https://openalex.org/W1588481459","https://openalex.org/W1607075260","https://openalex.org/W1975338463","https://openalex.org/W1988286948","https://openalex.org/W1989218840","https://openalex.org/W2003968955","https://openalex.org/W2012278694","https://openalex.org/W2062716389","https://openalex.org/W2064089677","https://openalex.org/W2078424527","https://openalex.org/W2089540425","https://openalex.org/W2095027279","https://openalex.org/W2110683333","https://openalex.org/W2115359487","https://openalex.org/W2127673274","https://openalex.org/W2130022711","https://openalex.org/W2133250872","https://openalex.org/W2134895826","https://openalex.org/W2145224769","https://openalex.org/W2151762825","https://openalex.org/W2165806469","https://openalex.org/W2171587453","https://openalex.org/W2783576711","https://openalex.org/W2902265613","https://openalex.org/W3146952922","https://openalex.org/W4231385708","https://openalex.org/W4302458519","https://openalex.org/W6629990375","https://openalex.org/W6635090140","https://openalex.org/W6670108224","https://openalex.org/W6679207819"],"related_works":["https://openalex.org/W2384867379","https://openalex.org/W3062287","https://openalex.org/W2380390332","https://openalex.org/W2742145873","https://openalex.org/W4245975140","https://openalex.org/W2329539859","https://openalex.org/W3191490922","https://openalex.org/W2062253548","https://openalex.org/W4225414539","https://openalex.org/W2227905990"],"abstract_inverted_index":{"Fault":[0],"simulation":[1,40,97,105,117,129],"is":[2,15,45,67,93,216,245],"a":[3,156],"critical":[4],"component":[5],"of":[6,42,54,63,78,150,158,172,189,233,235],"the":[7,33,75,86,90,96,104,121,140,148,169,178,183,187,190,197,226,257],"automatic":[8],"test":[9],"pattern":[10],"generation":[11],"(ATPG)":[12],"tool,":[13],"which":[14,48,102],"widely":[16],"used":[17,181],"in":[18,74,182],"chip":[19],"development.":[20],"The":[21,39,61],"CPU\u2013GPU":[22,122],"heterogeneous":[23,123],"system":[24],"can":[25],"accelerate":[26],"fault":[27,116,210,239],"simulation.":[28,191],"However,":[29],"existing":[30],"work":[31],"faces":[32],"following":[34],"challenges:":[35],"1)":[36],"Path":[37],"Divergence:":[38],"path":[41,151],"different":[43,55,64,128,133],"faults":[44],"not":[46,68],"uniform,":[47],"leads":[49],"to":[50,71,132,146,164,185,247],"low":[51],"parallel":[52,115,199],"efficiency":[53],"GPU":[56,91,184,215,244],"threads;":[57],"2)":[58],"Unbalanced":[59],"Workload:":[60],"load":[62,162],"computing":[65,174],"units":[66],"balanced,":[69],"leading":[70],"serious":[72],"differences":[73],"execution":[76,170],"time":[77,171],"each":[79,173],"part;":[80],"and":[81,95,160,168],"3)":[82],"Poor":[83],"Scalability:":[84],"When":[85],"circuit":[87,134],"scale":[88],"increases,":[89],"memory":[92],"limited":[94],"has":[98],"strong":[99],"structural":[100],"dependence,":[101],"makes":[103],"difficult.":[106],"In":[107,136],"this":[108],"work,":[109],"we":[110,138,195],"propose":[111,196],"an":[112],"adaptive":[113],"multidimensional":[114],"framework":[118],"based":[119,212,241],"on":[120,201,213,229,242],"system.":[124],"We":[125,153,176],"adaptively":[126],"select":[127],"approaches":[130],"according":[131],"scales.":[135],"detail,":[137],"use":[139,155],"fanout-free":[141],"region":[142],"(FFR)":[143],"grouping":[144],"method":[145],"solve":[147],"problem":[149],"divergence.":[152],"also":[154],"combination":[157],"static":[159],"dynamic":[161],"balancing":[163],"tradeoff":[165],"data":[166],"handling":[167],"unit.":[175],"limit":[177],"queue":[179],"length":[180],"improve":[186],"scalability":[188],"To":[192],"further":[193],"accelerate,":[194],"4-D":[198],"architecture":[200],"multiple":[202],"GPUs.":[203],"Extensive":[204],"experimental":[205],"results":[206],"show":[207],"that":[208],"our":[209,238],"simulator":[211,240],"8":[214],"<inline-formula":[217,248],"xmlns:mml=\"http://www.w3.org/1998/Math/MathML\"":[218,249],"xmlns:xlink=\"http://www.w3.org/1999/xlink\">":[219,250],"<tex-math":[220,251],"notation=\"LaTeX\">$105.7\\times":[221],"$":[222,253],"</tex-math></inline-formula>":[223,254],"faster":[224,255],"than":[225,256],"commercial":[227],"tool":[228],"average.":[230],"For":[231],"tens":[232],"millions":[234],"gate-level":[236],"circuits,":[237],"one":[243],"up":[246],"notation=\"LaTeX\">$25.9\\times":[252],"CPU":[258],"single-threaded":[259],"simulator.":[260]},"counts_by_year":[{"year":2025,"cited_by_count":2},{"year":2024,"cited_by_count":3},{"year":2023,"cited_by_count":2}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}
