{"id":"https://openalex.org/W4291910403","doi":"https://doi.org/10.1109/tcad.2022.3199307","title":"On Reducing LDE Variations in Modern Analog Placement","display_name":"On Reducing LDE Variations in Modern Analog Placement","publication_year":2022,"publication_date":"2022-08-15","ids":{"openalex":"https://openalex.org/W4291910403","doi":"https://doi.org/10.1109/tcad.2022.3199307"},"language":"en","primary_location":{"id":"doi:10.1109/tcad.2022.3199307","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tcad.2022.3199307","pdf_url":null,"source":{"id":"https://openalex.org/S100835903","display_name":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","issn_l":"0278-0070","issn":["0278-0070","1937-4151"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5098033927","display_name":"A. K. Thasreefa","orcid":null},"institutions":[{"id":"https://openalex.org/I4210120917","display_name":"Taiwan Semiconductor Manufacturing Company (Taiwan)","ror":"https://ror.org/02wx79d08","country_code":"TW","type":"company","lineage":["https://openalex.org/I4210120917"]}],"countries":["TW"],"is_corresponding":true,"raw_author_name":"A. K. Thasreefa","raw_affiliation_strings":["Test Chip Methodology, Taiwan Semiconductor Manufacturing Company Ltd., Hsinchu, Taiwan"],"affiliations":[{"raw_affiliation_string":"Test Chip Methodology, Taiwan Semiconductor Manufacturing Company Ltd., Hsinchu, Taiwan","institution_ids":["https://openalex.org/I4210120917"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5061799084","display_name":"Abhishek Patyal","orcid":"https://orcid.org/0000-0001-7094-7601"},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Abhishek Patyal","raw_affiliation_strings":["Systems Design Group, Synopsys Taiwan Company Ltd., Hsinchu, Taiwan"],"affiliations":[{"raw_affiliation_string":"Systems Design Group, Synopsys Taiwan Company Ltd., Hsinchu, Taiwan","institution_ids":[]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5088127989","display_name":"Hao-Yu Chi","orcid":"https://orcid.org/0000-0002-7719-0119"},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Hao-Yu Chi","raw_affiliation_strings":["Systems Design Group, Synopsys Taiwan Company Ltd., Hsinchu, Taiwan"],"affiliations":[{"raw_affiliation_string":"Systems Design Group, Synopsys Taiwan Company Ltd., Hsinchu, Taiwan","institution_ids":[]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5020643571","display_name":"Mark Po-Hung Lin","orcid":null},"institutions":[{"id":"https://openalex.org/I148366613","display_name":"National Yang Ming Chiao Tung University","ror":"https://ror.org/00se2k293","country_code":"TW","type":"education","lineage":["https://openalex.org/I148366613"]}],"countries":["TW"],"is_corresponding":false,"raw_author_name":"Mark Po-Hung Lin","raw_affiliation_strings":["Institute of Electronics, National Yang Ming Chiao Tung University, Hsinchu, Taiwan"],"affiliations":[{"raw_affiliation_string":"Institute of Electronics, National Yang Ming Chiao Tung University, Hsinchu, Taiwan","institution_ids":["https://openalex.org/I148366613"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5021615416","display_name":"Hung-Ming Chen","orcid":"https://orcid.org/0000-0001-8173-3131"},"institutions":[{"id":"https://openalex.org/I148366613","display_name":"National Yang Ming Chiao Tung University","ror":"https://ror.org/00se2k293","country_code":"TW","type":"education","lineage":["https://openalex.org/I148366613"]}],"countries":["TW"],"is_corresponding":false,"raw_author_name":"Hung-Ming Chen","raw_affiliation_strings":["Institute of Electronics, National Yang Ming Chiao Tung University, Hsinchu, Taiwan"],"affiliations":[{"raw_affiliation_string":"Institute of Electronics, National Yang Ming Chiao Tung University, Hsinchu, Taiwan","institution_ids":["https://openalex.org/I148366613"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":5,"corresponding_author_ids":["https://openalex.org/A5098033927"],"corresponding_institution_ids":["https://openalex.org/I4210120917"],"apc_list":null,"apc_paid":null,"fwci":0.2762,"has_fulltext":false,"cited_by_count":4,"citation_normalized_percentile":{"value":0.52861511,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":91,"max":99},"biblio":{"volume":"42","issue":"4","first_page":"1268","last_page":"1279"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11527","display_name":"3D IC and TSV technologies","score":0.9994000196456909,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11338","display_name":"Advancements in Photolithography Techniques","score":0.9993000030517578,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/multiplier","display_name":"Multiplier (economics)","score":0.5962235331535339},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.5885321497917175},{"id":"https://openalex.org/keywords/analogue-electronics","display_name":"Analogue electronics","score":0.539859414100647},{"id":"https://openalex.org/keywords/transistor","display_name":"Transistor","score":0.5233582258224487},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.4686443507671356},{"id":"https://openalex.org/keywords/electronic-circuit","display_name":"Electronic circuit","score":0.44905614852905273},{"id":"https://openalex.org/keywords/simulated-annealing","display_name":"Simulated annealing","score":0.421044260263443},{"id":"https://openalex.org/keywords/topology","display_name":"Topology (electrical circuits)","score":0.4158175587654114},{"id":"https://openalex.org/keywords/integrated-circuit-layout","display_name":"Integrated circuit layout","score":0.41373831033706665},{"id":"https://openalex.org/keywords/voltage","display_name":"Voltage","score":0.4092669188976288},{"id":"https://openalex.org/keywords/integrated-circuit","display_name":"Integrated circuit","score":0.3425253629684448},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.3168395459651947},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.22733882069587708},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.19162899255752563}],"concepts":[{"id":"https://openalex.org/C124584101","wikidata":"https://www.wikidata.org/wiki/Q1053266","display_name":"Multiplier (economics)","level":2,"score":0.5962235331535339},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.5885321497917175},{"id":"https://openalex.org/C29074008","wikidata":"https://www.wikidata.org/wiki/Q174925","display_name":"Analogue electronics","level":3,"score":0.539859414100647},{"id":"https://openalex.org/C172385210","wikidata":"https://www.wikidata.org/wiki/Q5339","display_name":"Transistor","level":3,"score":0.5233582258224487},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.4686443507671356},{"id":"https://openalex.org/C134146338","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Electronic circuit","level":2,"score":0.44905614852905273},{"id":"https://openalex.org/C126980161","wikidata":"https://www.wikidata.org/wiki/Q863783","display_name":"Simulated annealing","level":2,"score":0.421044260263443},{"id":"https://openalex.org/C184720557","wikidata":"https://www.wikidata.org/wiki/Q7825049","display_name":"Topology (electrical circuits)","level":2,"score":0.4158175587654114},{"id":"https://openalex.org/C2765594","wikidata":"https://www.wikidata.org/wiki/Q2624187","display_name":"Integrated circuit layout","level":3,"score":0.41373831033706665},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.4092669188976288},{"id":"https://openalex.org/C530198007","wikidata":"https://www.wikidata.org/wiki/Q80831","display_name":"Integrated circuit","level":2,"score":0.3425253629684448},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.3168395459651947},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.22733882069587708},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.19162899255752563},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.0},{"id":"https://openalex.org/C162324750","wikidata":"https://www.wikidata.org/wiki/Q8134","display_name":"Economics","level":0,"score":0.0},{"id":"https://openalex.org/C139719470","wikidata":"https://www.wikidata.org/wiki/Q39680","display_name":"Macroeconomics","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/tcad.2022.3199307","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tcad.2022.3199307","pdf_url":null,"source":{"id":"https://openalex.org/S100835903","display_name":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","issn_l":"0278-0070","issn":["0278-0070","1937-4151"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","raw_type":"journal-article"}],"best_oa_location":null,"sustainable_development_goals":[{"display_name":"Affordable and clean energy","score":0.6800000071525574,"id":"https://metadata.un.org/sdg/7"}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":16,"referenced_works":["https://openalex.org/W2015428081","https://openalex.org/W2023347947","https://openalex.org/W2100740271","https://openalex.org/W2109826730","https://openalex.org/W2125411772","https://openalex.org/W2127708750","https://openalex.org/W2141019759","https://openalex.org/W2148808647","https://openalex.org/W2154462472","https://openalex.org/W2304810057","https://openalex.org/W2332691800","https://openalex.org/W2401293503","https://openalex.org/W2905247075","https://openalex.org/W2968824443","https://openalex.org/W3107536670","https://openalex.org/W6656316420"],"related_works":["https://openalex.org/W1610298456","https://openalex.org/W2132947409","https://openalex.org/W2044272038","https://openalex.org/W3144305002","https://openalex.org/W2055936709","https://openalex.org/W2146385727","https://openalex.org/W4254962629","https://openalex.org/W2537272291","https://openalex.org/W1994701518","https://openalex.org/W2135098054"],"abstract_inverted_index":{"Layout-dependent":[0],"(LDEs)":[1],"introduce":[2,82],"an":[3,86],"inevitable":[4],"performance":[5],"degradation":[6],"in":[7,43,58,94],"analog":[8,127,160],"and":[9,34,46,118,137,171],"mixed-signal":[10],"circuit":[11,179],"design":[12,53],"with":[13,73,101],"advanced":[14],"process":[15],"technologies":[16],"below":[17],"90":[18],"nm.":[19],"The":[20],"main":[21],"LDE":[22,99,109,174],"sources,":[23],"including":[24],"the":[25,35,68,83,98,114,119,135,142,153,166,178],"well":[26],"proximity":[27],"effect":[28,38],"(WPE),":[29],"length":[30],"of":[31,49,56,71,85,149],"diffusion":[32],"(LOD),":[33],"oxide-to-oxide":[36],"spacing":[37],"(OSE),":[39],"cause":[40],"substantial":[41],"fluctuations":[42],"carrier":[44],"mobility":[45,88,116],"threshold":[47],"voltage":[48],"transistors.":[50],"In":[51,78],"traditional":[52],"flows,":[54],"impact":[55],"these":[57],"post-layout":[59],"simulation,":[60],"leading":[61],"to":[62,75,96,152],"expensive":[63],"re-design":[64],"iterations":[65],"by":[66],"inspecting":[67],"physical":[69],"locations":[70],"devices":[72],"respect":[74],"one":[76],"another.":[77],"this":[79],"article,":[80],"we":[81],"concept":[84],"ideal":[87],"multiplier":[89,117],"based":[90],"on":[91,113,157],"physics":[92],"models,":[93],"order":[95],"minimize":[97],"effects":[100],"a":[102],"fast":[103],"simulated":[104],"annealing":[105],"algorithm":[106],"through":[107],"various":[108],"alleviating":[110],"operations.":[111],"Based":[112],"introduced":[115],"hierarchical":[120],"B*-tree":[121],"(HB*-tree)":[122],"topological":[123],"representation,":[124],"our":[125],"LDE-aware":[126],"placement":[128],"methodology":[129],"can":[130,169],"simultaneously":[131],"optimize":[132],"not":[133],"only":[134],"area":[136],"wire":[138],"length,":[139],"but":[140],"also":[141],"LDEs,":[143],"while":[144,176],"maintaining":[145],"linear-packing":[146],"time":[147],"complexity":[148],"HB*-trees.":[150],"Compared":[151],"most":[154],"recent":[155],"works":[156],"65":[158],"nm-based":[159],"circuits,":[161],"experimental":[162],"results":[163],"show":[164],"that":[165],"proposed":[167],"method":[168],"effectively":[170],"efficiently":[172],"reduce":[173],"variations,":[175],"improving":[177],"performance.":[180]},"counts_by_year":[{"year":2026,"cited_by_count":1},{"year":2025,"cited_by_count":1},{"year":2024,"cited_by_count":2}],"updated_date":"2026-03-27T14:29:43.386196","created_date":"2025-10-10T00:00:00"}
