{"id":"https://openalex.org/W4293243640","doi":"https://doi.org/10.1109/tcad.2022.3197343","title":"Cut and Forward: Safe and Secure Communication for FPGA System on Chips","display_name":"Cut and Forward: Safe and Secure Communication for FPGA System on Chips","publication_year":2022,"publication_date":"2022-08-09","ids":{"openalex":"https://openalex.org/W4293243640","doi":"https://doi.org/10.1109/tcad.2022.3197343"},"language":"en","primary_location":{"id":"doi:10.1109/tcad.2022.3197343","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tcad.2022.3197343","pdf_url":null,"source":{"id":"https://openalex.org/S100835903","display_name":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","issn_l":"0278-0070","issn":["0278-0070","1937-4151"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5000981593","display_name":"Francesco Restuccia","orcid":"https://orcid.org/0000-0001-6955-1888"},"institutions":[{"id":"https://openalex.org/I36258959","display_name":"University of California San Diego","ror":"https://ror.org/0168r3w48","country_code":"US","type":"education","lineage":["https://openalex.org/I36258959"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Francesco Restuccia","raw_affiliation_strings":["Computer Science and Engineering, University of California at San Diego, San Diego, CA, USA"],"raw_orcid":"https://orcid.org/0000-0001-6955-1888","affiliations":[{"raw_affiliation_string":"Computer Science and Engineering, University of California at San Diego, San Diego, CA, USA","institution_ids":["https://openalex.org/I36258959"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5000231774","display_name":"Ryan Kastner","orcid":"https://orcid.org/0000-0001-9062-5570"},"institutions":[{"id":"https://openalex.org/I36258959","display_name":"University of California San Diego","ror":"https://ror.org/0168r3w48","country_code":"US","type":"education","lineage":["https://openalex.org/I36258959"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Ryan Kastner","raw_affiliation_strings":["Computer Science and Engineering, University of California at San Diego, San Diego, CA, USA"],"raw_orcid":"https://orcid.org/0000-0001-9062-5570","affiliations":[{"raw_affiliation_string":"Computer Science and Engineering, University of California at San Diego, San Diego, CA, USA","institution_ids":["https://openalex.org/I36258959"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":2,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":2.0995,"has_fulltext":false,"cited_by_count":10,"citation_normalized_percentile":{"value":0.86236559,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":94,"max":98},"biblio":{"volume":"41","issue":"11","first_page":"4052","last_page":"4063"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T12122","display_name":"Physical Unclonable Functions (PUFs) and Hardware Security","score":0.9994000196456909,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T12122","display_name":"Physical Unclonable Functions (PUFs) and Hardware Security","score":0.9994000196456909,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9991999864578247,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10502","display_name":"Advanced Memory and Neural Computing","score":0.9983999729156494,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7131353616714478},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.7116325497627258},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.6375232934951782},{"id":"https://openalex.org/keywords/dram","display_name":"Dram","score":0.47970718145370483},{"id":"https://openalex.org/keywords/system-on-a-chip","display_name":"System on a chip","score":0.4373806118965149},{"id":"https://openalex.org/keywords/chip","display_name":"Chip","score":0.4184885025024414},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.2962653934955597},{"id":"https://openalex.org/keywords/telecommunications","display_name":"Telecommunications","score":0.13406598567962646}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7131353616714478},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.7116325497627258},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.6375232934951782},{"id":"https://openalex.org/C7366592","wikidata":"https://www.wikidata.org/wiki/Q1255620","display_name":"Dram","level":2,"score":0.47970718145370483},{"id":"https://openalex.org/C118021083","wikidata":"https://www.wikidata.org/wiki/Q610398","display_name":"System on a chip","level":2,"score":0.4373806118965149},{"id":"https://openalex.org/C165005293","wikidata":"https://www.wikidata.org/wiki/Q1074500","display_name":"Chip","level":2,"score":0.4184885025024414},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.2962653934955597},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.13406598567962646}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/tcad.2022.3197343","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tcad.2022.3197343","pdf_url":null,"source":{"id":"https://openalex.org/S100835903","display_name":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","issn_l":"0278-0070","issn":["0278-0070","1937-4151"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","raw_type":"journal-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[{"id":"https://openalex.org/G456479724","display_name":null,"funder_award_id":"1718586","funder_id":"https://openalex.org/F4320306076","funder_display_name":"National Science Foundation"},{"id":"https://openalex.org/G6623656913","display_name":null,"funder_award_id":"GRC TASK 2993.001","funder_id":"https://openalex.org/F4320306087","funder_display_name":"Semiconductor Research Corporation"}],"funders":[{"id":"https://openalex.org/F4320306076","display_name":"National Science Foundation","ror":"https://ror.org/021nxhr62"},{"id":"https://openalex.org/F4320306087","display_name":"Semiconductor Research Corporation","ror":"https://ror.org/047z4n946"}],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":27,"referenced_works":["https://openalex.org/W1793246495","https://openalex.org/W1965115062","https://openalex.org/W2061205755","https://openalex.org/W2086037506","https://openalex.org/W2092826570","https://openalex.org/W2107571813","https://openalex.org/W2113130027","https://openalex.org/W2141964508","https://openalex.org/W2146970120","https://openalex.org/W2151968406","https://openalex.org/W2155509137","https://openalex.org/W2159319976","https://openalex.org/W2464661970","https://openalex.org/W2626464680","https://openalex.org/W2741018157","https://openalex.org/W3000062206","https://openalex.org/W3034688542","https://openalex.org/W3092347650","https://openalex.org/W3159074911","https://openalex.org/W3166405244","https://openalex.org/W3176436306","https://openalex.org/W4200195825","https://openalex.org/W4283724762","https://openalex.org/W6683884165","https://openalex.org/W6688598517","https://openalex.org/W6766818676","https://openalex.org/W6779702991"],"related_works":["https://openalex.org/W2096844293","https://openalex.org/W2363944576","https://openalex.org/W2351041855","https://openalex.org/W2570254841","https://openalex.org/W2036806516","https://openalex.org/W2065289416","https://openalex.org/W1967394420","https://openalex.org/W2565425548","https://openalex.org/W2392009442","https://openalex.org/W13556768"],"abstract_inverted_index":{"Modern":[0],"FPGA":[1,125,137,176],"system":[2],"on":[3,124,127,154,173],"chips":[4,128],"uses":[5],"complex":[6],"multimanager,":[7],"multisubordinate":[8],"on-chip":[9,29,74],"communication":[10,35,122],"networks.":[11],"Processor":[12],"cores,":[13],"hardware":[14],"accelerators,":[15],"DMA":[16],"engines,":[17],"and":[18,32,42,109,113,131,142,146,156,163,167],"other":[19],"manager":[20],"components":[21,25],"actively":[22],"access":[23,145],"subordinate":[24],"like":[26],"off-chip":[27],"DRAM,":[28],"memories,":[30],"caches,":[31],"I/Os.":[33],"On-chip":[34],"networks":[36],"are":[37],"designed":[38,149],"for":[39,120],"high":[40],"bandwidth":[41],"low":[43],"latency.":[44],"They":[45],"use":[46],"simple,":[47],"fast":[48],"transactions":[49],"that":[50,161],"largely":[51],"assumes":[52],"the":[53,66,70,73,134],"managers":[54,71],"cooperate.":[55],"For":[56],"example,":[57],"it":[58],"does":[59],"not":[60],"describe":[61],"default":[62],"mechanisms":[63],"to":[64,82,139,150],"ensure":[65],"safe":[67,141],"behaviors":[68],"of":[69,78,95,97,136],"using":[72],"interconnect.":[75],"This":[76],"lack":[77],"specification":[79],"can":[80,92],"lead":[81],"unpredictable":[83],"behaviors:":[84],"a":[85,116,174,181],"single":[86],"misbehaving,":[87],"misconfigured,":[88],"or":[89],"malicious":[90],"component":[91],"cause":[93],"denial":[94],"service":[96],"shared":[98],"resources.":[99],"Clearly,":[100],"this":[101],"issue":[102],"is":[103,115,147],"critical":[104],"in":[105,169],"systems":[106,126],"with":[107],"safety":[108,166],"security":[110,168],"constraints.":[111],"Cut":[112,130,162],"forward":[114,132,164],"novel":[117],"switching":[118],"method":[119],"multicomponent":[121],"architectures":[123],"(SoCs).":[129],"leverages":[133],"programmability":[135],"SoCs":[138],"enable":[140],"secure":[143],"bus":[144],"carefully":[148],"minimize":[151],"its":[152],"impact":[153],"performance":[155],"resource":[157],"usage.":[158],"Experiments":[159],"show":[160],"ensures":[165],"realistic":[170],"applications":[171],"deployed":[172],"commercial":[175],"SoC":[177],"from":[178],"Xilinx":[179],"including":[180],"popular":[182],"deep":[183],"neural":[184],"network":[185],"accelerator.":[186]},"counts_by_year":[{"year":2026,"cited_by_count":1},{"year":2025,"cited_by_count":3},{"year":2024,"cited_by_count":4},{"year":2022,"cited_by_count":2}],"updated_date":"2026-06-14T07:44:22.658603","created_date":"2025-10-10T00:00:00"}
