{"id":"https://openalex.org/W4287887519","doi":"https://doi.org/10.1109/tcad.2022.3193646","title":"Leveraging Modern C++ in High-Level Synthesis","display_name":"Leveraging Modern C++ in High-Level Synthesis","publication_year":2022,"publication_date":"2022-07-25","ids":{"openalex":"https://openalex.org/W4287887519","doi":"https://doi.org/10.1109/tcad.2022.3193646"},"language":"en","primary_location":{"id":"doi:10.1109/tcad.2022.3193646","is_oa":true,"landing_page_url":"https://doi.org/10.1109/tcad.2022.3193646","pdf_url":"https://ieeexplore.ieee.org/ielx7/43/10077488/09839291.pdf","source":{"id":"https://openalex.org/S100835903","display_name":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","issn_l":"0278-0070","issn":["0278-0070","1937-4151"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":"cc-by","license_id":"https://openalex.org/licenses/cc-by","version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":true,"oa_status":"hybrid","oa_url":"https://ieeexplore.ieee.org/ielx7/43/10077488/09839291.pdf","any_repository_has_fulltext":true},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5049676900","display_name":"Sakari Lahti","orcid":"https://orcid.org/0000-0002-9915-4784"},"institutions":[{"id":"https://openalex.org/I166825849","display_name":"Tampere University","ror":"https://ror.org/033003e23","country_code":"FI","type":"education","lineage":["https://openalex.org/I166825849"]}],"countries":["FI"],"is_corresponding":true,"raw_author_name":"Sakari Lahti","raw_affiliation_strings":["Unit of Computing Sciences, Tampere University, Tampere, Finland","Unit of Computing Sciences, Tampere University, 33720 Tampere, Finland"],"raw_orcid":"https://orcid.org/0000-0002-9915-4784","affiliations":[{"raw_affiliation_string":"Unit of Computing Sciences, Tampere University, Tampere, Finland","institution_ids":["https://openalex.org/I166825849"]},{"raw_affiliation_string":"Unit of Computing Sciences, Tampere University, 33720 Tampere, Finland","institution_ids":["https://openalex.org/I166825849"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5068408930","display_name":"Matti Rintala","orcid":"https://orcid.org/0000-0002-1780-377X"},"institutions":[{"id":"https://openalex.org/I166825849","display_name":"Tampere University","ror":"https://ror.org/033003e23","country_code":"FI","type":"education","lineage":["https://openalex.org/I166825849"]}],"countries":["FI"],"is_corresponding":false,"raw_author_name":"Matti Rintala","raw_affiliation_strings":["Unit of Computing Sciences, Tampere University, Tampere, Finland","Unit of Computing Sciences, Tampere University, 33720 Tampere, Finland"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Unit of Computing Sciences, Tampere University, Tampere, Finland","institution_ids":["https://openalex.org/I166825849"]},{"raw_affiliation_string":"Unit of Computing Sciences, Tampere University, 33720 Tampere, Finland","institution_ids":["https://openalex.org/I166825849"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5102937415","display_name":"Timo D. H\u00e4m\u00e4l\u00e4inen","orcid":"https://orcid.org/0000-0002-7867-0800"},"institutions":[{"id":"https://openalex.org/I166825849","display_name":"Tampere University","ror":"https://ror.org/033003e23","country_code":"FI","type":"education","lineage":["https://openalex.org/I166825849"]}],"countries":["FI"],"is_corresponding":false,"raw_author_name":"Timo D. H\u00e4m\u00e4l\u00e4inen","raw_affiliation_strings":["Unit of Computing Sciences, Tampere University, Tampere, Finland","Unit of Computing Sciences, Tampere University, 33720 Tampere, Finland"],"raw_orcid":"https://orcid.org/0000-0002-7867-0800","affiliations":[{"raw_affiliation_string":"Unit of Computing Sciences, Tampere University, Tampere, Finland","institution_ids":["https://openalex.org/I166825849"]},{"raw_affiliation_string":"Unit of Computing Sciences, Tampere University, 33720 Tampere, Finland","institution_ids":["https://openalex.org/I166825849"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":["https://openalex.org/A5049676900"],"corresponding_institution_ids":["https://openalex.org/I166825849"],"apc_list":null,"apc_paid":null,"fwci":2.3931,"has_fulltext":true,"cited_by_count":11,"citation_normalized_percentile":{"value":0.88472678,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":96,"max":98},"biblio":{"volume":"42","issue":"4","first_page":"1123","last_page":"1132"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9994999766349792,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9994999766349792,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9984999895095825,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9983000159263611,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7661911249160767},{"id":"https://openalex.org/keywords/high-level-synthesis","display_name":"High-level synthesis","score":0.7208572626113892},{"id":"https://openalex.org/keywords/clarity","display_name":"CLARITY","score":0.5786476731300354},{"id":"https://openalex.org/keywords/code","display_name":"Code (set theory)","score":0.5029405951499939},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.502825915813446},{"id":"https://openalex.org/keywords/limiting","display_name":"Limiting","score":0.4855625331401825},{"id":"https://openalex.org/keywords/programming-language","display_name":"Programming language","score":0.47060948610305786},{"id":"https://openalex.org/keywords/productivity","display_name":"Productivity","score":0.45752274990081787},{"id":"https://openalex.org/keywords/code-generation","display_name":"Code generation","score":0.4174850583076477},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.296979695558548},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.13792353868484497},{"id":"https://openalex.org/keywords/key","display_name":"Key (lock)","score":0.09510990977287292},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.09190568327903748},{"id":"https://openalex.org/keywords/set","display_name":"Set (abstract data type)","score":0.07893067598342896}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7661911249160767},{"id":"https://openalex.org/C58013763","wikidata":"https://www.wikidata.org/wiki/Q5754574","display_name":"High-level synthesis","level":3,"score":0.7208572626113892},{"id":"https://openalex.org/C2777146004","wikidata":"https://www.wikidata.org/wiki/Q14949826","display_name":"CLARITY","level":2,"score":0.5786476731300354},{"id":"https://openalex.org/C2776760102","wikidata":"https://www.wikidata.org/wiki/Q5139990","display_name":"Code (set theory)","level":3,"score":0.5029405951499939},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.502825915813446},{"id":"https://openalex.org/C188198153","wikidata":"https://www.wikidata.org/wiki/Q1613840","display_name":"Limiting","level":2,"score":0.4855625331401825},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.47060948610305786},{"id":"https://openalex.org/C204983608","wikidata":"https://www.wikidata.org/wiki/Q2111958","display_name":"Productivity","level":2,"score":0.45752274990081787},{"id":"https://openalex.org/C133162039","wikidata":"https://www.wikidata.org/wiki/Q1061077","display_name":"Code generation","level":3,"score":0.4174850583076477},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.296979695558548},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.13792353868484497},{"id":"https://openalex.org/C26517878","wikidata":"https://www.wikidata.org/wiki/Q228039","display_name":"Key (lock)","level":2,"score":0.09510990977287292},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.09190568327903748},{"id":"https://openalex.org/C177264268","wikidata":"https://www.wikidata.org/wiki/Q1514741","display_name":"Set (abstract data type)","level":2,"score":0.07893067598342896},{"id":"https://openalex.org/C139719470","wikidata":"https://www.wikidata.org/wiki/Q39680","display_name":"Macroeconomics","level":1,"score":0.0},{"id":"https://openalex.org/C78519656","wikidata":"https://www.wikidata.org/wiki/Q101333","display_name":"Mechanical engineering","level":1,"score":0.0},{"id":"https://openalex.org/C185592680","wikidata":"https://www.wikidata.org/wiki/Q2329","display_name":"Chemistry","level":0,"score":0.0},{"id":"https://openalex.org/C55493867","wikidata":"https://www.wikidata.org/wiki/Q7094","display_name":"Biochemistry","level":1,"score":0.0},{"id":"https://openalex.org/C162324750","wikidata":"https://www.wikidata.org/wiki/Q8134","display_name":"Economics","level":0,"score":0.0}],"mesh":[],"locations_count":2,"locations":[{"id":"doi:10.1109/tcad.2022.3193646","is_oa":true,"landing_page_url":"https://doi.org/10.1109/tcad.2022.3193646","pdf_url":"https://ieeexplore.ieee.org/ielx7/43/10077488/09839291.pdf","source":{"id":"https://openalex.org/S100835903","display_name":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","issn_l":"0278-0070","issn":["0278-0070","1937-4151"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":"cc-by","license_id":"https://openalex.org/licenses/cc-by","version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","raw_type":"journal-article"},{"id":"pmh:oai:trepo.tuni.fi:10024/223057","is_oa":true,"landing_page_url":"https://trepo.tuni.fi/handle/10024/223057","pdf_url":null,"source":{"id":"https://openalex.org/S7407055260","display_name":"Trepo - Institutional Repository of Tampere University","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":null,"host_organization_name":null,"host_organization_lineage":[],"host_organization_lineage_names":[],"type":"repository"},"license":"cc-by","license_id":"https://openalex.org/licenses/cc-by","version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":null,"raw_type":"publishedVersion"}],"best_oa_location":{"id":"doi:10.1109/tcad.2022.3193646","is_oa":true,"landing_page_url":"https://doi.org/10.1109/tcad.2022.3193646","pdf_url":"https://ieeexplore.ieee.org/ielx7/43/10077488/09839291.pdf","source":{"id":"https://openalex.org/S100835903","display_name":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","issn_l":"0278-0070","issn":["0278-0070","1937-4151"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":"cc-by","license_id":"https://openalex.org/licenses/cc-by","version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","raw_type":"journal-article"},"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"pdf":true,"grobid_xml":true},"content_urls":{"pdf":"https://content.openalex.org/works/W4287887519.pdf","grobid_xml":"https://content.openalex.org/works/W4287887519.grobid-xml"},"referenced_works_count":22,"referenced_works":["https://openalex.org/W124174006","https://openalex.org/W200320269","https://openalex.org/W1997102550","https://openalex.org/W2060932829","https://openalex.org/W2087852986","https://openalex.org/W2121075990","https://openalex.org/W2154009134","https://openalex.org/W2166029537","https://openalex.org/W2171318521","https://openalex.org/W2253587711","https://openalex.org/W2331352034","https://openalex.org/W2558370909","https://openalex.org/W2800690434","https://openalex.org/W2895073260","https://openalex.org/W2925360983","https://openalex.org/W2975468520","https://openalex.org/W3036885224","https://openalex.org/W3085407124","https://openalex.org/W3089476745","https://openalex.org/W3108085245","https://openalex.org/W4248294582","https://openalex.org/W6637750486"],"related_works":["https://openalex.org/W2086338133","https://openalex.org/W4367679314","https://openalex.org/W225526533","https://openalex.org/W2078361494","https://openalex.org/W2009234990","https://openalex.org/W4244083766","https://openalex.org/W2612099726","https://openalex.org/W2160632767","https://openalex.org/W2068555872","https://openalex.org/W4252190617"],"abstract_inverted_index":{"High-level":[0],"synthesis":[1],"(HLS)":[2],"enables":[3],"the":[4,55,77,100,110,126,130,147,154,160],"automated":[5],"conversion":[6],"of":[7,92,113,150],"high-level":[8],"language":[9,111,132],"algorithms":[10,18],"into":[11],"synthesizable":[12],"register-transfer":[13],"level":[14],"code,":[15],"allowing":[16],"computation-intensive":[17],"to":[19,68,176],"be":[20],"accelerated":[21],"on":[22],"FPGAs.":[23],"Most":[24],"HLS":[25,56,138,162],"tools":[26,163],"have":[27,59,165],"C++":[28,47,70,105,170],"as":[29,33],"their":[30,119,174],"input":[31],"language,":[32],"it":[34],"is":[35],"widely":[36],"known":[37],"in":[38,106],"both":[39,81],"software":[40],"and":[41,63,85,89,115,117,172],"hardware":[42],"industry.":[43],"However,":[44],"even":[45],"though":[46],"receives":[48],"a":[49,73],"new":[50],"standard":[51],"every":[52],"three":[53],"years,":[54],"tool":[57],"vendors":[58],"mostly":[60],"provided":[61],"support":[62,128,167],"examples":[64],"using":[65,153],"C++98/03.":[66],"Limiting":[67],"early":[69],"standards":[71,79],"imposes":[72],"productivity":[74],"penalty,":[75],"since":[76],"newer":[78,155],"provide":[80,142],"compilation":[82],"time":[83],"reductions":[84],"more":[86],"concise,":[87],"expressive,":[88],"maintainable":[90],"way":[91],"writing":[93],"code.":[94],"In":[95],"this":[96],"study,":[97],"we":[98,141],"make":[99],"case":[101],"for":[102,121,129,168],"adopting":[103],"modern":[104,131,169],"HLS.":[107,122],"We":[108,123,157],"inspect":[109],"features":[112,133],"C++11":[114],"forward,":[116],"consider":[118],"benefits":[120],"also":[124],"test":[125],"present":[127],"with":[134],"two":[135],"state-of-the-art":[136],"commercial":[137],"tools.":[139],"Finally,":[140],"an":[143],"extended":[144],"example,":[145],"demonstrating":[146],"increased":[148],"clarity":[149],"code":[151],"achieved":[152],"standards.":[156],"note":[158],"that":[159],"investigated":[161],"already":[164],"good":[166],"features,":[171],"urge":[173],"adoption":[175],"increase":[177],"designer":[178],"productivity.":[179]},"counts_by_year":[{"year":2025,"cited_by_count":5},{"year":2024,"cited_by_count":3},{"year":2023,"cited_by_count":3}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}
