{"id":"https://openalex.org/W4285303868","doi":"https://doi.org/10.1109/tcad.2022.3184633","title":"Utilizing XMG-Based Synthesis to Preserve Self-Duality for RFET-Based Circuits","display_name":"Utilizing XMG-Based Synthesis to Preserve Self-Duality for RFET-Based Circuits","publication_year":2022,"publication_date":"2022-06-20","ids":{"openalex":"https://openalex.org/W4285303868","doi":"https://doi.org/10.1109/tcad.2022.3184633"},"language":"en","primary_location":{"id":"doi:10.1109/tcad.2022.3184633","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tcad.2022.3184633","pdf_url":null,"source":{"id":"https://openalex.org/S100835903","display_name":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","issn_l":"0278-0070","issn":["0278-0070","1937-4151"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":true,"oa_status":"green","oa_url":"https://infoscience.epfl.ch/handle/20.500.14299/193612","any_repository_has_fulltext":true},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5075349265","display_name":"Shubham Rai","orcid":"https://orcid.org/0000-0002-6522-5628"},"institutions":[{"id":"https://openalex.org/I78650965","display_name":"TU Dresden","ror":"https://ror.org/042aqky30","country_code":"DE","type":"education","lineage":["https://openalex.org/I78650965"]}],"countries":["DE"],"is_corresponding":true,"raw_author_name":"Shubham Rai","raw_affiliation_strings":["Chair for Processor Design, CfAED, Technische Universität Dresden, Dresden, Germany"],"affiliations":[{"raw_affiliation_string":"Chair for Processor Design, CfAED, Technische Universität Dresden, Dresden, Germany","institution_ids":["https://openalex.org/I78650965"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5061118962","display_name":"Alessandro Tempia Calvino","orcid":"https://orcid.org/0000-0003-1312-2907"},"institutions":[{"id":"https://openalex.org/I5124864","display_name":"\u00c9cole Polytechnique F\u00e9d\u00e9rale de Lausanne","ror":"https://ror.org/02s376052","country_code":"CH","type":"education","lineage":["https://openalex.org/I2799323385","https://openalex.org/I5124864"]}],"countries":["CH"],"is_corresponding":false,"raw_author_name":"Alessandro Tempia Calvino","raw_affiliation_strings":["Integrated Systems Laboratory, EPFL, Lausanne, Switzerland"],"affiliations":[{"raw_affiliation_string":"Integrated Systems Laboratory, EPFL, Lausanne, Switzerland","institution_ids":["https://openalex.org/I5124864"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5011120024","display_name":"Heinz Riener","orcid":"https://orcid.org/0000-0003-1527-7160"},"institutions":[{"id":"https://openalex.org/I78650965","display_name":"TU Dresden","ror":"https://ror.org/042aqky30","country_code":"DE","type":"education","lineage":["https://openalex.org/I78650965"]}],"countries":["DE"],"is_corresponding":false,"raw_author_name":"Heinz Riener","raw_affiliation_strings":["Chair for Processor Design, CfAED, Technische Universität Dresden, Dresden, Germany"],"affiliations":[{"raw_affiliation_string":"Chair for Processor Design, CfAED, Technische Universität Dresden, Dresden, Germany","institution_ids":["https://openalex.org/I78650965"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5072927296","display_name":"Giovanni De Micheli","orcid":"https://orcid.org/0000-0002-7827-3215"},"institutions":[{"id":"https://openalex.org/I78650965","display_name":"TU Dresden","ror":"https://ror.org/042aqky30","country_code":"DE","type":"education","lineage":["https://openalex.org/I78650965"]}],"countries":["DE"],"is_corresponding":false,"raw_author_name":"Giovanni De Micheli","raw_affiliation_strings":["Chair for Processor Design, CfAED, Technische Universität Dresden, Dresden, Germany"],"affiliations":[{"raw_affiliation_string":"Chair for Processor Design, CfAED, Technische Universität Dresden, Dresden, Germany","institution_ids":["https://openalex.org/I78650965"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5100755285","display_name":"Akash Kumar","orcid":"https://orcid.org/0000-0001-7125-1737"},"institutions":[{"id":"https://openalex.org/I78650965","display_name":"TU Dresden","ror":"https://ror.org/042aqky30","country_code":"DE","type":"education","lineage":["https://openalex.org/I78650965"]}],"countries":["DE"],"is_corresponding":false,"raw_author_name":"Akash Kumar","raw_affiliation_strings":["Chair for Processor Design, CfAED, Technische Universität Dresden, Dresden, Germany"],"affiliations":[{"raw_affiliation_string":"Chair for Processor Design, CfAED, Technische Universität Dresden, Dresden, Germany","institution_ids":["https://openalex.org/I78650965"]}]}],"institutions":[],"countries_distinct_count":2,"institutions_distinct_count":5,"corresponding_author_ids":["https://openalex.org/A5075349265"],"corresponding_institution_ids":["https://openalex.org/I78650965"],"apc_list":null,"apc_paid":null,"fwci":1.8576,"has_fulltext":false,"cited_by_count":10,"citation_normalized_percentile":{"value":0.84374434,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":91,"max":99},"biblio":{"volume":"42","issue":"3","first_page":"914","last_page":"927"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T12122","display_name":"Physical Unclonable Functions (PUFs) and Hardware Security","score":0.9993000030517578,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T12122","display_name":"Physical Unclonable Functions (PUFs) and Hardware Security","score":0.9993000030517578,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10558","display_name":"Advancements in Semiconductor Devices and Circuit Design","score":0.9988999962806702,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10472","display_name":"Semiconductor materials and devices","score":0.9972000122070312,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/duality","display_name":"Duality (order theory)","score":0.6927781701087952},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.5586049556732178},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.5332702398300171},{"id":"https://openalex.org/keywords/transistor","display_name":"Transistor","score":0.5140434503555298},{"id":"https://openalex.org/keywords/electronic-circuit","display_name":"Electronic circuit","score":0.4957650601863861},{"id":"https://openalex.org/keywords/logic-synthesis","display_name":"Logic synthesis","score":0.45985063910484314},{"id":"https://openalex.org/keywords/representation","display_name":"Representation (politics)","score":0.4270256757736206},{"id":"https://openalex.org/keywords/pass-transistor-logic","display_name":"Pass transistor logic","score":0.41140806674957275},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.33406904339790344},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.3268771767616272},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.2845168113708496},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.19662350416183472},{"id":"https://openalex.org/keywords/digital-electronics","display_name":"Digital electronics","score":0.19156816601753235},{"id":"https://openalex.org/keywords/voltage","display_name":"Voltage","score":0.16777214407920837},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.15481573343276978},{"id":"https://openalex.org/keywords/pure-mathematics","display_name":"Pure mathematics","score":0.07404688000679016}],"concepts":[{"id":"https://openalex.org/C2778023678","wikidata":"https://www.wikidata.org/wiki/Q554403","display_name":"Duality (order theory)","level":2,"score":0.6927781701087952},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.5586049556732178},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.5332702398300171},{"id":"https://openalex.org/C172385210","wikidata":"https://www.wikidata.org/wiki/Q5339","display_name":"Transistor","level":3,"score":0.5140434503555298},{"id":"https://openalex.org/C134146338","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Electronic circuit","level":2,"score":0.4957650601863861},{"id":"https://openalex.org/C157922185","wikidata":"https://www.wikidata.org/wiki/Q173198","display_name":"Logic synthesis","level":3,"score":0.45985063910484314},{"id":"https://openalex.org/C2776359362","wikidata":"https://www.wikidata.org/wiki/Q2145286","display_name":"Representation (politics)","level":3,"score":0.4270256757736206},{"id":"https://openalex.org/C198521697","wikidata":"https://www.wikidata.org/wiki/Q7142438","display_name":"Pass transistor logic","level":4,"score":0.41140806674957275},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.33406904339790344},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.3268771767616272},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.2845168113708496},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.19662350416183472},{"id":"https://openalex.org/C81843906","wikidata":"https://www.wikidata.org/wiki/Q173156","display_name":"Digital electronics","level":3,"score":0.19156816601753235},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.16777214407920837},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.15481573343276978},{"id":"https://openalex.org/C202444582","wikidata":"https://www.wikidata.org/wiki/Q837863","display_name":"Pure mathematics","level":1,"score":0.07404688000679016},{"id":"https://openalex.org/C199539241","wikidata":"https://www.wikidata.org/wiki/Q7748","display_name":"Law","level":1,"score":0.0},{"id":"https://openalex.org/C17744445","wikidata":"https://www.wikidata.org/wiki/Q36442","display_name":"Political science","level":0,"score":0.0},{"id":"https://openalex.org/C94625758","wikidata":"https://www.wikidata.org/wiki/Q7163","display_name":"Politics","level":2,"score":0.0}],"mesh":[],"locations_count":3,"locations":[{"id":"doi:10.1109/tcad.2022.3184633","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tcad.2022.3184633","pdf_url":null,"source":{"id":"https://openalex.org/S100835903","display_name":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","issn_l":"0278-0070","issn":["0278-0070","1937-4151"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","raw_type":"journal-article"},{"id":"pmh:oai:infoscience.epfl.ch:299152","is_oa":true,"landing_page_url":"https://infoscience.epfl.ch/handle/20.500.14299/193612","pdf_url":null,"source":{"id":"https://openalex.org/S4306400487","display_name":"Infoscience (Ecole Polytechnique F\u00e9d\u00e9rale de Lausanne)","issn_l":null,"issn":null,"is_oa":true,"is_in_doaj":false,"is_core":false,"host_organization":null,"host_organization_name":null,"host_organization_lineage":[],"host_organization_lineage_names":[],"type":"repository"},"license":"cc-by-nc-nd","license_id":"https://openalex.org/licenses/cc-by-nc-nd","version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":null,"raw_type":"research article"},{"id":"pmh:oai:qucosa:de:qucosa:80602","is_oa":true,"landing_page_url":"https://tud.qucosa.de/id/qucosa%3A80602","pdf_url":null,"source":{"id":"https://openalex.org/S4377196312","display_name":"Qucosa (Saxon State and University Library Dresden)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I3132420320","host_organization_name":"SLUB Dresden","host_organization_lineage":["https://openalex.org/I3132420320"],"host_organization_lineage_names":[],"type":"repository"},"license":"cc-by","license_id":"https://openalex.org/licenses/cc-by","version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":null,"raw_type":"doc-type:Text"}],"best_oa_location":{"id":"pmh:oai:infoscience.epfl.ch:299152","is_oa":true,"landing_page_url":"https://infoscience.epfl.ch/handle/20.500.14299/193612","pdf_url":null,"source":{"id":"https://openalex.org/S4306400487","display_name":"Infoscience (Ecole Polytechnique F\u00e9d\u00e9rale de Lausanne)","issn_l":null,"issn":null,"is_oa":true,"is_in_doaj":false,"is_core":false,"host_organization":null,"host_organization_name":null,"host_organization_lineage":[],"host_organization_lineage_names":[],"type":"repository"},"license":"cc-by-nc-nd","license_id":"https://openalex.org/licenses/cc-by-nc-nd","version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":null,"raw_type":"research article"},"sustainable_development_goals":[{"id":"https://metadata.un.org/sdg/9","score":0.44999998807907104,"display_name":"Industry, innovation and infrastructure"}],"awards":[{"id":"https://openalex.org/G821014536","display_name":null,"funder_award_id":"439891087","funder_id":"https://openalex.org/F4320320879","funder_display_name":"Deutsche Forschungsgemeinschaft"}],"funders":[{"id":"https://openalex.org/F4320320879","display_name":"Deutsche Forschungsgemeinschaft","ror":"https://ror.org/018mejw64"}],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":60,"referenced_works":["https://openalex.org/W35668030","https://openalex.org/W632399495","https://openalex.org/W1481714151","https://openalex.org/W1483713538","https://openalex.org/W1528837436","https://openalex.org/W1776822698","https://openalex.org/W1977426672","https://openalex.org/W1985457698","https://openalex.org/W1993932586","https://openalex.org/W2001346321","https://openalex.org/W2011829553","https://openalex.org/W2042813319","https://openalex.org/W2050779425","https://openalex.org/W2055215434","https://openalex.org/W2085803561","https://openalex.org/W2100465945","https://openalex.org/W2110737535","https://openalex.org/W2117379410","https://openalex.org/W2125803098","https://openalex.org/W2129183345","https://openalex.org/W2145594740","https://openalex.org/W2150787480","https://openalex.org/W2156694126","https://openalex.org/W2161125053","https://openalex.org/W2166127884","https://openalex.org/W2219292504","https://openalex.org/W2312503676","https://openalex.org/W2322754293","https://openalex.org/W2346682451","https://openalex.org/W2468019634","https://openalex.org/W2563335932","https://openalex.org/W2587608034","https://openalex.org/W2587804194","https://openalex.org/W2607365186","https://openalex.org/W2614074621","https://openalex.org/W2617185248","https://openalex.org/W2786101043","https://openalex.org/W2799027281","https://openalex.org/W2799908977","https://openalex.org/W2889418642","https://openalex.org/W2897947687","https://openalex.org/W2900265717","https://openalex.org/W2906525761","https://openalex.org/W2906629987","https://openalex.org/W2908846298","https://openalex.org/W2913650413","https://openalex.org/W2944997892","https://openalex.org/W2946189651","https://openalex.org/W2982812248","https://openalex.org/W3036425636","https://openalex.org/W3036970922","https://openalex.org/W3185234608","https://openalex.org/W4212945444","https://openalex.org/W4236218105","https://openalex.org/W4239323126","https://openalex.org/W4256548512","https://openalex.org/W4299487805","https://openalex.org/W6601412428","https://openalex.org/W6704780577","https://openalex.org/W6750853391"],"related_works":["https://openalex.org/W2145801698","https://openalex.org/W1968762246","https://openalex.org/W1592843625","https://openalex.org/W1599902002","https://openalex.org/W2146100485","https://openalex.org/W1983471457","https://openalex.org/W4281385583","https://openalex.org/W2757225496","https://openalex.org/W1912101345","https://openalex.org/W2594283002"],"abstract_inverted_index":{"Individual":[0],"transistors":[1,17,23,61],"based":[2],"on":[3],"emerging":[4],"reconfigurable":[5,21],"nanotechnologies":[6],"exhibit":[7],"electrical":[8],"conduction":[9],"for":[10,74,130,166,213],"both":[11],"types":[12],"of":[13,39,79],"charge":[14],"carriers.":[15],"These":[16],"[referred":[18],"to":[19,28,63,69,98,132,217,223],"as":[20,48,106],"field-effect":[22],"(RFETs)]":[24],"enable":[25],"dynamic":[26],"reconfiguration":[27],"demonstrate":[29,159],"either":[30],"a":[31,49,80,118,144,148],"p-":[32],"or":[33],"an":[34],"n-type":[35],"functionality.":[36],"This":[37],"duality":[38],"functionality":[40],"at":[41],"the":[42,64,77,107,154,200,209,224],"transistor":[43],"level":[44],"is":[45],"efficiently":[46,204],"abstracted":[47],"self-dual":[50],"Boolean":[51],"logic,":[52],"that":[53,121,199],"can":[54],"be":[55,84],"physically":[56],"realized":[57],"with":[58,171,185,192,221],"fewer":[59],"RFET":[60],"compared":[62],"contemporary":[65],"CMOS":[66],"technology.":[67],"Consequently,":[68],"achieve":[70],"better":[71],"area":[72,211,219],"reduction":[73],"RFET-based":[75,214],"circuits,":[76],"self-duality":[78,100,134,206],"given":[81],"circuit":[82],"should":[83],"preserved":[85],"during":[86,110,135],"logic":[87,108,111,137],"optimization":[88,178,184,191],"and":[89,113,128,147,168,179,188,207],"technology":[90,114,140],"mapping.":[91,115,195],"In":[92],"this":[93],"article,":[94],"we":[95,142,158],"specifically":[96],"aim":[97],"preserve":[99,133],"by":[101,162],"using":[102],"Xor-majority":[103],"graphs":[104],"(XMGs)":[105],"representation":[109],"synthesis":[112,119,174],"We":[116],"propose":[117],"flow":[120,203],"uses":[122],"new":[123],"restructuring":[124],"techniques,":[125],"called":[126],"rewriting":[127],"resubstitution":[129],"XMGs":[131],"technology-independent":[136],"synthesis.":[138],"For":[139],"mapping,":[141],"use":[143],"novel":[145],"open-source":[146],"logic-representation":[149,193],"agnostic":[150,194],"mapping":[151],"tool.":[152],"Using":[153],"above-proposed":[155],"XMG-based":[156,183,202],"flow,":[157],"its":[160],"benefits":[161],"comparing":[163],"post-mapping":[164],"areas":[165],"synthetic":[167],"cryptographic":[169],"benchmarks":[170],"three":[172],"different":[173],"flows:":[175],"1)":[176],"AIG-based":[177,180,186,190],"mapping;":[181,187],"2)":[182],"3)":[189],"Our":[196],"experiments":[197],"show":[198],"proposed":[201],"preserves":[205],"achieves":[208],"best":[210],"results":[212],"circuits":[215],"(up":[216],"12.36%":[218],"reduction)":[220],"respect":[222],"baseline.":[225]},"counts_by_year":[{"year":2026,"cited_by_count":2},{"year":2025,"cited_by_count":1},{"year":2024,"cited_by_count":2},{"year":2023,"cited_by_count":5}],"updated_date":"2026-03-24T08:02:53.985720","created_date":"2025-10-10T00:00:00"}