{"id":"https://openalex.org/W3205346928","doi":"https://doi.org/10.1109/tcad.2021.3120070","title":"An Incremental Placement Flow for Advanced FPGAs With Timing Awareness","display_name":"An Incremental Placement Flow for Advanced FPGAs With Timing Awareness","publication_year":2021,"publication_date":"2021-10-15","ids":{"openalex":"https://openalex.org/W3205346928","doi":"https://doi.org/10.1109/tcad.2021.3120070","mag":"3205346928"},"language":"en","primary_location":{"id":"doi:10.1109/tcad.2021.3120070","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tcad.2021.3120070","pdf_url":null,"source":{"id":"https://openalex.org/S100835903","display_name":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","issn_l":"0278-0070","issn":["0278-0070","1937-4151"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5101664594","display_name":"Zhifeng Lin","orcid":"https://orcid.org/0000-0002-4597-4322"},"institutions":[{"id":"https://openalex.org/I80947539","display_name":"Fuzhou University","ror":"https://ror.org/011xvna82","country_code":"CN","type":"education","lineage":["https://openalex.org/I80947539"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Zhifeng Lin","raw_affiliation_strings":["College of Mathematics and Computer Science, Fuzhou University, Fuzhou, China"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"College of Mathematics and Computer Science, Fuzhou University, Fuzhou, China","institution_ids":["https://openalex.org/I80947539"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5088784101","display_name":"Yanyue Xie","orcid":"https://orcid.org/0000-0002-4325-521X"},"institutions":[{"id":"https://openalex.org/I12912129","display_name":"Northeastern University","ror":"https://ror.org/04t5xt781","country_code":"US","type":"education","lineage":["https://openalex.org/I12912129"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Yanyue Xie","raw_affiliation_strings":["Department of Electrical and Computer Engineering, Northeastern University, Boston, MA, USA"],"raw_orcid":"https://orcid.org/0000-0002-4325-521X","affiliations":[{"raw_affiliation_string":"Department of Electrical and Computer Engineering, Northeastern University, Boston, MA, USA","institution_ids":["https://openalex.org/I12912129"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5002478857","display_name":"Peng Zou","orcid":"https://orcid.org/0000-0002-8345-0976"},"institutions":[{"id":"https://openalex.org/I24943067","display_name":"Fudan University","ror":"https://ror.org/013q1eq08","country_code":"CN","type":"education","lineage":["https://openalex.org/I24943067"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Peng Zou","raw_affiliation_strings":["State Key Laboratory of ASIC and System, Fudan University, Shanghai, China"],"raw_orcid":"https://orcid.org/0000-0002-8345-0976","affiliations":[{"raw_affiliation_string":"State Key Laboratory of ASIC and System, Fudan University, Shanghai, China","institution_ids":["https://openalex.org/I24943067"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5084837358","display_name":"Sifei Wang","orcid":"https://orcid.org/0000-0002-7408-4118"},"institutions":[{"id":"https://openalex.org/I4210132426","display_name":"Shanghai Fudan Microelectronics (China)","ror":"https://ror.org/02vfj3j86","country_code":"CN","type":"company","lineage":["https://openalex.org/I4210132426"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Sifei Wang","raw_affiliation_strings":["FPGA Department, Shanghai Fudan Microelectronics Group Company, Ltd., Shanghai, China"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"FPGA Department, Shanghai Fudan Microelectronics Group Company, Ltd., Shanghai, China","institution_ids":["https://openalex.org/I4210132426"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5103098516","display_name":"Jun Yu","orcid":"https://orcid.org/0000-0003-4286-9292"},"institutions":[{"id":"https://openalex.org/I24943067","display_name":"Fudan University","ror":"https://ror.org/013q1eq08","country_code":"CN","type":"education","lineage":["https://openalex.org/I24943067"]},{"id":"https://openalex.org/I4210132426","display_name":"Shanghai Fudan Microelectronics (China)","ror":"https://ror.org/02vfj3j86","country_code":"CN","type":"company","lineage":["https://openalex.org/I4210132426"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Jun Yu","raw_affiliation_strings":["State Key Laboratory of ASIC and System, Fudan University, Shanghai, China","FPGA Department, Shanghai Fudan Microelectronics Group Company, Ltd., Shanghai, China"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"State Key Laboratory of ASIC and System, Fudan University, Shanghai, China","institution_ids":["https://openalex.org/I24943067"]},{"raw_affiliation_string":"FPGA Department, Shanghai Fudan Microelectronics Group Company, Ltd., Shanghai, China","institution_ids":["https://openalex.org/I4210132426"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5101854580","display_name":"Jianli Chen","orcid":"https://orcid.org/0000-0002-1391-2696"},"institutions":[{"id":"https://openalex.org/I24943067","display_name":"Fudan University","ror":"https://ror.org/013q1eq08","country_code":"CN","type":"education","lineage":["https://openalex.org/I24943067"]},{"id":"https://openalex.org/I80947539","display_name":"Fuzhou University","ror":"https://ror.org/011xvna82","country_code":"CN","type":"education","lineage":["https://openalex.org/I80947539"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Jianli Chen","raw_affiliation_strings":["State Key Laboratory of ASIC and System, Fudan University, Shanghai, China","Center for Discrete Mathematics and Theoretical Computer Science, Fuzhou University, Fuzhou, China"],"raw_orcid":"https://orcid.org/0000-0002-1391-2696","affiliations":[{"raw_affiliation_string":"State Key Laboratory of ASIC and System, Fudan University, Shanghai, China","institution_ids":["https://openalex.org/I24943067"]},{"raw_affiliation_string":"Center for Discrete Mathematics and Theoretical Computer Science, Fuzhou University, Fuzhou, China","institution_ids":["https://openalex.org/I80947539"]}]}],"institutions":[],"countries_distinct_count":2,"institutions_distinct_count":6,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":0.3051,"has_fulltext":false,"cited_by_count":4,"citation_normalized_percentile":{"value":0.57381344,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":90,"max":96},"biblio":{"volume":"41","issue":"9","first_page":"3092","last_page":"3103"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.8730044364929199},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7317073941230774},{"id":"https://openalex.org/keywords/static-timing-analysis","display_name":"Static timing analysis","score":0.7247173190116882},{"id":"https://openalex.org/keywords/placement","display_name":"Placement","score":0.6331987380981445},{"id":"https://openalex.org/keywords/routing","display_name":"Routing (electronic design automation)","score":0.5830137133598328},{"id":"https://openalex.org/keywords/place-and-route","display_name":"Place and route","score":0.552049458026886},{"id":"https://openalex.org/keywords/path","display_name":"Path (computing)","score":0.5187044739723206},{"id":"https://openalex.org/keywords/critical-path-method","display_name":"Critical path method","score":0.4398016333580017},{"id":"https://openalex.org/keywords/electronic-circuit","display_name":"Electronic circuit","score":0.4223778247833252},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.41385164856910706},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.4070509374141693},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.33375024795532227},{"id":"https://openalex.org/keywords/computer-engineering","display_name":"Computer engineering","score":0.3280358910560608},{"id":"https://openalex.org/keywords/circuit-design","display_name":"Circuit design","score":0.2553443908691406},{"id":"https://openalex.org/keywords/physical-design","display_name":"Physical design","score":0.24256235361099243},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.11912864446640015}],"concepts":[{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.8730044364929199},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7317073941230774},{"id":"https://openalex.org/C93682380","wikidata":"https://www.wikidata.org/wiki/Q2025226","display_name":"Static timing analysis","level":2,"score":0.7247173190116882},{"id":"https://openalex.org/C117690923","wikidata":"https://www.wikidata.org/wiki/Q1484784","display_name":"Placement","level":4,"score":0.6331987380981445},{"id":"https://openalex.org/C74172769","wikidata":"https://www.wikidata.org/wiki/Q1446839","display_name":"Routing (electronic design automation)","level":2,"score":0.5830137133598328},{"id":"https://openalex.org/C127879752","wikidata":"https://www.wikidata.org/wiki/Q3390760","display_name":"Place and route","level":3,"score":0.552049458026886},{"id":"https://openalex.org/C2777735758","wikidata":"https://www.wikidata.org/wiki/Q817765","display_name":"Path (computing)","level":2,"score":0.5187044739723206},{"id":"https://openalex.org/C115874739","wikidata":"https://www.wikidata.org/wiki/Q825377","display_name":"Critical path method","level":2,"score":0.4398016333580017},{"id":"https://openalex.org/C134146338","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Electronic circuit","level":2,"score":0.4223778247833252},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.41385164856910706},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.4070509374141693},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.33375024795532227},{"id":"https://openalex.org/C113775141","wikidata":"https://www.wikidata.org/wiki/Q428691","display_name":"Computer engineering","level":1,"score":0.3280358910560608},{"id":"https://openalex.org/C190560348","wikidata":"https://www.wikidata.org/wiki/Q3245116","display_name":"Circuit design","level":2,"score":0.2553443908691406},{"id":"https://openalex.org/C188817802","wikidata":"https://www.wikidata.org/wiki/Q13426855","display_name":"Physical design","level":3,"score":0.24256235361099243},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.11912864446640015},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.0},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.0},{"id":"https://openalex.org/C201995342","wikidata":"https://www.wikidata.org/wiki/Q682496","display_name":"Systems engineering","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/tcad.2021.3120070","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tcad.2021.3120070","pdf_url":null,"source":{"id":"https://openalex.org/S100835903","display_name":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","issn_l":"0278-0070","issn":["0278-0070","1937-4151"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","raw_type":"journal-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[{"id":"https://openalex.org/G506419027","display_name":null,"funder_award_id":"61977017","funder_id":"https://openalex.org/F4320321001","funder_display_name":"National Natural Science Foundation of China"}],"funders":[{"id":"https://openalex.org/F4320321001","display_name":"National Natural Science Foundation of China","ror":"https://ror.org/01h0zpd94"}],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":32,"referenced_works":["https://openalex.org/W1983950263","https://openalex.org/W2003799216","https://openalex.org/W2015080260","https://openalex.org/W2020461489","https://openalex.org/W2029031086","https://openalex.org/W2067856828","https://openalex.org/W2094806828","https://openalex.org/W2113066134","https://openalex.org/W2124537194","https://openalex.org/W2150281391","https://openalex.org/W2167190617","https://openalex.org/W2235104033","https://openalex.org/W2319154394","https://openalex.org/W2416483345","https://openalex.org/W2533722497","https://openalex.org/W2535860792","https://openalex.org/W2738078952","https://openalex.org/W2770762651","https://openalex.org/W2774510317","https://openalex.org/W2801898382","https://openalex.org/W2897282114","https://openalex.org/W3005126554","https://openalex.org/W3036696276","https://openalex.org/W3091843774","https://openalex.org/W3092270010","https://openalex.org/W3143454515","https://openalex.org/W4234143391","https://openalex.org/W4237144696","https://openalex.org/W4253397218","https://openalex.org/W6682873384","https://openalex.org/W6689434856","https://openalex.org/W6763734198"],"related_works":["https://openalex.org/W2550704533","https://openalex.org/W2890026549","https://openalex.org/W3150210954","https://openalex.org/W2138208643","https://openalex.org/W2160596219","https://openalex.org/W2144122197","https://openalex.org/W3205346928","https://openalex.org/W2135304146","https://openalex.org/W2046316843","https://openalex.org/W2129468521"],"abstract_inverted_index":{"As":[0],"interconnects":[1],"dominate":[2],"circuit":[3],"performance":[4],"in":[5,124],"modern":[6],"field":[7],"programmable":[8],"gate":[9],"arrays":[10],"(FPGAs),":[11],"placement":[12,44,53],"becomes":[13],"a":[14,50,69,88,121],"crucial":[15],"stage":[16],"for":[17,46],"timing":[18,26,66,83,98],"closure.":[19],"Traditional":[20],"FPGA":[21,111],"placers":[22],"seldom":[23],"consider":[24],"the":[25,77,82,140],"constraints":[27],"and,":[28],"thus,":[29],"may":[30],"lead":[31],"to":[32,57,61,75,93,135],"illegal":[33],"routing":[34],"solutions.":[35],"In":[36],"this":[37],"article,":[38],"we":[39,86],"present":[40],"an":[41,109],"incremental":[42],"timing-driven":[43],"flow":[45],"advanced":[47,110],"FPGAs.":[48],"First,":[49],"timing-based":[51],"global":[52],"strategy":[54],"is":[55,73],"designed":[56],"guide":[58],"heterogeneous":[59],"blocks":[60],"desired":[62],"locations":[63],"with":[64,139],"satisfied":[65],"constraints.":[67],"Then,":[68],"timing-aware":[70],"packing":[71],"algorithm":[72,103],"developed":[74],"mitigate":[76],"design":[78],"complexity":[79],"while":[80],"improving":[81],"results.":[84],"Finally,":[85],"propose":[87],"critical":[89],"path-based":[90],"optimization":[91],"method":[92],"generate":[94],"optimized":[95],"layout":[96],"without":[97],"violations.":[99],"We":[100],"evaluate":[101],"our":[102,118],"based":[104],"on":[105],"industrial":[106],"circuits":[107],"using":[108],"device.":[112],"The":[113],"experimental":[114],"results":[115],"show":[116],"that":[117,130],"placer":[119],"achieves":[120],"5.1%":[122],"improvement":[123],"worst":[125],"slack":[126],"and":[127],"produce":[128],"placements":[129],"require":[131],"16.7%":[132],"less":[133],"time":[134],"route":[136],"when":[137],"compared":[138],"leading":[141],"commercial":[142],"tool":[143],"Xilinx":[144],"Vivado.":[145]},"counts_by_year":[{"year":2025,"cited_by_count":1},{"year":2024,"cited_by_count":2},{"year":2023,"cited_by_count":1}],"updated_date":"2026-06-11T09:08:48.828518","created_date":"2025-10-10T00:00:00"}