{"id":"https://openalex.org/W3199918294","doi":"https://doi.org/10.1109/tcad.2021.3114262","title":"High-Speed Adder Design Space Exploration via Graph Neural Processes","display_name":"High-Speed Adder Design Space Exploration via Graph Neural Processes","publication_year":2021,"publication_date":"2021-09-21","ids":{"openalex":"https://openalex.org/W3199918294","doi":"https://doi.org/10.1109/tcad.2021.3114262","mag":"3199918294"},"language":"en","primary_location":{"id":"doi:10.1109/tcad.2021.3114262","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tcad.2021.3114262","pdf_url":null,"source":{"id":"https://openalex.org/S100835903","display_name":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","issn_l":"0278-0070","issn":["0278-0070","1937-4151"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5101413344","display_name":"Hao Geng","orcid":"https://orcid.org/0000-0002-0943-7714"},"institutions":[{"id":"https://openalex.org/I177725633","display_name":"Chinese University of Hong Kong","ror":"https://ror.org/00t33hh48","country_code":"HK","type":"education","lineage":["https://openalex.org/I177725633"]}],"countries":["HK"],"is_corresponding":false,"raw_author_name":"Hao Geng","raw_affiliation_strings":["Department of Computer Science and Engineering, The Chinese University of Hong Kong, Hong Kong, SAR"],"raw_orcid":"https://orcid.org/0000-0002-0943-7714","affiliations":[{"raw_affiliation_string":"Department of Computer Science and Engineering, The Chinese University of Hong Kong, Hong Kong, SAR","institution_ids":["https://openalex.org/I177725633"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5071995111","display_name":"Yuzhe Ma","orcid":"https://orcid.org/0000-0002-3612-4182"},"institutions":[{"id":"https://openalex.org/I177725633","display_name":"Chinese University of Hong Kong","ror":"https://ror.org/00t33hh48","country_code":"HK","type":"education","lineage":["https://openalex.org/I177725633"]}],"countries":["HK"],"is_corresponding":false,"raw_author_name":"Yuzhe Ma","raw_affiliation_strings":["Department of Computer Science and Engineering, The Chinese University of Hong Kong, Hong Kong, SAR"],"raw_orcid":"https://orcid.org/0000-0002-3612-4182","affiliations":[{"raw_affiliation_string":"Department of Computer Science and Engineering, The Chinese University of Hong Kong, Hong Kong, SAR","institution_ids":["https://openalex.org/I177725633"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5031010282","display_name":"Qi Xu","orcid":"https://orcid.org/0000-0002-0375-9800"},"institutions":[{"id":"https://openalex.org/I126520041","display_name":"University of Science and Technology of China","ror":"https://ror.org/04c4dkn09","country_code":"CN","type":"education","lineage":["https://openalex.org/I126520041","https://openalex.org/I19820366"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Qi Xu","raw_affiliation_strings":["School of Microelectronics, University of Science and Technology of China, Hefei, China"],"raw_orcid":"https://orcid.org/0000-0002-0375-9800","affiliations":[{"raw_affiliation_string":"School of Microelectronics, University of Science and Technology of China, Hefei, China","institution_ids":["https://openalex.org/I126520041"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5100675222","display_name":"Jin Miao","orcid":"https://orcid.org/0000-0002-0150-4599"},"institutions":[{"id":"https://openalex.org/I1291425158","display_name":"Google (United States)","ror":"https://ror.org/00njsd438","country_code":"US","type":"company","lineage":["https://openalex.org/I1291425158","https://openalex.org/I4210128969"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Jin Miao","raw_affiliation_strings":["Google, Mountain View, CA, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Google, Mountain View, CA, USA","institution_ids":["https://openalex.org/I1291425158"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5101967869","display_name":"Subhendu Roy","orcid":"https://orcid.org/0000-0001-8554-563X"},"institutions":[{"id":"https://openalex.org/I66217453","display_name":"Cadence Design Systems (United States)","ror":"https://ror.org/04w8xa018","country_code":"US","type":"company","lineage":["https://openalex.org/I66217453"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Subhendu Roy","raw_affiliation_strings":["Design and Sign-Off Group-Machine Learning Group, Cadence Design Systems, San Jose, CA, USA"],"raw_orcid":"https://orcid.org/0000-0001-8554-563X","affiliations":[{"raw_affiliation_string":"Design and Sign-Off Group-Machine Learning Group, Cadence Design Systems, San Jose, CA, USA","institution_ids":["https://openalex.org/I66217453"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5051340429","display_name":"Bei Yu","orcid":"https://orcid.org/0000-0001-6406-4810"},"institutions":[{"id":"https://openalex.org/I177725633","display_name":"Chinese University of Hong Kong","ror":"https://ror.org/00t33hh48","country_code":"HK","type":"education","lineage":["https://openalex.org/I177725633"]}],"countries":["HK"],"is_corresponding":false,"raw_author_name":"Bei Yu","raw_affiliation_strings":["Department of Computer Science and Engineering, The Chinese University of Hong Kong, Hong Kong, SAR"],"raw_orcid":"https://orcid.org/0000-0001-6406-4810","affiliations":[{"raw_affiliation_string":"Department of Computer Science and Engineering, The Chinese University of Hong Kong, Hong Kong, SAR","institution_ids":["https://openalex.org/I177725633"]}]}],"institutions":[],"countries_distinct_count":3,"institutions_distinct_count":4,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":1.8686,"has_fulltext":false,"cited_by_count":26,"citation_normalized_percentile":{"value":0.85761342,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":94,"max":99},"biblio":{"volume":"41","issue":"8","first_page":"2657","last_page":"2670"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9995999932289124,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9995999932289124,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9993000030517578,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9987999796867371,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/adder","display_name":"Adder","score":0.8172756433486938},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6845787763595581},{"id":"https://openalex.org/keywords/very-large-scale-integration","display_name":"Very-large-scale integration","score":0.4792076051235199},{"id":"https://openalex.org/keywords/pareto-principle","display_name":"Pareto principle","score":0.4519313871860504},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.4516984820365906},{"id":"https://openalex.org/keywords/graph","display_name":"Graph","score":0.44653597474098206},{"id":"https://openalex.org/keywords/design-space-exploration","display_name":"Design space exploration","score":0.4385858178138733},{"id":"https://openalex.org/keywords/autoencoder","display_name":"Autoencoder","score":0.4358241558074951},{"id":"https://openalex.org/keywords/artificial-neural-network","display_name":"Artificial neural network","score":0.40242260694503784},{"id":"https://openalex.org/keywords/theoretical-computer-science","display_name":"Theoretical computer science","score":0.39877381920814514},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.3463992178440094},{"id":"https://openalex.org/keywords/artificial-intelligence","display_name":"Artificial intelligence","score":0.27963176369667053},{"id":"https://openalex.org/keywords/mathematical-optimization","display_name":"Mathematical optimization","score":0.2470935881137848},{"id":"https://openalex.org/keywords/latency","display_name":"Latency (audio)","score":0.2088642418384552},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.17235067486763},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.0845385491847992}],"concepts":[{"id":"https://openalex.org/C164620267","wikidata":"https://www.wikidata.org/wiki/Q376953","display_name":"Adder","level":3,"score":0.8172756433486938},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6845787763595581},{"id":"https://openalex.org/C14580979","wikidata":"https://www.wikidata.org/wiki/Q876049","display_name":"Very-large-scale integration","level":2,"score":0.4792076051235199},{"id":"https://openalex.org/C137635306","wikidata":"https://www.wikidata.org/wiki/Q182667","display_name":"Pareto principle","level":2,"score":0.4519313871860504},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.4516984820365906},{"id":"https://openalex.org/C132525143","wikidata":"https://www.wikidata.org/wiki/Q141488","display_name":"Graph","level":2,"score":0.44653597474098206},{"id":"https://openalex.org/C2776221188","wikidata":"https://www.wikidata.org/wiki/Q21072556","display_name":"Design space exploration","level":2,"score":0.4385858178138733},{"id":"https://openalex.org/C101738243","wikidata":"https://www.wikidata.org/wiki/Q786435","display_name":"Autoencoder","level":3,"score":0.4358241558074951},{"id":"https://openalex.org/C50644808","wikidata":"https://www.wikidata.org/wiki/Q192776","display_name":"Artificial neural network","level":2,"score":0.40242260694503784},{"id":"https://openalex.org/C80444323","wikidata":"https://www.wikidata.org/wiki/Q2878974","display_name":"Theoretical computer science","level":1,"score":0.39877381920814514},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.3463992178440094},{"id":"https://openalex.org/C154945302","wikidata":"https://www.wikidata.org/wiki/Q11660","display_name":"Artificial intelligence","level":1,"score":0.27963176369667053},{"id":"https://openalex.org/C126255220","wikidata":"https://www.wikidata.org/wiki/Q141495","display_name":"Mathematical optimization","level":1,"score":0.2470935881137848},{"id":"https://openalex.org/C82876162","wikidata":"https://www.wikidata.org/wiki/Q17096504","display_name":"Latency (audio)","level":2,"score":0.2088642418384552},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.17235067486763},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.0845385491847992},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.0}],"mesh":[],"locations_count":2,"locations":[{"id":"doi:10.1109/tcad.2021.3114262","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tcad.2021.3114262","pdf_url":null,"source":{"id":"https://openalex.org/S100835903","display_name":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","issn_l":"0278-0070","issn":["0278-0070","1937-4151"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","raw_type":"journal-article"},{"id":"pmh:oai:repository.hkust.edu.hk:1783.1-120591","is_oa":false,"landing_page_url":"https://repository.hkust.edu.hk/ir/Record/1783.1-120591","pdf_url":null,"source":{"id":"https://openalex.org/S4306401796","display_name":"Rare & Special e-Zone (The Hong Kong University of Science and Technology)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I200769079","host_organization_name":"Hong Kong University of Science and Technology","host_organization_lineage":["https://openalex.org/I200769079"],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":null,"raw_type":"Article"}],"best_oa_location":null,"sustainable_development_goals":[{"display_name":"Industry, innovation and infrastructure","score":0.6600000262260437,"id":"https://metadata.un.org/sdg/9"}],"awards":[{"id":"https://openalex.org/G1755464029","display_name":null,"funder_award_id":"CUHK14209420","funder_id":"https://openalex.org/F4320321592","funder_display_name":"Research Grants Council, University Grants Committee"}],"funders":[{"id":"https://openalex.org/F4320321592","display_name":"Research Grants Council, University Grants Committee","ror":"https://ror.org/00djwmt25"}],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":42,"referenced_works":["https://openalex.org/W1564638059","https://openalex.org/W1963965124","https://openalex.org/W2061485512","https://openalex.org/W2097117768","https://openalex.org/W2131647018","https://openalex.org/W2141984024","https://openalex.org/W2165698076","https://openalex.org/W2168848751","https://openalex.org/W2194775991","https://openalex.org/W2403021642","https://openalex.org/W2744606792","https://openalex.org/W2794037558","https://openalex.org/W2883160951","https://openalex.org/W2905187565","https://openalex.org/W2919115771","https://openalex.org/W2945250736","https://openalex.org/W3048752520","https://openalex.org/W3092488979","https://openalex.org/W3105444733","https://openalex.org/W3185219798","https://openalex.org/W3185695382","https://openalex.org/W3194360729","https://openalex.org/W3199630607","https://openalex.org/W4200156956","https://openalex.org/W4200520905","https://openalex.org/W4211049957","https://openalex.org/W6638924413","https://openalex.org/W6674916494","https://openalex.org/W6676179485","https://openalex.org/W6681338486","https://openalex.org/W6730084236","https://openalex.org/W6738964360","https://openalex.org/W6751513613","https://openalex.org/W6752040014","https://openalex.org/W6752968661","https://openalex.org/W6758711939","https://openalex.org/W6762549195","https://openalex.org/W6762724357","https://openalex.org/W6766978945","https://openalex.org/W6769040946","https://openalex.org/W6787362515","https://openalex.org/W6790640883"],"related_works":["https://openalex.org/W2159052453","https://openalex.org/W3013693939","https://openalex.org/W4390550886","https://openalex.org/W2566616303","https://openalex.org/W3131327266","https://openalex.org/W2752972570","https://openalex.org/W4297051394","https://openalex.org/W3217463396","https://openalex.org/W2734887215","https://openalex.org/W2015155483"],"abstract_inverted_index":{"Adders":[0],"are":[1],"the":[2,6,23,47,56,62,76,113,131,140,151,155,160],"primary":[3],"components":[4],"in":[5,22,195],"data-path":[7],"logic":[8],"of":[9,75,86,126],"a":[10,19,72,96,101,146,190],"microprocessor,":[11],"and":[12,79,100,175],"thus,":[13],"adder":[14,38,88,128,163],"design":[15,50,63],"has":[16],"been":[17],"always":[18],"critical":[20],"issue":[21],"very":[24],"large-scale":[25],"integration":[26],"(VLSI)":[27],"industry.":[28],"However,":[29],"it":[30],"is":[31,111,134],"infeasible":[32],"for":[33],"designers":[34],"to":[35,46,60,71,139,158],"obtain":[36],"optimal":[37],"architecture":[39],"by":[40],"exhaustively":[41],"running":[42],"EDA":[43],"flow":[44,74],"due":[45,70],"extremely":[48],"large":[49],"space.":[51,64],"Previous":[52],"arts":[53],"have":[54],"proposed":[55],"machine":[57],"learning-based":[58],"framework":[59,149,187],"explore":[61,159],"Nevertheless,":[65],"they":[66],"fall":[67],"into":[68,105],"suboptimality":[69],"two-stage":[73],"learning":[77,125],"process":[78,103],"less":[80],"efficient":[81],"nor":[82],"effective":[83],"feature":[84,124],"representations":[85],"prefix":[87,127,162],"structures.":[89],"In":[90],"this":[91],"article,":[92],"we":[93,144],"first":[94],"integrate":[95],"variational":[97],"graph":[98,152],"autoencoder":[99],"neural":[102,117],"(NP)":[104],"an":[106,137],"end-to-end,":[107],"multibranch":[108],"framework,":[109],"which":[110],"termed":[112],"<italic":[114],"xmlns:mml=\"http://www.w3.org/1998/Math/MathML\"":[115],"xmlns:xlink=\"http://www.w3.org/1999/xlink\">graph":[116],"process</i>":[118],".":[119],"The":[120,177],"former":[121],"performs":[122],"automatic":[123],"structures,":[129],"whilst":[130],"latter":[132],"one":[133],"designed":[135],"as":[136,154,172],"alternative":[138],"Gaussian":[141],"process.":[142],"Then,":[143],"propose":[145],"sequential":[147],"optimization":[148],"with":[150,165,183,200],"NP":[153],"surrogate":[156],"model":[157],"Pareto-optimal":[161],"structures":[164],"tradeoff":[166],"among":[167],"Quality-of-Result":[168],"(QoR)":[169],"metrics,":[170],"such":[171],"power,":[173],"area,":[174],"delay.":[176],"experimental":[178],"results":[179],"show":[180],"that":[181],"compared":[182],"state-of-the-art":[184],"methodologies,":[185],"our":[186],"can":[188],"achieve":[189],"much":[191],"better":[192],"Pareto":[193],"frontier":[194],"multiple":[196],"QoR":[197],"metric":[198],"spaces":[199],"fewer":[201],"design-flow":[202],"evaluations.":[203]},"counts_by_year":[{"year":2026,"cited_by_count":1},{"year":2025,"cited_by_count":6},{"year":2024,"cited_by_count":8},{"year":2023,"cited_by_count":4},{"year":2022,"cited_by_count":7}],"updated_date":"2026-03-27T05:58:40.876381","created_date":"2025-10-10T00:00:00"}