{"id":"https://openalex.org/W3197664379","doi":"https://doi.org/10.1109/tcad.2021.3108704","title":"A Simulation-Guided Paradigm for Logic Synthesis and Verification","display_name":"A Simulation-Guided Paradigm for Logic Synthesis and Verification","publication_year":2021,"publication_date":"2021-08-30","ids":{"openalex":"https://openalex.org/W3197664379","doi":"https://doi.org/10.1109/tcad.2021.3108704","mag":"3197664379"},"language":"en","primary_location":{"id":"doi:10.1109/tcad.2021.3108704","is_oa":true,"landing_page_url":"https://doi.org/10.1109/tcad.2021.3108704","pdf_url":"https://ieeexplore.ieee.org/ielx7/43/9832686/09524746.pdf","source":{"id":"https://openalex.org/S100835903","display_name":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","issn_l":"0278-0070","issn":["0278-0070","1937-4151"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":"cc-by","license_id":"https://openalex.org/licenses/cc-by","version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":true,"oa_status":"hybrid","oa_url":"https://ieeexplore.ieee.org/ielx7/43/9832686/09524746.pdf","any_repository_has_fulltext":true},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5051617290","display_name":"Siang-Yun Lee","orcid":"https://orcid.org/0000-0001-5907-2314"},"institutions":[{"id":"https://openalex.org/I5124864","display_name":"\u00c9cole Polytechnique F\u00e9d\u00e9rale de Lausanne","ror":"https://ror.org/02s376052","country_code":"CH","type":"education","lineage":["https://openalex.org/I2799323385","https://openalex.org/I5124864"]}],"countries":["CH"],"is_corresponding":false,"raw_author_name":"Siang-Yun Lee","raw_affiliation_strings":["Integrated Systems Laboratory, Swiss Federal Institute of Technology Lausanne, Lausanne, Switzerland"],"raw_orcid":"https://orcid.org/0000-0001-5907-2314","affiliations":[{"raw_affiliation_string":"Integrated Systems Laboratory, Swiss Federal Institute of Technology Lausanne, Lausanne, Switzerland","institution_ids":["https://openalex.org/I5124864"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5011120024","display_name":"Heinz Riener","orcid":"https://orcid.org/0000-0003-1527-7160"},"institutions":[{"id":"https://openalex.org/I5124864","display_name":"\u00c9cole Polytechnique F\u00e9d\u00e9rale de Lausanne","ror":"https://ror.org/02s376052","country_code":"CH","type":"education","lineage":["https://openalex.org/I2799323385","https://openalex.org/I5124864"]}],"countries":["CH"],"is_corresponding":false,"raw_author_name":"Heinz Riener","raw_affiliation_strings":["Integrated Systems Laboratory, Swiss Federal Institute of Technology Lausanne, Lausanne, Switzerland"],"raw_orcid":"https://orcid.org/0000-0003-1527-7160","affiliations":[{"raw_affiliation_string":"Integrated Systems Laboratory, Swiss Federal Institute of Technology Lausanne, Lausanne, Switzerland","institution_ids":["https://openalex.org/I5124864"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5110450560","display_name":"Alan Mishchenko","orcid":"https://orcid.org/0009-0004-1303-6261"},"institutions":[{"id":"https://openalex.org/I95457486","display_name":"University of California, Berkeley","ror":"https://ror.org/01an7q238","country_code":"US","type":"education","lineage":["https://openalex.org/I95457486"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Alan Mishchenko","raw_affiliation_strings":["Department of EECS, University of California at Berkeley, Berkeley, CA, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of EECS, University of California at Berkeley, Berkeley, CA, USA","institution_ids":["https://openalex.org/I95457486"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5064568178","display_name":"Robert K. Brayton","orcid":"https://orcid.org/0000-0002-3861-1718"},"institutions":[{"id":"https://openalex.org/I95457486","display_name":"University of California, Berkeley","ror":"https://ror.org/01an7q238","country_code":"US","type":"education","lineage":["https://openalex.org/I95457486"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Robert K. Brayton","raw_affiliation_strings":["Department of EECS, University of California at Berkeley, Berkeley, CA, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of EECS, University of California at Berkeley, Berkeley, CA, USA","institution_ids":["https://openalex.org/I95457486"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5072927296","display_name":"Giovanni De Micheli","orcid":"https://orcid.org/0000-0002-7827-3215"},"institutions":[{"id":"https://openalex.org/I5124864","display_name":"\u00c9cole Polytechnique F\u00e9d\u00e9rale de Lausanne","ror":"https://ror.org/02s376052","country_code":"CH","type":"education","lineage":["https://openalex.org/I2799323385","https://openalex.org/I5124864"]}],"countries":["CH"],"is_corresponding":false,"raw_author_name":"Giovanni De Micheli","raw_affiliation_strings":["Integrated Systems Laboratory, Swiss Federal Institute of Technology Lausanne, Lausanne, Switzerland"],"raw_orcid":"https://orcid.org/0000-0002-7827-3215","affiliations":[{"raw_affiliation_string":"Integrated Systems Laboratory, Swiss Federal Institute of Technology Lausanne, Lausanne, Switzerland","institution_ids":["https://openalex.org/I5124864"]}]}],"institutions":[],"countries_distinct_count":2,"institutions_distinct_count":2,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":2.461,"has_fulltext":true,"cited_by_count":36,"citation_normalized_percentile":{"value":0.90508676,"is_in_top_1_percent":false,"is_in_top_10_percent":true},"cited_by_percentile_year":{"min":96,"max":100},"biblio":{"volume":"41","issue":"8","first_page":"2573","last_page":"2586"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10142","display_name":"Formal Methods in Verification","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1703","display_name":"Computational Theory and Mathematics"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10142","display_name":"Formal Methods in Verification","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1703","display_name":"Computational Theory and Mathematics"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9994999766349792,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7801144123077393},{"id":"https://openalex.org/keywords/boolean-satisfiability-problem","display_name":"Boolean satisfiability problem","score":0.7160059213638306},{"id":"https://openalex.org/keywords/formal-equivalence-checking","display_name":"Formal equivalence checking","score":0.6173067092895508},{"id":"https://openalex.org/keywords/equivalence","display_name":"Equivalence (formal languages)","score":0.6092160940170288},{"id":"https://openalex.org/keywords/boolean-function","display_name":"Boolean function","score":0.5642825365066528},{"id":"https://openalex.org/keywords/and-inverter-graph","display_name":"And-inverter graph","score":0.5629035830497742},{"id":"https://openalex.org/keywords/reduction","display_name":"Reduction (mathematics)","score":0.5125793814659119},{"id":"https://openalex.org/keywords/model-checking","display_name":"Model checking","score":0.49628812074661255},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.4747141897678375},{"id":"https://openalex.org/keywords/theoretical-computer-science","display_name":"Theoretical computer science","score":0.45232754945755005},{"id":"https://openalex.org/keywords/formal-verification","display_name":"Formal verification","score":0.4176388680934906},{"id":"https://openalex.org/keywords/combinational-logic","display_name":"Combinational logic","score":0.41295433044433594},{"id":"https://openalex.org/keywords/boolean-circuit","display_name":"Boolean circuit","score":0.349600613117218},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.34430649876594543},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.3385205566883087},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.13580727577209473}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7801144123077393},{"id":"https://openalex.org/C6943359","wikidata":"https://www.wikidata.org/wiki/Q875276","display_name":"Boolean satisfiability problem","level":2,"score":0.7160059213638306},{"id":"https://openalex.org/C96654402","wikidata":"https://www.wikidata.org/wiki/Q5469962","display_name":"Formal equivalence checking","level":3,"score":0.6173067092895508},{"id":"https://openalex.org/C2780069185","wikidata":"https://www.wikidata.org/wiki/Q7977945","display_name":"Equivalence (formal languages)","level":2,"score":0.6092160940170288},{"id":"https://openalex.org/C187455244","wikidata":"https://www.wikidata.org/wiki/Q942353","display_name":"Boolean function","level":2,"score":0.5642825365066528},{"id":"https://openalex.org/C196836630","wikidata":"https://www.wikidata.org/wiki/Q4753279","display_name":"And-inverter graph","level":4,"score":0.5629035830497742},{"id":"https://openalex.org/C111335779","wikidata":"https://www.wikidata.org/wiki/Q3454686","display_name":"Reduction (mathematics)","level":2,"score":0.5125793814659119},{"id":"https://openalex.org/C110251889","wikidata":"https://www.wikidata.org/wiki/Q1569697","display_name":"Model checking","level":2,"score":0.49628812074661255},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.4747141897678375},{"id":"https://openalex.org/C80444323","wikidata":"https://www.wikidata.org/wiki/Q2878974","display_name":"Theoretical computer science","level":1,"score":0.45232754945755005},{"id":"https://openalex.org/C111498074","wikidata":"https://www.wikidata.org/wiki/Q173326","display_name":"Formal verification","level":2,"score":0.4176388680934906},{"id":"https://openalex.org/C81409106","wikidata":"https://www.wikidata.org/wiki/Q76505","display_name":"Combinational logic","level":3,"score":0.41295433044433594},{"id":"https://openalex.org/C141796577","wikidata":"https://www.wikidata.org/wiki/Q837479","display_name":"Boolean circuit","level":3,"score":0.349600613117218},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.34430649876594543},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.3385205566883087},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.13580727577209473},{"id":"https://openalex.org/C2524010","wikidata":"https://www.wikidata.org/wiki/Q8087","display_name":"Geometry","level":1,"score":0.0},{"id":"https://openalex.org/C118615104","wikidata":"https://www.wikidata.org/wiki/Q121416","display_name":"Discrete mathematics","level":1,"score":0.0}],"mesh":[],"locations_count":2,"locations":[{"id":"doi:10.1109/tcad.2021.3108704","is_oa":true,"landing_page_url":"https://doi.org/10.1109/tcad.2021.3108704","pdf_url":"https://ieeexplore.ieee.org/ielx7/43/9832686/09524746.pdf","source":{"id":"https://openalex.org/S100835903","display_name":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","issn_l":"0278-0070","issn":["0278-0070","1937-4151"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":"cc-by","license_id":"https://openalex.org/licenses/cc-by","version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","raw_type":"journal-article"},{"id":"pmh:oai:infoscience.epfl.ch:295496","is_oa":true,"landing_page_url":"https://infoscience.epfl.ch/handle/20.500.14299/189591","pdf_url":null,"source":{"id":"https://openalex.org/S4306400487","display_name":"Infoscience (Ecole Polytechnique F\u00e9d\u00e9rale de Lausanne)","issn_l":null,"issn":null,"is_oa":true,"is_in_doaj":false,"is_core":false,"host_organization":null,"host_organization_name":null,"host_organization_lineage":[],"host_organization_lineage_names":[],"type":"repository"},"license":"cc-by-nc-nd","license_id":"https://openalex.org/licenses/cc-by-nc-nd","version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":null,"raw_type":"research article"}],"best_oa_location":{"id":"doi:10.1109/tcad.2021.3108704","is_oa":true,"landing_page_url":"https://doi.org/10.1109/tcad.2021.3108704","pdf_url":"https://ieeexplore.ieee.org/ielx7/43/9832686/09524746.pdf","source":{"id":"https://openalex.org/S100835903","display_name":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","issn_l":"0278-0070","issn":["0278-0070","1937-4151"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":"cc-by","license_id":"https://openalex.org/licenses/cc-by","version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","raw_type":"journal-article"},"sustainable_development_goals":[],"awards":[{"id":"https://openalex.org/G4031396262","display_name":null,"funder_award_id":"200021_1920981","funder_id":"https://openalex.org/F4320320924","funder_display_name":"Schweizerischer Nationalfonds zur F\u00f6rderung der Wissenschaftlichen Forschung"},{"id":"https://openalex.org/G5758087479","display_name":null,"funder_award_id":"2867.001","funder_id":"https://openalex.org/F4320306087","funder_display_name":"Semiconductor Research Corporation"}],"funders":[{"id":"https://openalex.org/F4320306087","display_name":"Semiconductor Research Corporation","ror":"https://ror.org/047z4n946"},{"id":"https://openalex.org/F4320320915","display_name":"\u00c9cole Polytechnique F\u00e9d\u00e9rale de Lausanne","ror":"https://ror.org/02s376052"},{"id":"https://openalex.org/F4320320924","display_name":"Schweizerischer Nationalfonds zur F\u00f6rderung der Wissenschaftlichen Forschung","ror":"https://ror.org/00yjd3n13"}],"has_content":{"pdf":true,"grobid_xml":true},"content_urls":{"pdf":"https://content.openalex.org/works/W3197664379.pdf","grobid_xml":"https://content.openalex.org/works/W3197664379.grobid-xml"},"referenced_works_count":41,"referenced_works":["https://openalex.org/W1528837436","https://openalex.org/W1612810659","https://openalex.org/W1986086062","https://openalex.org/W1993932586","https://openalex.org/W1994143452","https://openalex.org/W1994730253","https://openalex.org/W2003979824","https://openalex.org/W2007701500","https://openalex.org/W2013784404","https://openalex.org/W2021709993","https://openalex.org/W2035561773","https://openalex.org/W2060407451","https://openalex.org/W2080267935","https://openalex.org/W2098244894","https://openalex.org/W2098667711","https://openalex.org/W2106950603","https://openalex.org/W2111994103","https://openalex.org/W2114394884","https://openalex.org/W2125024536","https://openalex.org/W2125803098","https://openalex.org/W2129183345","https://openalex.org/W2133085302","https://openalex.org/W2133527541","https://openalex.org/W2140132043","https://openalex.org/W2140975144","https://openalex.org/W2158395308","https://openalex.org/W2159871346","https://openalex.org/W2166566648","https://openalex.org/W2166795801","https://openalex.org/W2169375167","https://openalex.org/W2587804194","https://openalex.org/W2617185248","https://openalex.org/W2786101043","https://openalex.org/W2906525761","https://openalex.org/W2946189651","https://openalex.org/W3028892935","https://openalex.org/W3036172124","https://openalex.org/W4233996121","https://openalex.org/W4299487805","https://openalex.org/W6601412428","https://openalex.org/W6636505876"],"related_works":["https://openalex.org/W2150974517","https://openalex.org/W2078076811","https://openalex.org/W35365073","https://openalex.org/W2148332793","https://openalex.org/W2348129335","https://openalex.org/W4241989857","https://openalex.org/W2109676928","https://openalex.org/W1745650241","https://openalex.org/W2166827623","https://openalex.org/W1998291836"],"abstract_inverted_index":{"This":[0],"article":[1],"proposes":[2],"a":[3,57,91,120,135,148],"new":[4],"logic":[5,85,180],"synthesis":[6,86,181],"and":[7,32,54,56,79,90],"verification":[8,33,92],"paradigm":[9],"based":[10],"on":[11],"circuit":[12],"simulation.":[13],"In":[14,104,155],"this":[15,102],"paradigm,":[16,132],"high":[17],"quality,":[18],"expressive":[19,49,174],"simulation":[20,50,108,175],"patterns":[21,51,70,109,176],"are":[22,52,71,97,110],"pregenerated":[23],"to":[24,47,60,73,119,145],"be":[25,74],"reused":[26],"in":[27,36,123,138,178],"multiple":[28],"runs":[29],"of":[30,100,115,141,161,172],"optimization":[31,116],"algorithms,":[34],"resulting":[35],"reduced":[37,166],"time-consuming":[38],"Boolean":[39,88,106],"computations":[40],"such":[41],"as":[42],"satisfiability":[43],"(SAT)":[44],"solving.":[45],"Methods":[46],"generate":[48],"presented":[53],"compared,":[55],"bit-packing":[58],"technique":[59],"compress":[61],"them":[62],"is":[63,165],"integrated":[64],"into":[65],"the":[66,125,130,139,159,170,173],"implementation.":[67],"The":[68],"generated":[69],"shown":[72],"reusable":[75],"across":[76],"different":[77],"algorithms":[78],"after":[80],"network":[81],"function":[82],"modifications.":[83],"A":[84],"algorithm,":[87,93,151],"resubstitution,":[89,107],"combinational":[94],"equivalence":[95,157],"checking,":[96,158],"two":[98],"examples":[99],"using":[101],"paradigm.":[103],"simulation-guided":[105,156],"used":[111],"for":[112],"efficient":[113],"filtering":[114],"choices,":[117],"leading":[118],"lower":[121],"cost":[122],"expanding":[124],"search":[126],"space.":[127],"By":[128],"adopting":[129],"proposed":[131],"we":[133],"achieve":[134],"5.9%":[136],"reduction":[137],"number":[140,160],"AIG":[142],"nodes,":[143],"compared":[144],"3.7%":[146],"by":[147,167],"state-of-the-art":[149],"resubstitution":[150],"within":[152],"comparable":[153],"runtime.":[154],"SAT":[162],"solver":[163],"calls":[164],"9.5%":[168],"with":[169],"use":[171],"accumulated":[177],"earlier":[179],"stages.":[182]},"counts_by_year":[{"year":2026,"cited_by_count":3},{"year":2025,"cited_by_count":16},{"year":2024,"cited_by_count":6},{"year":2023,"cited_by_count":8},{"year":2022,"cited_by_count":3}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}