{"id":"https://openalex.org/W4243492124","doi":"https://doi.org/10.1109/tcad.2021.3101715","title":"Migrating Assertions From Dense to Discrete Time","display_name":"Migrating Assertions From Dense to Discrete Time","publication_year":2021,"publication_date":"2021-08-02","ids":{"openalex":"https://openalex.org/W4243492124","doi":"https://doi.org/10.1109/tcad.2021.3101715"},"language":"en","primary_location":{"id":"doi:10.1109/tcad.2021.3101715","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tcad.2021.3101715","pdf_url":null,"source":{"id":"https://openalex.org/S100835903","display_name":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","issn_l":"0278-0070","issn":["0278-0070","1937-4151"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5084186243","display_name":"Sudipa Mandal","orcid":"https://orcid.org/0000-0002-8952-3638"},"institutions":[{"id":"https://openalex.org/I145894827","display_name":"Indian Institute of Technology Kharagpur","ror":"https://ror.org/03w5sq511","country_code":"IN","type":"education","lineage":["https://openalex.org/I145894827"]}],"countries":["IN"],"is_corresponding":false,"raw_author_name":"Sudipa Mandal","raw_affiliation_strings":["Department of Computer Science and Engineering, Indian Institute of Technology Kharagpur, Kharagpur, India"],"raw_orcid":"https://orcid.org/0000-0002-8952-3638","affiliations":[{"raw_affiliation_string":"Department of Computer Science and Engineering, Indian Institute of Technology Kharagpur, Kharagpur, India","institution_ids":["https://openalex.org/I145894827"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5033329960","display_name":"Pallab Dasgupta","orcid":"https://orcid.org/0000-0002-2178-8154"},"institutions":[{"id":"https://openalex.org/I145894827","display_name":"Indian Institute of Technology Kharagpur","ror":"https://ror.org/03w5sq511","country_code":"IN","type":"education","lineage":["https://openalex.org/I145894827"]}],"countries":["IN"],"is_corresponding":false,"raw_author_name":"Pallab Dasgupta","raw_affiliation_strings":["Department of Computer Science and Engineering, Indian Institute of Technology Kharagpur, Kharagpur, India"],"raw_orcid":"https://orcid.org/0000-0002-2178-8154","affiliations":[{"raw_affiliation_string":"Department of Computer Science and Engineering, Indian Institute of Technology Kharagpur, Kharagpur, India","institution_ids":["https://openalex.org/I145894827"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":2,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":0.1522,"has_fulltext":false,"cited_by_count":1,"citation_normalized_percentile":{"value":0.56904146,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":90,"max":94},"biblio":{"volume":"41","issue":"7","first_page":"2362","last_page":"2371"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10142","display_name":"Formal Methods in Verification","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1703","display_name":"Computational Theory and Mathematics"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10142","display_name":"Formal Methods in Verification","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1703","display_name":"Computational Theory and Mathematics"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/assertion","display_name":"Assertion","score":0.9412933588027954},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7236040234565735},{"id":"https://openalex.org/keywords/granularity","display_name":"Granularity","score":0.6426182389259338},{"id":"https://openalex.org/keywords/analog-signal","display_name":"Analog signal","score":0.5418393015861511},{"id":"https://openalex.org/keywords/signal","display_name":"SIGNAL (programming language)","score":0.5360114574432373},{"id":"https://openalex.org/keywords/clock-signal","display_name":"Clock signal","score":0.5216434597969055},{"id":"https://openalex.org/keywords/boundary","display_name":"Boundary (topology)","score":0.48450109362602234},{"id":"https://openalex.org/keywords/boundary-scan","display_name":"Boundary scan","score":0.4680953323841095},{"id":"https://openalex.org/keywords/mixed-signal-integrated-circuit","display_name":"Mixed-signal integrated circuit","score":0.4471827745437622},{"id":"https://openalex.org/keywords/analog-computer","display_name":"Analog computer","score":0.4263400435447693},{"id":"https://openalex.org/keywords/computer-engineering","display_name":"Computer engineering","score":0.3954182267189026},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.3926890790462494},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.3247249722480774},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.2988321781158447},{"id":"https://openalex.org/keywords/integrated-circuit","display_name":"Integrated circuit","score":0.2501097321510315},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.14059022068977356},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.13884922862052917},{"id":"https://openalex.org/keywords/digital-signal-processing","display_name":"Digital signal processing","score":0.11886906623840332},{"id":"https://openalex.org/keywords/jitter","display_name":"Jitter","score":0.11781322956085205},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.10589754581451416},{"id":"https://openalex.org/keywords/telecommunications","display_name":"Telecommunications","score":0.10207623243331909},{"id":"https://openalex.org/keywords/programming-language","display_name":"Programming language","score":0.09689804911613464}],"concepts":[{"id":"https://openalex.org/C40422974","wikidata":"https://www.wikidata.org/wiki/Q741248","display_name":"Assertion","level":2,"score":0.9412933588027954},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7236040234565735},{"id":"https://openalex.org/C177774035","wikidata":"https://www.wikidata.org/wiki/Q1246948","display_name":"Granularity","level":2,"score":0.6426182389259338},{"id":"https://openalex.org/C13412647","wikidata":"https://www.wikidata.org/wiki/Q174948","display_name":"Analog signal","level":3,"score":0.5418393015861511},{"id":"https://openalex.org/C2779843651","wikidata":"https://www.wikidata.org/wiki/Q7390335","display_name":"SIGNAL (programming language)","level":2,"score":0.5360114574432373},{"id":"https://openalex.org/C137059387","wikidata":"https://www.wikidata.org/wiki/Q426882","display_name":"Clock signal","level":3,"score":0.5216434597969055},{"id":"https://openalex.org/C62354387","wikidata":"https://www.wikidata.org/wiki/Q875399","display_name":"Boundary (topology)","level":2,"score":0.48450109362602234},{"id":"https://openalex.org/C992767","wikidata":"https://www.wikidata.org/wiki/Q895156","display_name":"Boundary scan","level":3,"score":0.4680953323841095},{"id":"https://openalex.org/C62907940","wikidata":"https://www.wikidata.org/wiki/Q1541329","display_name":"Mixed-signal integrated circuit","level":3,"score":0.4471827745437622},{"id":"https://openalex.org/C90915687","wikidata":"https://www.wikidata.org/wiki/Q63759","display_name":"Analog computer","level":2,"score":0.4263400435447693},{"id":"https://openalex.org/C113775141","wikidata":"https://www.wikidata.org/wiki/Q428691","display_name":"Computer engineering","level":1,"score":0.3954182267189026},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.3926890790462494},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.3247249722480774},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.2988321781158447},{"id":"https://openalex.org/C530198007","wikidata":"https://www.wikidata.org/wiki/Q80831","display_name":"Integrated circuit","level":2,"score":0.2501097321510315},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.14059022068977356},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.13884922862052917},{"id":"https://openalex.org/C84462506","wikidata":"https://www.wikidata.org/wiki/Q173142","display_name":"Digital signal processing","level":2,"score":0.11886906623840332},{"id":"https://openalex.org/C134652429","wikidata":"https://www.wikidata.org/wiki/Q1052698","display_name":"Jitter","level":2,"score":0.11781322956085205},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.10589754581451416},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.10207623243331909},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.09689804911613464},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.0},{"id":"https://openalex.org/C134306372","wikidata":"https://www.wikidata.org/wiki/Q7754","display_name":"Mathematical analysis","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/tcad.2021.3101715","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tcad.2021.3101715","pdf_url":null,"source":{"id":"https://openalex.org/S100835903","display_name":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","issn_l":"0278-0070","issn":["0278-0070","1937-4151"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","raw_type":"journal-article"}],"best_oa_location":null,"sustainable_development_goals":[{"id":"https://metadata.un.org/sdg/10","score":0.8100000023841858,"display_name":"Reduced inequalities"}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":26,"referenced_works":["https://openalex.org/W6669264","https://openalex.org/W1533557569","https://openalex.org/W1547304883","https://openalex.org/W1608292181","https://openalex.org/W1972085901","https://openalex.org/W1975120975","https://openalex.org/W1991079660","https://openalex.org/W2016719768","https://openalex.org/W2049399166","https://openalex.org/W2049696538","https://openalex.org/W2051874670","https://openalex.org/W2147263744","https://openalex.org/W2161425891","https://openalex.org/W2172085120","https://openalex.org/W2343845377","https://openalex.org/W2469998798","https://openalex.org/W2795807184","https://openalex.org/W2895557151","https://openalex.org/W2921224415","https://openalex.org/W2963838659","https://openalex.org/W3041259634","https://openalex.org/W3101384075","https://openalex.org/W3106225727","https://openalex.org/W3108121382","https://openalex.org/W4235485872","https://openalex.org/W4255744499"],"related_works":["https://openalex.org/W2007207109","https://openalex.org/W1560200347","https://openalex.org/W2783385538","https://openalex.org/W4243492124","https://openalex.org/W13047877","https://openalex.org/W2100734450","https://openalex.org/W2966162830","https://openalex.org/W1994708634","https://openalex.org/W404391717","https://openalex.org/W4319951280"],"abstract_inverted_index":{"Mixed-signal":[0],"assertions":[1,50],"need":[2],"to":[3,36,55,61,80],"be":[4],"monitored":[5],"over":[6],"dense":[7],"time":[8],"during":[9],"analog":[10,13,42,49],"simulation":[11,27,39],"because":[12],"events":[14],"are":[15,76],"not":[16,77],"aligned":[17],"with":[18],"clock":[19,102],"boundaries":[20],"in":[21,44,64,83,106],"general.":[22],"On":[23],"the":[24,38,41,45,48,52,56,65,81,87,98,101,107],"other":[25],"hand,":[26],"of":[28,40,100],"large":[29],"integrated":[30],"circuits":[31],"regularly":[32],"employs":[33],"clocked":[34],"approximations":[35],"accelerate":[37],"content":[43],"design.":[46],"Migrating":[47],"from":[51],"continuous":[53],"setting":[54,58],"discrete":[57],"is":[59],"necessary":[60],"monitor":[62],"compliance":[63],"digital\u2013analog":[66],"boundary,":[67],"but":[68],"such":[69],"migration":[70,92],"must":[71],"ensure":[72],"that":[73],"assertion":[74,105],"failures":[75],"missed":[78],"due":[79],"loss":[82],"precision.":[84],"We":[85],"propose":[86],"formal":[88],"basis":[89],"for":[90,96,103],"this":[91],"and":[93],"a":[94],"methodology":[95],"choosing":[97],"granularity":[99],"an":[104],"digital":[108],"setting.":[109]},"counts_by_year":[{"year":2024,"cited_by_count":1}],"updated_date":"2026-06-11T09:08:48.828518","created_date":"2025-10-10T00:00:00"}