{"id":"https://openalex.org/W3136950882","doi":"https://doi.org/10.1109/tcad.2021.3065902","title":"DASS: Combining Dynamic &amp; Static Scheduling in High-Level Synthesis","display_name":"DASS: Combining Dynamic &amp; Static Scheduling in High-Level Synthesis","publication_year":2021,"publication_date":"2021-03-15","ids":{"openalex":"https://openalex.org/W3136950882","doi":"https://doi.org/10.1109/tcad.2021.3065902","mag":"3136950882"},"language":"en","primary_location":{"id":"doi:10.1109/tcad.2021.3065902","is_oa":true,"landing_page_url":"https://doi.org/10.1109/tcad.2021.3065902","pdf_url":"https://ieeexplore.ieee.org/ielx7/43/9716240/09378784.pdf","source":{"id":"https://openalex.org/S100835903","display_name":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","issn_l":"0278-0070","issn":["0278-0070","1937-4151"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":true,"oa_status":"bronze","oa_url":"https://ieeexplore.ieee.org/ielx7/43/9716240/09378784.pdf","any_repository_has_fulltext":true},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5060302344","display_name":"Jianyi Cheng","orcid":"https://orcid.org/0000-0003-2791-2555"},"institutions":[{"id":"https://openalex.org/I47508984","display_name":"Imperial College London","ror":"https://ror.org/041kmwe10","country_code":"GB","type":"education","lineage":["https://openalex.org/I47508984"]}],"countries":["GB"],"is_corresponding":false,"raw_author_name":"Jianyi Cheng","raw_affiliation_strings":["Department of Electrical and Electronic Engineering, Imperial College London, London, U.K"],"raw_orcid":"https://orcid.org/0000-0003-2791-2555","affiliations":[{"raw_affiliation_string":"Department of Electrical and Electronic Engineering, Imperial College London, London, U.K","institution_ids":["https://openalex.org/I47508984"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5030147096","display_name":"Lana Josipovi\u0107","orcid":"https://orcid.org/0000-0001-6659-8533"},"institutions":[{"id":"https://openalex.org/I5124864","display_name":"\u00c9cole Polytechnique F\u00e9d\u00e9rale de Lausanne","ror":"https://ror.org/02s376052","country_code":"CH","type":"education","lineage":["https://openalex.org/I2799323385","https://openalex.org/I5124864"]}],"countries":["CH"],"is_corresponding":false,"raw_author_name":"Lana Josipovic","raw_affiliation_strings":["School of Computer and Communication Sciences, \u00c9cole Polytechnique F\u00e9d\u00e9rale de Lausanne, Lausanne, Switzerland"],"raw_orcid":"https://orcid.org/0000-0001-6659-8533","affiliations":[{"raw_affiliation_string":"School of Computer and Communication Sciences, \u00c9cole Polytechnique F\u00e9d\u00e9rale de Lausanne, Lausanne, Switzerland","institution_ids":["https://openalex.org/I5124864"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5029829952","display_name":"George A. Constantinides","orcid":"https://orcid.org/0000-0002-0201-310X"},"institutions":[{"id":"https://openalex.org/I47508984","display_name":"Imperial College London","ror":"https://ror.org/041kmwe10","country_code":"GB","type":"education","lineage":["https://openalex.org/I47508984"]}],"countries":["GB"],"is_corresponding":false,"raw_author_name":"George A. Constantinides","raw_affiliation_strings":["Department of Electrical and Electronic Engineering, Imperial College London, London, U.K"],"raw_orcid":"https://orcid.org/0000-0002-0201-310X","affiliations":[{"raw_affiliation_string":"Department of Electrical and Electronic Engineering, Imperial College London, London, U.K","institution_ids":["https://openalex.org/I47508984"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5020575991","display_name":"Paolo Ienne","orcid":"https://orcid.org/0000-0002-6142-7345"},"institutions":[{"id":"https://openalex.org/I5124864","display_name":"\u00c9cole Polytechnique F\u00e9d\u00e9rale de Lausanne","ror":"https://ror.org/02s376052","country_code":"CH","type":"education","lineage":["https://openalex.org/I2799323385","https://openalex.org/I5124864"]}],"countries":["CH"],"is_corresponding":false,"raw_author_name":"Paolo Ienne","raw_affiliation_strings":["School of Computer and Communication Sciences, \u00c9cole Polytechnique F\u00e9d\u00e9rale de Lausanne, Lausanne, Switzerland"],"raw_orcid":"https://orcid.org/0000-0002-6142-7345","affiliations":[{"raw_affiliation_string":"School of Computer and Communication Sciences, \u00c9cole Polytechnique F\u00e9d\u00e9rale de Lausanne, Lausanne, Switzerland","institution_ids":["https://openalex.org/I5124864"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5002846450","display_name":"John Wickerson","orcid":"https://orcid.org/0000-0001-6735-5533"},"institutions":[{"id":"https://openalex.org/I47508984","display_name":"Imperial College London","ror":"https://ror.org/041kmwe10","country_code":"GB","type":"education","lineage":["https://openalex.org/I47508984"]}],"countries":["GB"],"is_corresponding":false,"raw_author_name":"John Wickerson","raw_affiliation_strings":["Department of Electrical and Electronic Engineering, Imperial College London, London, U.K"],"raw_orcid":"https://orcid.org/0000-0001-6735-5533","affiliations":[{"raw_affiliation_string":"Department of Electrical and Electronic Engineering, Imperial College London, London, U.K","institution_ids":["https://openalex.org/I47508984"]}]}],"institutions":[],"countries_distinct_count":2,"institutions_distinct_count":2,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":2.2991,"has_fulltext":true,"cited_by_count":21,"citation_normalized_percentile":{"value":0.87736407,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":99},"biblio":{"volume":"41","issue":"3","first_page":"628","last_page":"641"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9988999962806702,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/dataflow","display_name":"Dataflow","score":0.7515075206756592},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7275699377059937},{"id":"https://openalex.org/keywords/scheduling","display_name":"Scheduling (production processes)","score":0.6270154118537903},{"id":"https://openalex.org/keywords/computation","display_name":"Computation","score":0.5167543292045593},{"id":"https://openalex.org/keywords/high-level-synthesis","display_name":"High-level synthesis","score":0.5068212151527405},{"id":"https://openalex.org/keywords/dynamic-priority-scheduling","display_name":"Dynamic priority scheduling","score":0.4309477210044861},{"id":"https://openalex.org/keywords/compiler","display_name":"Compiler","score":0.41952604055404663},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.41880810260772705},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.25670716166496277},{"id":"https://openalex.org/keywords/programming-language","display_name":"Programming language","score":0.19120359420776367},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.18400666117668152},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.16592621803283691},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.13532394170761108},{"id":"https://openalex.org/keywords/mathematical-optimization","display_name":"Mathematical optimization","score":0.1326301395893097},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.11791753768920898}],"concepts":[{"id":"https://openalex.org/C96324660","wikidata":"https://www.wikidata.org/wiki/Q205446","display_name":"Dataflow","level":2,"score":0.7515075206756592},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7275699377059937},{"id":"https://openalex.org/C206729178","wikidata":"https://www.wikidata.org/wiki/Q2271896","display_name":"Scheduling (production processes)","level":2,"score":0.6270154118537903},{"id":"https://openalex.org/C45374587","wikidata":"https://www.wikidata.org/wiki/Q12525525","display_name":"Computation","level":2,"score":0.5167543292045593},{"id":"https://openalex.org/C58013763","wikidata":"https://www.wikidata.org/wiki/Q5754574","display_name":"High-level synthesis","level":3,"score":0.5068212151527405},{"id":"https://openalex.org/C107568181","wikidata":"https://www.wikidata.org/wiki/Q5319000","display_name":"Dynamic priority scheduling","level":3,"score":0.4309477210044861},{"id":"https://openalex.org/C169590947","wikidata":"https://www.wikidata.org/wiki/Q47506","display_name":"Compiler","level":2,"score":0.41952604055404663},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.41880810260772705},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.25670716166496277},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.19120359420776367},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.18400666117668152},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.16592621803283691},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.13532394170761108},{"id":"https://openalex.org/C126255220","wikidata":"https://www.wikidata.org/wiki/Q141495","display_name":"Mathematical optimization","level":1,"score":0.1326301395893097},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.11791753768920898},{"id":"https://openalex.org/C68387754","wikidata":"https://www.wikidata.org/wiki/Q7271585","display_name":"Schedule","level":2,"score":0.0}],"mesh":[],"locations_count":5,"locations":[{"id":"doi:10.1109/tcad.2021.3065902","is_oa":true,"landing_page_url":"https://doi.org/10.1109/tcad.2021.3065902","pdf_url":"https://ieeexplore.ieee.org/ielx7/43/9716240/09378784.pdf","source":{"id":"https://openalex.org/S100835903","display_name":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","issn_l":"0278-0070","issn":["0278-0070","1937-4151"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","raw_type":"journal-article"},{"id":"pmh:oai:pure.ed.ac.uk:publications/2140e93c-856e-4464-bc50-be50740cfcde","is_oa":true,"landing_page_url":"https://hdl.handle.net/20.500.11820/2140e93c-856e-4464-bc50-be50740cfcde","pdf_url":"https://www.research.ed.ac.uk/files/471364362/ChengEtalIEEETCDICS2022DASSCombiningDynamicAndStaticScheduling.pdf","source":{"id":"https://openalex.org/S4406922455","display_name":"Edinburgh Research Explorer","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":null,"host_organization_name":null,"host_organization_lineage":[],"host_organization_lineage_names":[],"type":"repository"},"license":"cc-by-nc-nd","license_id":"https://openalex.org/licenses/cc-by-nc-nd","version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"Cheng, J, Josipovic, L, Constantinides, G A, Ienne, P & Wickerson, J 2021, 'DASS : Combining dynamic static scheduling in high-level synthesis', IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 41, no. 3, pp. 628-641. https://doi.org/10.1109/TCAD.2021.3065902","raw_type":"info:eu-repo/semantics/article"},{"id":"pmh:oai:infoscience.epfl.ch:292702","is_oa":true,"landing_page_url":"https://infoscience.epfl.ch/handle/20.500.14299/186291","pdf_url":null,"source":{"id":"https://openalex.org/S4306400487","display_name":"Infoscience (Ecole Polytechnique F\u00e9d\u00e9rale de Lausanne)","issn_l":null,"issn":null,"is_oa":true,"is_in_doaj":false,"is_core":false,"host_organization":null,"host_organization_name":null,"host_organization_lineage":[],"host_organization_lineage_names":[],"type":"repository"},"license":"cc-by-nc-nd","license_id":"https://openalex.org/licenses/cc-by-nc-nd","version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"WoS","raw_type":"research article"},{"id":"pmh:oai:pure.ed.ac.uk:openaire/2140e93c-856e-4464-bc50-be50740cfcde","is_oa":true,"landing_page_url":"https://www.research.ed.ac.uk/en/publications/2140e93c-856e-4464-bc50-be50740cfcde","pdf_url":null,"source":{"id":"https://openalex.org/S4406922455","display_name":"Edinburgh Research Explorer","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":null,"host_organization_name":null,"host_organization_lineage":[],"host_organization_lineage_names":[],"type":"repository"},"license":"cc-by-nc-nd","license_id":"https://openalex.org/licenses/cc-by-nc-nd","version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"Cheng, J, Josipovic, L, Constantinides, G A, Ienne, P & Wickerson, J 2021, 'DASS : Combining dynamic static scheduling in high-level synthesis', IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 41, no. 3, pp. 628-641. https://doi.org/10.1109/TCAD.2021.3065902","raw_type":"info:eu-repo/semantics/article"},{"id":"pmh:oai:spiral.imperial.ac.uk:10044/1/87618","is_oa":true,"landing_page_url":"http://hdl.handle.net/10044/1/87618","pdf_url":null,"source":{"id":"https://openalex.org/S4306401396","display_name":"Spiral (Imperial College London)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I47508984","host_organization_name":"Imperial College London","host_organization_lineage":["https://openalex.org/I47508984"],"host_organization_lineage_names":[],"type":"repository"},"license":"cc-by-nc-nd","license_id":"https://openalex.org/licenses/cc-by-nc-nd","version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"641","raw_type":"Journal Article"}],"best_oa_location":{"id":"doi:10.1109/tcad.2021.3065902","is_oa":true,"landing_page_url":"https://doi.org/10.1109/tcad.2021.3065902","pdf_url":"https://ieeexplore.ieee.org/ielx7/43/9716240/09378784.pdf","source":{"id":"https://openalex.org/S100835903","display_name":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","issn_l":"0278-0070","issn":["0278-0070","1937-4151"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","raw_type":"journal-article"},"sustainable_development_goals":[],"awards":[{"id":"https://openalex.org/G1641431731","display_name":null,"funder_award_id":"EP/R006865/1","funder_id":"https://openalex.org/F4320334627","funder_display_name":"Engineering and Physical Sciences Research Council"},{"id":"https://openalex.org/G2784140359","display_name":"Application Customisation: Enhancing Design Quality and Developer Productivity","funder_award_id":"EP/P010040/1","funder_id":"https://openalex.org/F4320334627","funder_display_name":"Engineering and Physical Sciences Research Council"},{"id":"https://openalex.org/G6480646621","display_name":"Interface reasoning for interacting systems (IRIS).","funder_award_id":"EP/R006865/1","funder_id":"https://openalex.org/F4320334627","funder_display_name":"Engineering and Physical Sciences Research Council"},{"id":"https://openalex.org/G774180880","display_name":null,"funder_award_id":"EP/P010040/1","funder_id":"https://openalex.org/F4320334627","funder_display_name":"Engineering and Physical Sciences Research Council"},{"id":"https://openalex.org/G8840470266","display_name":null,"funder_award_id":"R006865/1","funder_id":"https://openalex.org/F4320334627","funder_display_name":"Engineering and Physical Sciences Research Council"}],"funders":[{"id":"https://openalex.org/F4320309327","display_name":"Google","ror":"https://ror.org/00njsd438"},{"id":"https://openalex.org/F4320320005","display_name":"Royal Academy of Engineering","ror":"https://ror.org/0526snb40"},{"id":"https://openalex.org/F4320334627","display_name":"Engineering and Physical Sciences Research Council","ror":"https://ror.org/0439y7842"}],"has_content":{"grobid_xml":true,"pdf":true},"content_urls":{"pdf":"https://content.openalex.org/works/W3136950882.pdf","grobid_xml":"https://content.openalex.org/works/W3136950882.grobid-xml"},"referenced_works_count":30,"referenced_works":["https://openalex.org/W1508051931","https://openalex.org/W1521564068","https://openalex.org/W1581408681","https://openalex.org/W1926668751","https://openalex.org/W2018055497","https://openalex.org/W2061988908","https://openalex.org/W2097803659","https://openalex.org/W2102604868","https://openalex.org/W2122078405","https://openalex.org/W2126730305","https://openalex.org/W2133737198","https://openalex.org/W2147088458","https://openalex.org/W2160566592","https://openalex.org/W2171318521","https://openalex.org/W2469322671","https://openalex.org/W2585583922","https://openalex.org/W2760331766","https://openalex.org/W2790678706","https://openalex.org/W2951537853","https://openalex.org/W3003508272","https://openalex.org/W3008119561","https://openalex.org/W3008230609","https://openalex.org/W3008412028","https://openalex.org/W3136950882","https://openalex.org/W4239489018","https://openalex.org/W4253128333","https://openalex.org/W6601865010","https://openalex.org/W6634345303","https://openalex.org/W6634898897","https://openalex.org/W6675548246"],"related_works":["https://openalex.org/W2998381397","https://openalex.org/W4236419692","https://openalex.org/W3167919718","https://openalex.org/W4239447582","https://openalex.org/W2150836909","https://openalex.org/W3206653210","https://openalex.org/W2134941280","https://openalex.org/W2461217932","https://openalex.org/W2531450434","https://openalex.org/W2048159764"],"abstract_inverted_index":{"A":[0],"central":[1],"task":[2],"in":[3,28,52],"high-level":[4],"synthesis":[5],"is":[6,23,32,58,113],"<italic":[7,24,48],"xmlns:mml=\"http://www.w3.org/1998/Math/MathML\"":[8,25,49],"xmlns:xlink=\"http://www.w3.org/1999/xlink\">scheduling</i>":[9],":":[10],"the":[11,45,90,106,116,119,153,156,162,185,201],"allocation":[12],"of":[13,47,108,118,155,164,172,184,200],"operations":[14],"to":[15,21,34,73,86,114,131,196,212],"clock":[16,36,56],"cycles.":[17],"The":[18],"classic":[19],"approach":[20,103],"scheduling":[22,69,82,102],"xmlns:xlink=\"http://www.w3.org/1999/xlink\">static</i>":[26],",":[27],"which":[29,53,158],"each":[30],"operation":[31],"mapped":[33],"a":[35,101,149,170],"cycle":[37,57],"at":[38,61],"compile-time,":[39],"but":[40],"recent":[41],"years":[42],"have":[43,65],"seen":[44],"emergence":[46],"xmlns:xlink=\"http://www.w3.org/1999/xlink\">dynamic</i>":[50],"scheduling,":[51],"an":[54],"operation\u2019s":[55],"only":[59],"determined":[60],"runtime.":[62],"Both":[63],"approaches":[64],"their":[66],"merits:":[67],"static":[68],"(SS)":[70],"can":[71,84,159,181],"lead":[72,85],"simpler":[74],"circuitry":[75],"and":[76,130,198],"more":[77],"resource":[78],"sharing,":[79],"while":[80],"dynamic":[81],"(DS)":[83],"faster":[87],"hardware":[88],"when":[89,147],"computation":[91],"has":[92],"nontrivial":[93],"control":[94],"flow.":[95],"In":[96],"this":[97,178],"work,":[98],"we":[99,180],"seek":[100],"that":[104,175,188,204],"combines":[105],"best":[107],"both":[109],"worlds.":[110],"Our":[111],"idea":[112],"identify":[115],"parts":[117,140],"input":[120],"program,":[121,157],"where":[122],"DS":[123,195],"does":[124],"not":[125],"bring":[126],"any":[127],"performance":[128,202],"advantage":[129],"use":[132],"SS":[133,211],"on":[134,169],"those":[135],"parts.":[136],"These":[137],"statically":[138],"scheduled":[139],"are":[141],"then":[142],"treated":[143],"as":[144],"black":[145],"boxes":[146],"creating":[148],"dataflow":[150],"circuit":[151],"for":[152],"remainder":[154],"benefit":[160],"from":[161,194,210],"flexibility":[163],"DS.":[165,213],"An":[166],"empirical":[167],"evaluation":[168],"range":[171],"applications":[173],"suggests":[174],"by":[176,192,208],"using":[177],"approach,":[179],"obtain":[182],"74%":[183],"area":[186],"savings":[187],"would":[189,205],"be":[190,206],"made":[191,207],"switching":[193,209],"SS,":[197],"135%":[199],"benefits":[203]},"counts_by_year":[{"year":2026,"cited_by_count":4},{"year":2025,"cited_by_count":7},{"year":2024,"cited_by_count":2},{"year":2023,"cited_by_count":6},{"year":2022,"cited_by_count":1},{"year":2021,"cited_by_count":1}],"updated_date":"2026-07-15T18:14:33.161393","created_date":"2025-10-10T00:00:00"}
